1 //===-- SIFixControlFlowLiveIntervals.cpp - Fix CF live intervals ---------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Spilling of EXEC masks used for control flow messes up control flow
12 /// lowering, so mark all live intervals associated with CF instructions as
15 //===----------------------------------------------------------------------===//
18 #include "SIInstrInfo.h"
19 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
20 #include "llvm/CodeGen/MachineFunctionPass.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #define DEBUG_TYPE "si-fix-cf-live-intervals"
29 class SIFixControlFlowLiveIntervals : public MachineFunctionPass {
34 SIFixControlFlowLiveIntervals() : MachineFunctionPass(ID) {
35 initializeSIFixControlFlowLiveIntervalsPass(*PassRegistry::getPassRegistry());
38 bool runOnMachineFunction(MachineFunction &MF) override;
40 StringRef getPassName() const override { return "SI Fix CF Live Intervals"; }
42 void getAnalysisUsage(AnalysisUsage &AU) const override {
43 AU.addRequired<LiveIntervals>();
45 MachineFunctionPass::getAnalysisUsage(AU);
49 } // End anonymous namespace.
51 INITIALIZE_PASS_BEGIN(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
52 "SI Fix CF Live Intervals", false, false)
53 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
54 INITIALIZE_PASS_END(SIFixControlFlowLiveIntervals, DEBUG_TYPE,
55 "SI Fix CF Live Intervals", false, false)
57 char SIFixControlFlowLiveIntervals::ID = 0;
59 char &llvm::SIFixControlFlowLiveIntervalsID = SIFixControlFlowLiveIntervals::ID;
61 FunctionPass *llvm::createSIFixControlFlowLiveIntervalsPass() {
62 return new SIFixControlFlowLiveIntervals();
65 bool SIFixControlFlowLiveIntervals::runOnMachineFunction(MachineFunction &MF) {
66 LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
68 for (const MachineBasicBlock &MBB : MF) {
69 for (const MachineInstr &MI : MBB) {
70 switch (MI.getOpcode()) {
73 case AMDGPU::SI_BREAK:
74 case AMDGPU::SI_IF_BREAK:
75 case AMDGPU::SI_ELSE_BREAK:
76 case AMDGPU::SI_END_CF: {
77 unsigned Reg = MI.getOperand(0).getReg();
78 LIS->getInterval(Reg).markNotSpillable();