1 //===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// Add implicit use of exec to vector register copies.
13 //===----------------------------------------------------------------------===//
16 #include "AMDGPUSubtarget.h"
17 #include "SIInstrInfo.h"
18 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
19 #include "llvm/CodeGen/MachineFunctionPass.h"
23 #define DEBUG_TYPE "si-fix-vgpr-copies"
27 class SIFixVGPRCopies : public MachineFunctionPass {
32 SIFixVGPRCopies() : MachineFunctionPass(ID) {
33 initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
36 bool runOnMachineFunction(MachineFunction &MF) override;
38 StringRef getPassName() const override { return "SI Fix VGPR copies"; }
41 } // End anonymous namespace.
43 INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
45 char SIFixVGPRCopies::ID = 0;
47 char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
49 bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
50 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
51 const SIRegisterInfo *TRI = ST.getRegisterInfo();
52 const SIInstrInfo *TII = ST.getInstrInfo();
55 for (MachineBasicBlock &MBB : MF) {
56 for (MachineInstr &MI : MBB) {
57 switch (MI.getOpcode()) {
59 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
61 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
62 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);