1 //===-- SIFoldOperands.cpp - Fold operands --- ----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
9 //===----------------------------------------------------------------------===//
13 #include "AMDGPUSubtarget.h"
14 #include "SIInstrInfo.h"
15 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
16 #include "llvm/CodeGen/MachineFunctionPass.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
19 #include "llvm/Support/Debug.h"
20 #include "llvm/Support/raw_ostream.h"
21 #include "llvm/Target/TargetMachine.h"
23 #define DEBUG_TYPE "si-fold-operands"
28 struct FoldCandidate {
31 MachineOperand *OpToFold;
35 unsigned char UseOpNo;
36 MachineOperand::MachineOperandType Kind;
38 FoldCandidate(MachineInstr *MI, unsigned OpNo, MachineOperand *FoldOp) :
39 UseMI(MI), OpToFold(nullptr), UseOpNo(OpNo), Kind(FoldOp->getType()) {
40 if (FoldOp->isImm()) {
41 ImmToFold = FoldOp->getImm();
42 } else if (FoldOp->isFI()) {
43 FrameIndexToFold = FoldOp->getIndex();
45 assert(FoldOp->isReg());
51 return Kind == MachineOperand::MO_FrameIndex;
55 return Kind == MachineOperand::MO_Immediate;
59 return Kind == MachineOperand::MO_Register;
63 class SIFoldOperands : public MachineFunctionPass {
66 MachineRegisterInfo *MRI;
67 const SIInstrInfo *TII;
68 const SIRegisterInfo *TRI;
70 void foldOperand(MachineOperand &OpToFold,
73 SmallVectorImpl<FoldCandidate> &FoldList,
74 SmallVectorImpl<MachineInstr *> &CopiesToReplace) const;
76 void foldInstOperand(MachineInstr &MI, MachineOperand &OpToFold) const;
79 SIFoldOperands() : MachineFunctionPass(ID) {
80 initializeSIFoldOperandsPass(*PassRegistry::getPassRegistry());
83 bool runOnMachineFunction(MachineFunction &MF) override;
85 StringRef getPassName() const override { return "SI Fold Operands"; }
87 void getAnalysisUsage(AnalysisUsage &AU) const override {
89 MachineFunctionPass::getAnalysisUsage(AU);
93 } // End anonymous namespace.
95 INITIALIZE_PASS(SIFoldOperands, DEBUG_TYPE,
96 "SI Fold Operands", false, false)
98 char SIFoldOperands::ID = 0;
100 char &llvm::SIFoldOperandsID = SIFoldOperands::ID;
102 // Wrapper around isInlineConstant that understands special cases when
103 // instruction types are replaced during operand folding.
104 static bool isInlineConstantIfFolded(const SIInstrInfo *TII,
105 const MachineInstr &UseMI,
107 const MachineOperand &OpToFold) {
108 if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
111 unsigned Opc = UseMI.getOpcode();
113 case AMDGPU::V_MAC_F32_e64:
114 case AMDGPU::V_MAC_F16_e64: {
115 // Special case for mac. Since this is replaced with mad when folded into
116 // src2, we need to check the legality for the final instruction.
117 int Src2Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2);
118 if (static_cast<int>(OpNo) == Src2Idx) {
119 bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64;
120 const MCInstrDesc &MadDesc
121 = TII->get(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16);
122 return TII->isInlineConstant(OpToFold, MadDesc.OpInfo[OpNo].OperandType);
130 FunctionPass *llvm::createSIFoldOperandsPass() {
131 return new SIFoldOperands();
134 static bool isSafeToFold(const MachineInstr &MI) {
135 switch (MI.getOpcode()) {
136 case AMDGPU::V_MOV_B32_e32:
137 case AMDGPU::V_MOV_B32_e64:
138 case AMDGPU::V_MOV_B64_PSEUDO: {
139 // If there are additional implicit register operands, this may be used for
140 // register indexing so the source register operand isn't simply copied.
141 unsigned NumOps = MI.getDesc().getNumOperands() +
142 MI.getDesc().getNumImplicitUses();
144 return MI.getNumOperands() == NumOps;
146 case AMDGPU::S_MOV_B32:
147 case AMDGPU::S_MOV_B64:
155 static bool updateOperand(FoldCandidate &Fold,
156 const TargetRegisterInfo &TRI) {
157 MachineInstr *MI = Fold.UseMI;
158 MachineOperand &Old = MI->getOperand(Fold.UseOpNo);
162 Old.ChangeToImmediate(Fold.ImmToFold);
167 Old.ChangeToFrameIndex(Fold.FrameIndexToFold);
171 MachineOperand *New = Fold.OpToFold;
172 if (TargetRegisterInfo::isVirtualRegister(Old.getReg()) &&
173 TargetRegisterInfo::isVirtualRegister(New->getReg())) {
174 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
178 // FIXME: Handle physical registers.
183 static bool isUseMIInFoldList(ArrayRef<FoldCandidate> FoldList,
184 const MachineInstr *MI) {
185 for (auto Candidate : FoldList) {
186 if (Candidate.UseMI == MI)
192 static bool tryAddToFoldList(SmallVectorImpl<FoldCandidate> &FoldList,
193 MachineInstr *MI, unsigned OpNo,
194 MachineOperand *OpToFold,
195 const SIInstrInfo *TII) {
196 if (!TII->isOperandLegal(*MI, OpNo, OpToFold)) {
198 // Special case for v_mac_{f16, f32}_e64 if we are trying to fold into src2
199 unsigned Opc = MI->getOpcode();
200 if ((Opc == AMDGPU::V_MAC_F32_e64 || Opc == AMDGPU::V_MAC_F16_e64) &&
201 (int)OpNo == AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2)) {
202 bool IsF32 = Opc == AMDGPU::V_MAC_F32_e64;
204 // Check if changing this to a v_mad_{f16, f32} instruction will allow us
205 // to fold the operand.
206 MI->setDesc(TII->get(IsF32 ? AMDGPU::V_MAD_F32 : AMDGPU::V_MAD_F16));
207 bool FoldAsMAD = tryAddToFoldList(FoldList, MI, OpNo, OpToFold, TII);
209 MI->untieRegOperand(OpNo);
212 MI->setDesc(TII->get(Opc));
215 // Special case for s_setreg_b32
216 if (Opc == AMDGPU::S_SETREG_B32 && OpToFold->isImm()) {
217 MI->setDesc(TII->get(AMDGPU::S_SETREG_IMM32_B32));
218 FoldList.push_back(FoldCandidate(MI, OpNo, OpToFold));
222 // If we are already folding into another operand of MI, then
223 // we can't commute the instruction, otherwise we risk making the
224 // other fold illegal.
225 if (isUseMIInFoldList(FoldList, MI))
228 // Operand is not legal, so try to commute the instruction to
229 // see if this makes it possible to fold.
230 unsigned CommuteIdx0 = TargetInstrInfo::CommuteAnyOperandIndex;
231 unsigned CommuteIdx1 = TargetInstrInfo::CommuteAnyOperandIndex;
232 bool CanCommute = TII->findCommutedOpIndices(*MI, CommuteIdx0, CommuteIdx1);
235 if (CommuteIdx0 == OpNo)
237 else if (CommuteIdx1 == OpNo)
241 // One of operands might be an Imm operand, and OpNo may refer to it after
242 // the call of commuteInstruction() below. Such situations are avoided
243 // here explicitly as OpNo must be a register operand to be a candidate
244 // for memory folding.
245 if (CanCommute && (!MI->getOperand(CommuteIdx0).isReg() ||
246 !MI->getOperand(CommuteIdx1).isReg()))
250 !TII->commuteInstruction(*MI, false, CommuteIdx0, CommuteIdx1))
253 if (!TII->isOperandLegal(*MI, OpNo, OpToFold))
257 FoldList.push_back(FoldCandidate(MI, OpNo, OpToFold));
261 // If the use operand doesn't care about the value, this may be an operand only
262 // used for register indexing, in which case it is unsafe to fold.
263 static bool isUseSafeToFold(const MachineInstr &MI,
264 const MachineOperand &UseMO) {
265 return !UseMO.isUndef();
266 //return !MI.hasRegisterImplicitUseOperand(UseMO.getReg());
269 void SIFoldOperands::foldOperand(
270 MachineOperand &OpToFold,
273 SmallVectorImpl<FoldCandidate> &FoldList,
274 SmallVectorImpl<MachineInstr *> &CopiesToReplace) const {
275 const MachineOperand &UseOp = UseMI->getOperand(UseOpIdx);
277 if (!isUseSafeToFold(*UseMI, UseOp))
280 // FIXME: Fold operands with subregs.
281 if (UseOp.isReg() && OpToFold.isReg()) {
282 if (UseOp.isImplicit() || UseOp.getSubReg() != AMDGPU::NoSubRegister)
285 // Don't fold subregister extracts into tied operands, only if it is a full
286 // copy since a subregister use tied to a full register def doesn't really
287 // make sense. e.g. don't fold:
289 // %vreg1 = COPY %vreg0:sub1
290 // %vreg2<tied3> = V_MAC_{F16, F32} %vreg3, %vreg4, %vreg1<tied0>
293 // %vreg2<tied3> = V_MAC_{F16, F32} %vreg3, %vreg4, %vreg0:sub1<tied0>
294 if (UseOp.isTied() && OpToFold.getSubReg() != AMDGPU::NoSubRegister)
298 // Special case for REG_SEQUENCE: We can't fold literals into
299 // REG_SEQUENCE instructions, so we have to fold them into the
300 // uses of REG_SEQUENCE.
301 if (UseMI->isRegSequence()) {
302 unsigned RegSeqDstReg = UseMI->getOperand(0).getReg();
303 unsigned RegSeqDstSubReg = UseMI->getOperand(UseOpIdx + 1).getImm();
305 for (MachineRegisterInfo::use_iterator
306 RSUse = MRI->use_begin(RegSeqDstReg), RSE = MRI->use_end();
307 RSUse != RSE; ++RSUse) {
309 MachineInstr *RSUseMI = RSUse->getParent();
310 if (RSUse->getSubReg() != RegSeqDstSubReg)
313 foldOperand(OpToFold, RSUseMI, RSUse.getOperandNo(), FoldList,
321 bool FoldingImm = OpToFold.isImm();
323 // In order to fold immediates into copies, we need to change the
325 if (FoldingImm && UseMI->isCopy()) {
326 unsigned DestReg = UseMI->getOperand(0).getReg();
327 const TargetRegisterClass *DestRC
328 = TargetRegisterInfo::isVirtualRegister(DestReg) ?
329 MRI->getRegClass(DestReg) :
330 TRI->getPhysRegClass(DestReg);
332 unsigned MovOp = TII->getMovOpcode(DestRC);
333 if (MovOp == AMDGPU::COPY)
336 UseMI->setDesc(TII->get(MovOp));
337 CopiesToReplace.push_back(UseMI);
339 const MCInstrDesc &UseDesc = UseMI->getDesc();
341 // Don't fold into target independent nodes. Target independent opcodes
342 // don't have defined register classes.
343 if (UseDesc.isVariadic() ||
344 UseDesc.OpInfo[UseOpIdx].RegClass == -1)
349 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &OpToFold, TII);
351 // FIXME: We could try to change the instruction from 64-bit to 32-bit
352 // to enable more folding opportunites. The shrink operands pass
353 // already does this.
358 const MCInstrDesc &FoldDesc = OpToFold.getParent()->getDesc();
359 const TargetRegisterClass *FoldRC =
360 TRI->getRegClass(FoldDesc.OpInfo[0].RegClass);
362 APInt Imm(TII->operandBitWidth(FoldDesc.OpInfo[1].OperandType),
365 // Split 64-bit constants into 32-bits for folding.
366 if (UseOp.getSubReg() && AMDGPU::getRegBitWidth(FoldRC->getID()) == 64) {
367 unsigned UseReg = UseOp.getReg();
368 const TargetRegisterClass *UseRC
369 = TargetRegisterInfo::isVirtualRegister(UseReg) ?
370 MRI->getRegClass(UseReg) :
371 TRI->getPhysRegClass(UseReg);
373 assert(Imm.getBitWidth() == 64);
375 if (AMDGPU::getRegBitWidth(UseRC->getID()) != 64)
378 if (UseOp.getSubReg() == AMDGPU::sub0) {
379 Imm = Imm.getLoBits(32);
381 assert(UseOp.getSubReg() == AMDGPU::sub1);
382 Imm = Imm.getHiBits(32);
386 MachineOperand ImmOp = MachineOperand::CreateImm(Imm.getSExtValue());
387 tryAddToFoldList(FoldList, UseMI, UseOpIdx, &ImmOp, TII);
390 static bool evalBinaryInstruction(unsigned Opcode, int32_t &Result,
391 uint32_t LHS, uint32_t RHS) {
393 case AMDGPU::V_AND_B32_e64:
394 case AMDGPU::V_AND_B32_e32:
395 case AMDGPU::S_AND_B32:
398 case AMDGPU::V_OR_B32_e64:
399 case AMDGPU::V_OR_B32_e32:
400 case AMDGPU::S_OR_B32:
403 case AMDGPU::V_XOR_B32_e64:
404 case AMDGPU::V_XOR_B32_e32:
405 case AMDGPU::S_XOR_B32:
408 case AMDGPU::V_LSHL_B32_e64:
409 case AMDGPU::V_LSHL_B32_e32:
410 case AMDGPU::S_LSHL_B32:
411 // The instruction ignores the high bits for out of bounds shifts.
412 Result = LHS << (RHS & 31);
414 case AMDGPU::V_LSHLREV_B32_e64:
415 case AMDGPU::V_LSHLREV_B32_e32:
416 Result = RHS << (LHS & 31);
418 case AMDGPU::V_LSHR_B32_e64:
419 case AMDGPU::V_LSHR_B32_e32:
420 case AMDGPU::S_LSHR_B32:
421 Result = LHS >> (RHS & 31);
423 case AMDGPU::V_LSHRREV_B32_e64:
424 case AMDGPU::V_LSHRREV_B32_e32:
425 Result = RHS >> (LHS & 31);
427 case AMDGPU::V_ASHR_I32_e64:
428 case AMDGPU::V_ASHR_I32_e32:
429 case AMDGPU::S_ASHR_I32:
430 Result = static_cast<int32_t>(LHS) >> (RHS & 31);
432 case AMDGPU::V_ASHRREV_I32_e64:
433 case AMDGPU::V_ASHRREV_I32_e32:
434 Result = static_cast<int32_t>(RHS) >> (LHS & 31);
441 static unsigned getMovOpc(bool IsScalar) {
442 return IsScalar ? AMDGPU::S_MOV_B32 : AMDGPU::V_MOV_B32_e32;
445 /// Remove any leftover implicit operands from mutating the instruction. e.g.
446 /// if we replace an s_and_b32 with a copy, we don't need the implicit scc def
448 static void stripExtraCopyOperands(MachineInstr &MI) {
449 const MCInstrDesc &Desc = MI.getDesc();
450 unsigned NumOps = Desc.getNumOperands() +
451 Desc.getNumImplicitUses() +
452 Desc.getNumImplicitDefs();
454 for (unsigned I = MI.getNumOperands() - 1; I >= NumOps; --I)
458 static void mutateCopyOp(MachineInstr &MI, const MCInstrDesc &NewDesc) {
460 stripExtraCopyOperands(MI);
463 static MachineOperand *getImmOrMaterializedImm(MachineRegisterInfo &MRI,
464 MachineOperand &Op) {
466 // If this has a subregister, it obviously is a register source.
467 if (Op.getSubReg() != AMDGPU::NoSubRegister)
470 MachineInstr *Def = MRI.getVRegDef(Op.getReg());
471 if (Def->isMoveImmediate()) {
472 MachineOperand &ImmSrc = Def->getOperand(1);
481 // Try to simplify operations with a constant that may appear after instruction
483 // TODO: See if a frame index with a fixed offset can fold.
484 static bool tryConstantFoldOp(MachineRegisterInfo &MRI,
485 const SIInstrInfo *TII,
487 MachineOperand *ImmOp) {
488 unsigned Opc = MI->getOpcode();
489 if (Opc == AMDGPU::V_NOT_B32_e64 || Opc == AMDGPU::V_NOT_B32_e32 ||
490 Opc == AMDGPU::S_NOT_B32) {
491 MI->getOperand(1).ChangeToImmediate(~ImmOp->getImm());
492 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_NOT_B32)));
496 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
500 int Src0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0);
501 MachineOperand *Src0 = getImmOrMaterializedImm(MRI, MI->getOperand(Src0Idx));
502 MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
504 if (!Src0->isImm() && !Src1->isImm())
507 // and k0, k1 -> v_mov_b32 (k0 & k1)
508 // or k0, k1 -> v_mov_b32 (k0 | k1)
509 // xor k0, k1 -> v_mov_b32 (k0 ^ k1)
510 if (Src0->isImm() && Src1->isImm()) {
512 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
515 const SIRegisterInfo &TRI = TII->getRegisterInfo();
516 bool IsSGPR = TRI.isSGPRReg(MRI, MI->getOperand(0).getReg());
518 // Be careful to change the right operand, src0 may belong to a different
520 MI->getOperand(Src0Idx).ChangeToImmediate(NewImm);
521 MI->RemoveOperand(Src1Idx);
522 mutateCopyOp(*MI, TII->get(getMovOpc(IsSGPR)));
526 if (!MI->isCommutable())
529 if (Src0->isImm() && !Src1->isImm()) {
530 std::swap(Src0, Src1);
531 std::swap(Src0Idx, Src1Idx);
534 int32_t Src1Val = static_cast<int32_t>(Src1->getImm());
535 if (Opc == AMDGPU::V_OR_B32_e64 ||
536 Opc == AMDGPU::V_OR_B32_e32 ||
537 Opc == AMDGPU::S_OR_B32) {
539 // y = or x, 0 => y = copy x
540 MI->RemoveOperand(Src1Idx);
541 mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
542 } else if (Src1Val == -1) {
543 // y = or x, -1 => y = v_mov_b32 -1
544 MI->RemoveOperand(Src1Idx);
545 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_OR_B32)));
552 if (MI->getOpcode() == AMDGPU::V_AND_B32_e64 ||
553 MI->getOpcode() == AMDGPU::V_AND_B32_e32 ||
554 MI->getOpcode() == AMDGPU::S_AND_B32) {
556 // y = and x, 0 => y = v_mov_b32 0
557 MI->RemoveOperand(Src0Idx);
558 mutateCopyOp(*MI, TII->get(getMovOpc(Opc == AMDGPU::S_AND_B32)));
559 } else if (Src1Val == -1) {
560 // y = and x, -1 => y = copy x
561 MI->RemoveOperand(Src1Idx);
562 mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
563 stripExtraCopyOperands(*MI);
570 if (MI->getOpcode() == AMDGPU::V_XOR_B32_e64 ||
571 MI->getOpcode() == AMDGPU::V_XOR_B32_e32 ||
572 MI->getOpcode() == AMDGPU::S_XOR_B32) {
574 // y = xor x, 0 => y = copy x
575 MI->RemoveOperand(Src1Idx);
576 mutateCopyOp(*MI, TII->get(AMDGPU::COPY));
584 void SIFoldOperands::foldInstOperand(MachineInstr &MI,
585 MachineOperand &OpToFold) const {
586 // We need mutate the operands of new mov instructions to add implicit
587 // uses of EXEC, but adding them invalidates the use_iterator, so defer
589 SmallVector<MachineInstr *, 4> CopiesToReplace;
590 SmallVector<FoldCandidate, 4> FoldList;
591 MachineOperand &Dst = MI.getOperand(0);
593 bool FoldingImm = OpToFold.isImm() || OpToFold.isFI();
595 unsigned NumLiteralUses = 0;
596 MachineOperand *NonInlineUse = nullptr;
597 int NonInlineUseOpNo = -1;
599 MachineRegisterInfo::use_iterator NextUse, NextInstUse;
600 for (MachineRegisterInfo::use_iterator
601 Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
602 Use != E; Use = NextUse) {
603 NextUse = std::next(Use);
604 MachineInstr *UseMI = Use->getParent();
605 unsigned OpNo = Use.getOperandNo();
607 // Folding the immediate may reveal operations that can be constant
608 // folded or replaced with a copy. This can happen for example after
609 // frame indices are lowered to constants or from splitting 64-bit
612 // We may also encounter cases where one or both operands are
613 // immediates materialized into a register, which would ordinarily not
614 // be folded due to multiple uses or operand constraints.
616 if (OpToFold.isImm() && tryConstantFoldOp(*MRI, TII, UseMI, &OpToFold)) {
617 DEBUG(dbgs() << "Constant folded " << *UseMI <<'\n');
619 // Some constant folding cases change the same immediate's use to a new
620 // instruction, e.g. and x, 0 -> 0. Make sure we re-visit the user
621 // again. The same constant folded instruction could also have a second
623 NextUse = MRI->use_begin(Dst.getReg());
627 // Try to fold any inline immediate uses, and then only fold other
628 // constants if they have one use.
630 // The legality of the inline immediate must be checked based on the use
631 // operand, not the defining instruction, because 32-bit instructions
632 // with 32-bit inline immediate sources may be used to materialize
633 // constants used in 16-bit operands.
635 // e.g. it is unsafe to fold:
636 // s_mov_b32 s0, 1.0 // materializes 0x3f800000
637 // v_add_f16 v0, v1, s0 // 1.0 f16 inline immediate sees 0x00003c00
639 // Folding immediates with more than one use will increase program size.
640 // FIXME: This will also reduce register usage, which may be better
641 // in some cases. A better heuristic is needed.
642 if (isInlineConstantIfFolded(TII, *UseMI, OpNo, OpToFold)) {
643 foldOperand(OpToFold, UseMI, OpNo, FoldList, CopiesToReplace);
645 if (++NumLiteralUses == 1) {
646 NonInlineUse = &*Use;
647 NonInlineUseOpNo = OpNo;
652 if (NumLiteralUses == 1) {
653 MachineInstr *UseMI = NonInlineUse->getParent();
654 foldOperand(OpToFold, UseMI, NonInlineUseOpNo, FoldList, CopiesToReplace);
658 for (MachineRegisterInfo::use_iterator
659 Use = MRI->use_begin(Dst.getReg()), E = MRI->use_end();
661 MachineInstr *UseMI = Use->getParent();
663 foldOperand(OpToFold, UseMI, Use.getOperandNo(),
664 FoldList, CopiesToReplace);
668 MachineFunction *MF = MI.getParent()->getParent();
669 // Make sure we add EXEC uses to any new v_mov instructions created.
670 for (MachineInstr *Copy : CopiesToReplace)
671 Copy->addImplicitDefUseOperands(*MF);
673 for (FoldCandidate &Fold : FoldList) {
674 if (updateOperand(Fold, *TRI)) {
677 assert(Fold.OpToFold && Fold.OpToFold->isReg());
678 // FIXME: Probably shouldn't bother trying to fold if not an
679 // SGPR. PeepholeOptimizer can eliminate redundant VGPR->VGPR
681 MRI->clearKillFlags(Fold.OpToFold->getReg());
683 DEBUG(dbgs() << "Folded source from " << MI << " into OpNo " <<
684 static_cast<int>(Fold.UseOpNo) << " of " << *Fold.UseMI << '\n');
689 bool SIFoldOperands::runOnMachineFunction(MachineFunction &MF) {
690 if (skipFunction(*MF.getFunction()))
693 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
695 MRI = &MF.getRegInfo();
696 TII = ST.getInstrInfo();
697 TRI = &TII->getRegisterInfo();
699 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
702 MachineBasicBlock &MBB = *BI;
703 MachineBasicBlock::iterator I, Next;
704 for (I = MBB.begin(); I != MBB.end(); I = Next) {
706 MachineInstr &MI = *I;
708 if (!isSafeToFold(MI))
711 MachineOperand &OpToFold = MI.getOperand(1);
712 bool FoldingImm = OpToFold.isImm() || OpToFold.isFI();
714 // FIXME: We could also be folding things like TargetIndexes.
715 if (!FoldingImm && !OpToFold.isReg())
718 if (OpToFold.isReg() &&
719 !TargetRegisterInfo::isVirtualRegister(OpToFold.getReg()))
722 // Prevent folding operands backwards in the function. For example,
723 // the COPY opcode must not be replaced by 1 in this example:
725 // %vreg3<def> = COPY %VGPR0; VGPR_32:%vreg3
727 // %VGPR0<def> = V_MOV_B32_e32 1, %EXEC<imp-use>
728 MachineOperand &Dst = MI.getOperand(0);
730 !TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
733 foldInstOperand(MI, OpToFold);