1 //===----------------------- SIFrameLowering.cpp --------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //==-----------------------------------------------------------------------===//
10 #include "SIFrameLowering.h"
11 #include "SIInstrInfo.h"
12 #include "SIMachineFunctionInfo.h"
13 #include "SIRegisterInfo.h"
14 #include "AMDGPUSubtarget.h"
16 #include "llvm/CodeGen/MachineFrameInfo.h"
17 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/MachineInstrBuilder.h"
19 #include "llvm/CodeGen/RegisterScavenging.h"
24 static ArrayRef<MCPhysReg> getAllSGPR128(const SISubtarget &ST,
25 const MachineFunction &MF) {
26 return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
27 ST.getMaxNumSGPRs(MF) / 4);
30 static ArrayRef<MCPhysReg> getAllSGPRs(const SISubtarget &ST,
31 const MachineFunction &MF) {
32 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(),
33 ST.getMaxNumSGPRs(MF));
36 void SIFrameLowering::emitFlatScratchInit(const SISubtarget &ST,
38 MachineBasicBlock &MBB) const {
39 const SIInstrInfo *TII = ST.getInstrInfo();
40 const SIRegisterInfo* TRI = &TII->getRegisterInfo();
42 // We don't need this if we only have spills since there is no user facing
45 // TODO: If we know we don't have flat instructions earlier, we can omit
46 // this from the input registers.
48 // TODO: We only need to know if we access scratch space through a flat
49 // pointer. Because we only detect if flat instructions are used at all,
50 // this will be used more often than necessary on VI.
52 // Debug location must be unknown since the first debug location is used to
53 // determine the end of the prologue.
55 MachineBasicBlock::iterator I = MBB.begin();
57 unsigned FlatScratchInitReg
58 = TRI->getPreloadedValue(MF, SIRegisterInfo::FLAT_SCRATCH_INIT);
60 MachineRegisterInfo &MRI = MF.getRegInfo();
61 MRI.addLiveIn(FlatScratchInitReg);
62 MBB.addLiveIn(FlatScratchInitReg);
64 unsigned FlatScrInitLo = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub0);
65 unsigned FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1);
67 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
68 unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
70 // Do a 64-bit pointer add.
71 if (ST.flatScratchIsPointer()) {
72 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), AMDGPU::FLAT_SCR_LO)
73 .addReg(FlatScrInitLo)
74 .addReg(ScratchWaveOffsetReg);
75 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADDC_U32), AMDGPU::FLAT_SCR_HI)
76 .addReg(FlatScrInitHi)
82 // Copy the size in bytes.
83 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), AMDGPU::FLAT_SCR_LO)
84 .addReg(FlatScrInitHi, RegState::Kill);
86 // Add wave offset in bytes to private base offset.
87 // See comment in AMDKernelCodeT.h for enable_sgpr_flat_scratch_init.
88 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_ADD_U32), FlatScrInitLo)
89 .addReg(FlatScrInitLo)
90 .addReg(ScratchWaveOffsetReg);
92 // Convert offset to 256-byte units.
93 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_LSHR_B32), AMDGPU::FLAT_SCR_HI)
94 .addReg(FlatScrInitLo, RegState::Kill)
98 unsigned SIFrameLowering::getReservedPrivateSegmentBufferReg(
99 const SISubtarget &ST,
100 const SIInstrInfo *TII,
101 const SIRegisterInfo *TRI,
102 SIMachineFunctionInfo *MFI,
103 MachineFunction &MF) const {
104 MachineRegisterInfo &MRI = MF.getRegInfo();
106 // We need to insert initialization of the scratch resource descriptor.
107 unsigned ScratchRsrcReg = MFI->getScratchRSrcReg();
108 if (ScratchRsrcReg == AMDGPU::NoRegister ||
109 !MRI.isPhysRegUsed(ScratchRsrcReg))
110 return AMDGPU::NoRegister;
112 if (ST.hasSGPRInitBug() ||
113 ScratchRsrcReg != TRI->reservedPrivateSegmentBufferReg(MF))
114 return ScratchRsrcReg;
116 // We reserved the last registers for this. Shift it down to the end of those
117 // which were actually used.
119 // FIXME: It might be safer to use a pseudoregister before replacement.
121 // FIXME: We should be able to eliminate unused input registers. We only
122 // cannot do this for the resources required for scratch access. For now we
123 // skip over user SGPRs and may leave unused holes.
125 // We find the resource first because it has an alignment requirement.
127 unsigned NumPreloaded = (MFI->getNumPreloadedSGPRs() + 3) / 4;
128 ArrayRef<MCPhysReg> AllSGPR128s = getAllSGPR128(ST, MF);
129 AllSGPR128s = AllSGPR128s.slice(std::min(static_cast<unsigned>(AllSGPR128s.size()), NumPreloaded));
131 // Skip the last N reserved elements because they should have already been
132 // reserved for VCC etc.
133 for (MCPhysReg Reg : AllSGPR128s) {
134 // Pick the first unallocated one. Make sure we don't clobber the other
135 // reserved input we needed.
136 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) {
137 MRI.replaceRegWith(ScratchRsrcReg, Reg);
138 MFI->setScratchRSrcReg(Reg);
143 return ScratchRsrcReg;
146 // Shift down registers reserved for the scratch wave offset and stack pointer
148 std::pair<unsigned, unsigned>
149 SIFrameLowering::getReservedPrivateSegmentWaveByteOffsetReg(
150 const SISubtarget &ST,
151 const SIInstrInfo *TII,
152 const SIRegisterInfo *TRI,
153 SIMachineFunctionInfo *MFI,
154 MachineFunction &MF) const {
155 MachineRegisterInfo &MRI = MF.getRegInfo();
156 unsigned ScratchWaveOffsetReg = MFI->getScratchWaveOffsetReg();
158 // No replacement necessary.
159 if (ScratchWaveOffsetReg == AMDGPU::NoRegister ||
160 !MRI.isPhysRegUsed(ScratchWaveOffsetReg)) {
161 assert(MFI->getStackPtrOffsetReg() == AMDGPU::NoRegister);
162 return std::make_pair(AMDGPU::NoRegister, AMDGPU::NoRegister);
165 unsigned SPReg = MFI->getStackPtrOffsetReg();
166 if (ST.hasSGPRInitBug())
167 return std::make_pair(ScratchWaveOffsetReg, SPReg);
169 unsigned NumPreloaded = MFI->getNumPreloadedSGPRs();
171 ArrayRef<MCPhysReg> AllSGPRs = getAllSGPRs(ST, MF);
172 if (NumPreloaded > AllSGPRs.size())
173 return std::make_pair(ScratchWaveOffsetReg, SPReg);
175 AllSGPRs = AllSGPRs.slice(NumPreloaded);
177 // We need to drop register from the end of the list that we cannot use
178 // for the scratch wave offset.
179 // + 2 s102 and s103 do not exist on VI.
181 // + 2 for xnack_mask
182 // + 2 for flat_scratch
183 // + 4 for registers reserved for scratch resource register
184 // + 1 for register reserved for scratch wave offset. (By exluding this
185 // register from the list to consider, it means that when this
186 // register is being used for the scratch wave offset and there
187 // are no other free SGPRs, then the value will stay in this register.
188 // + 1 if stack pointer is used.
191 unsigned ReservedRegCount = 13;
192 if (SPReg != AMDGPU::NoRegister)
195 if (AllSGPRs.size() < ReservedRegCount)
196 return std::make_pair(ScratchWaveOffsetReg, SPReg);
198 bool HandledScratchWaveOffsetReg =
199 ScratchWaveOffsetReg != TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
201 for (MCPhysReg Reg : AllSGPRs.drop_back(ReservedRegCount)) {
202 // Pick the first unallocated SGPR. Be careful not to pick an alias of the
203 // scratch descriptor, since we haven’t added its uses yet.
204 if (!MRI.isPhysRegUsed(Reg) && MRI.isAllocatable(Reg)) {
205 if (!HandledScratchWaveOffsetReg) {
206 HandledScratchWaveOffsetReg = true;
208 MRI.replaceRegWith(ScratchWaveOffsetReg, Reg);
209 MFI->setScratchWaveOffsetReg(Reg);
210 ScratchWaveOffsetReg = Reg;
212 if (SPReg == AMDGPU::NoRegister)
215 MRI.replaceRegWith(SPReg, Reg);
216 MFI->setStackPtrOffsetReg(Reg);
223 return std::make_pair(ScratchWaveOffsetReg, SPReg);
226 void SIFrameLowering::emitPrologue(MachineFunction &MF,
227 MachineBasicBlock &MBB) const {
228 // Emit debugger prologue if "amdgpu-debugger-emit-prologue" attribute was
230 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
231 auto AMDGPUASI = ST.getAMDGPUAS();
232 if (ST.debuggerEmitPrologue())
233 emitDebuggerPrologue(MF, MBB);
235 assert(&MF.front() == &MBB && "Shrink-wrapping not yet supported");
237 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
239 // If we only have SGPR spills, we won't actually be using scratch memory
240 // since these spill to VGPRs.
242 // FIXME: We should be cleaning up these unused SGPR spill frame indices
245 const SIInstrInfo *TII = ST.getInstrInfo();
246 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
247 MachineRegisterInfo &MRI = MF.getRegInfo();
249 // We need to do the replacement of the private segment buffer and wave offset
250 // register even if there are no stack objects. There could be stores to undef
251 // or a constant without an associated object.
253 // FIXME: We still have implicit uses on SGPR spill instructions in case they
254 // need to spill to vector memory. It's likely that will not happen, but at
255 // this point it appears we need the setup. This part of the prolog should be
256 // emitted after frame indices are eliminated.
258 if (MF.getFrameInfo().hasStackObjects() && MFI->hasFlatScratchInit())
259 emitFlatScratchInit(ST, MF, MBB);
261 unsigned SPReg = MFI->getStackPtrOffsetReg();
262 if (SPReg != AMDGPU::NoRegister) {
264 int64_t StackSize = MF.getFrameInfo().getStackSize();
266 if (StackSize == 0) {
267 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::COPY), SPReg)
268 .addReg(MFI->getScratchWaveOffsetReg());
270 BuildMI(MBB, MBB.begin(), DL, TII->get(AMDGPU::S_ADD_U32), SPReg)
271 .addReg(MFI->getScratchWaveOffsetReg())
272 .addImm(StackSize * ST.getWavefrontSize());
276 unsigned ScratchRsrcReg
277 = getReservedPrivateSegmentBufferReg(ST, TII, TRI, MFI, MF);
279 unsigned ScratchWaveOffsetReg;
280 std::tie(ScratchWaveOffsetReg, SPReg)
281 = getReservedPrivateSegmentWaveByteOffsetReg(ST, TII, TRI, MFI, MF);
283 // It's possible to have uses of only ScratchWaveOffsetReg without
284 // ScratchRsrcReg if it's only used for the initialization of flat_scratch,
285 // but the inverse is not true.
286 if (ScratchWaveOffsetReg == AMDGPU::NoRegister) {
287 assert(ScratchRsrcReg == AMDGPU::NoRegister);
291 // We need to insert initialization of the scratch resource descriptor.
292 unsigned PreloadedScratchWaveOffsetReg = TRI->getPreloadedValue(
293 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
295 unsigned PreloadedPrivateBufferReg = AMDGPU::NoRegister;
296 if (ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF)) {
297 PreloadedPrivateBufferReg = TRI->getPreloadedValue(
298 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
301 bool OffsetRegUsed = MRI.isPhysRegUsed(ScratchWaveOffsetReg);
302 bool ResourceRegUsed = ScratchRsrcReg != AMDGPU::NoRegister &&
303 MRI.isPhysRegUsed(ScratchRsrcReg);
305 // We added live-ins during argument lowering, but since they were not used
306 // they were deleted. We're adding the uses now, so add them back.
308 assert(PreloadedScratchWaveOffsetReg != AMDGPU::NoRegister &&
309 "scratch wave offset input is required");
310 MRI.addLiveIn(PreloadedScratchWaveOffsetReg);
311 MBB.addLiveIn(PreloadedScratchWaveOffsetReg);
314 if (ResourceRegUsed && PreloadedPrivateBufferReg != AMDGPU::NoRegister) {
315 assert(ST.isAmdCodeObjectV2(MF) || ST.isMesaGfxShader(MF));
316 MRI.addLiveIn(PreloadedPrivateBufferReg);
317 MBB.addLiveIn(PreloadedPrivateBufferReg);
320 // Make the register selected live throughout the function.
321 for (MachineBasicBlock &OtherBB : MF) {
322 if (&OtherBB == &MBB)
326 OtherBB.addLiveIn(ScratchWaveOffsetReg);
329 OtherBB.addLiveIn(ScratchRsrcReg);
333 MachineBasicBlock::iterator I = MBB.begin();
335 // If we reserved the original input registers, we don't need to copy to the
336 // reserved registers.
338 bool CopyBuffer = ResourceRegUsed &&
339 PreloadedPrivateBufferReg != AMDGPU::NoRegister &&
340 ST.isAmdCodeObjectV2(MF) &&
341 ScratchRsrcReg != PreloadedPrivateBufferReg;
343 // This needs to be careful of the copying order to avoid overwriting one of
344 // the input registers before it's been copied to it's final
345 // destination. Usually the offset should be copied first.
346 bool CopyBufferFirst = TRI->isSubRegisterEq(PreloadedPrivateBufferReg,
347 ScratchWaveOffsetReg);
348 if (CopyBuffer && CopyBufferFirst) {
349 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
350 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
354 PreloadedScratchWaveOffsetReg != ScratchWaveOffsetReg) {
355 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchWaveOffsetReg)
356 .addReg(PreloadedScratchWaveOffsetReg,
357 MRI.isPhysRegUsed(ScratchWaveOffsetReg) ? 0 : RegState::Kill);
360 if (CopyBuffer && !CopyBufferFirst) {
361 BuildMI(MBB, I, DL, TII->get(AMDGPU::COPY), ScratchRsrcReg)
362 .addReg(PreloadedPrivateBufferReg, RegState::Kill);
365 if (ResourceRegUsed && (ST.isMesaGfxShader(MF) || (PreloadedPrivateBufferReg == AMDGPU::NoRegister))) {
366 assert(!ST.isAmdCodeObjectV2(MF));
367 const MCInstrDesc &SMovB32 = TII->get(AMDGPU::S_MOV_B32);
369 unsigned Rsrc2 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub2);
370 unsigned Rsrc3 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub3);
372 // Use relocations to get the pointer, and setup the other bits manually.
373 uint64_t Rsrc23 = TII->getScratchRsrcWords23();
375 if (MFI->hasPrivateMemoryInputPtr()) {
376 unsigned Rsrc01 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0_sub1);
378 if (AMDGPU::isCompute(MF.getFunction()->getCallingConv())) {
379 const MCInstrDesc &Mov64 = TII->get(AMDGPU::S_MOV_B64);
381 BuildMI(MBB, I, DL, Mov64, Rsrc01)
382 .addReg(PreloadedPrivateBufferReg)
383 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
385 const MCInstrDesc &LoadDwordX2 = TII->get(AMDGPU::S_LOAD_DWORDX2_IMM);
388 PointerType::get(Type::getInt64Ty(MF.getFunction()->getContext()),
389 AMDGPUASI.CONSTANT_ADDRESS);
390 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
391 auto MMO = MF.getMachineMemOperand(PtrInfo,
392 MachineMemOperand::MOLoad |
393 MachineMemOperand::MOInvariant |
394 MachineMemOperand::MODereferenceable,
396 BuildMI(MBB, I, DL, LoadDwordX2, Rsrc01)
397 .addReg(PreloadedPrivateBufferReg)
401 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
404 unsigned Rsrc0 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub0);
405 unsigned Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1);
407 BuildMI(MBB, I, DL, SMovB32, Rsrc0)
408 .addExternalSymbol("SCRATCH_RSRC_DWORD0")
409 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
411 BuildMI(MBB, I, DL, SMovB32, Rsrc1)
412 .addExternalSymbol("SCRATCH_RSRC_DWORD1")
413 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
417 BuildMI(MBB, I, DL, SMovB32, Rsrc2)
418 .addImm(Rsrc23 & 0xffffffff)
419 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
421 BuildMI(MBB, I, DL, SMovB32, Rsrc3)
422 .addImm(Rsrc23 >> 32)
423 .addReg(ScratchRsrcReg, RegState::ImplicitDefine);
427 void SIFrameLowering::emitEpilogue(MachineFunction &MF,
428 MachineBasicBlock &MBB) const {
432 static bool allStackObjectsAreDead(const MachineFrameInfo &MFI) {
433 for (int I = MFI.getObjectIndexBegin(), E = MFI.getObjectIndexEnd();
435 if (!MFI.isDeadObjectIndex(I))
442 int SIFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
443 unsigned &FrameReg) const {
444 const SIRegisterInfo *RI = MF.getSubtarget<SISubtarget>().getRegisterInfo();
446 FrameReg = RI->getFrameRegister(MF);
447 return MF.getFrameInfo().getObjectOffset(FI);
450 void SIFrameLowering::processFunctionBeforeFrameFinalized(
452 RegScavenger *RS) const {
453 MachineFrameInfo &MFI = MF.getFrameInfo();
455 if (!MFI.hasStackObjects())
458 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
459 const SIInstrInfo *TII = ST.getInstrInfo();
460 const SIRegisterInfo &TRI = TII->getRegisterInfo();
461 SIMachineFunctionInfo *FuncInfo = MF.getInfo<SIMachineFunctionInfo>();
462 bool AllSGPRSpilledToVGPRs = false;
464 if (TRI.spillSGPRToVGPR() && FuncInfo->hasSpilledSGPRs()) {
465 AllSGPRSpilledToVGPRs = true;
467 // Process all SGPR spills before frame offsets are finalized. Ideally SGPRs
468 // are spilled to VGPRs, in which case we can eliminate the stack usage.
470 // XXX - This operates under the assumption that only other SGPR spills are
471 // users of the frame index. I'm not 100% sure this is correct. The
472 // StackColoring pass has a comment saying a future improvement would be to
473 // merging of allocas with spill slots, but for now according to
474 // MachineFrameInfo isSpillSlot can't alias any other object.
475 for (MachineBasicBlock &MBB : MF) {
476 MachineBasicBlock::iterator Next;
477 for (auto I = MBB.begin(), E = MBB.end(); I != E; I = Next) {
478 MachineInstr &MI = *I;
481 if (TII->isSGPRSpill(MI)) {
482 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex();
483 if (FuncInfo->allocateSGPRSpillToVGPR(MF, FI)) {
484 bool Spilled = TRI.eliminateSGPRToVGPRSpillFrameIndex(MI, FI, RS);
486 assert(Spilled && "failed to spill SGPR to VGPR when allocated");
488 AllSGPRSpilledToVGPRs = false;
493 FuncInfo->removeSGPRToVGPRFrameIndices(MFI);
496 // FIXME: The other checks should be redundant with allStackObjectsAreDead,
497 // but currently hasNonSpillStackObjects is set only from source
498 // allocas. Stack temps produced from legalization are not counted currently.
499 if (FuncInfo->hasNonSpillStackObjects() || FuncInfo->hasSpilledVGPRs() ||
500 !AllSGPRSpilledToVGPRs || !allStackObjectsAreDead(MFI)) {
501 assert(RS && "RegScavenger required if spilling");
503 // We force this to be at offset 0 so no user object ever has 0 as an
504 // address, so we may use 0 as an invalid pointer value. This is because
505 // LLVM assumes 0 is an invalid pointer in address space 0. Because alloca
506 // is required to be address space 0, we are forced to accept this for
507 // now. Ideally we could have the stack in another address space with 0 as a
508 // valid pointer, and -1 as the null value.
510 // This will also waste additional space when user stack objects require > 4
513 // The main cost here is losing the offset for addressing modes. However
514 // this also ensures we shouldn't need a register for the offset when
515 // emergency scavenging.
516 int ScavengeFI = MFI.CreateFixedObject(
517 TRI.getSpillSize(AMDGPU::SGPR_32RegClass), 0, false);
518 RS->addScavengingFrameIndex(ScavengeFI);
522 void SIFrameLowering::emitDebuggerPrologue(MachineFunction &MF,
523 MachineBasicBlock &MBB) const {
524 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
525 const SIInstrInfo *TII = ST.getInstrInfo();
526 const SIRegisterInfo *TRI = &TII->getRegisterInfo();
527 const SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
529 MachineBasicBlock::iterator I = MBB.begin();
532 // For each dimension:
533 for (unsigned i = 0; i < 3; ++i) {
534 // Get work group ID SGPR, and make it live-in again.
535 unsigned WorkGroupIDSGPR = MFI->getWorkGroupIDSGPR(i);
536 MF.getRegInfo().addLiveIn(WorkGroupIDSGPR);
537 MBB.addLiveIn(WorkGroupIDSGPR);
539 // Since SGPRs are spilled into VGPRs, copy work group ID SGPR to VGPR in
540 // order to spill it to scratch.
541 unsigned WorkGroupIDVGPR =
542 MF.getRegInfo().createVirtualRegister(&AMDGPU::VGPR_32RegClass);
543 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), WorkGroupIDVGPR)
544 .addReg(WorkGroupIDSGPR);
546 // Spill work group ID.
547 int WorkGroupIDObjectIdx = MFI->getDebuggerWorkGroupIDStackObjectIndex(i);
548 TII->storeRegToStackSlot(MBB, I, WorkGroupIDVGPR, false,
549 WorkGroupIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);
551 // Get work item ID VGPR, and make it live-in again.
552 unsigned WorkItemIDVGPR = MFI->getWorkItemIDVGPR(i);
553 MF.getRegInfo().addLiveIn(WorkItemIDVGPR);
554 MBB.addLiveIn(WorkItemIDVGPR);
556 // Spill work item ID.
557 int WorkItemIDObjectIdx = MFI->getDebuggerWorkItemIDStackObjectIndex(i);
558 TII->storeRegToStackSlot(MBB, I, WorkItemIDVGPR, false,
559 WorkItemIDObjectIdx, &AMDGPU::VGPR_32RegClass, TRI);