1 //===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Custom DAG lowering for SI
13 //===----------------------------------------------------------------------===//
17 #define _USE_MATH_DEFINES
22 #include "AMDGPUIntrinsicInfo.h"
23 #include "AMDGPUSubtarget.h"
24 #include "SIISelLowering.h"
25 #include "SIInstrInfo.h"
26 #include "SIMachineFunctionInfo.h"
27 #include "SIRegisterInfo.h"
28 #include "llvm/ADT/BitVector.h"
29 #include "llvm/ADT/StringSwitch.h"
30 #include "llvm/CodeGen/CallingConvLower.h"
31 #include "llvm/CodeGen/MachineInstrBuilder.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/SelectionDAG.h"
34 #include "llvm/IR/DiagnosticInfo.h"
35 #include "llvm/IR/Function.h"
39 // -amdgpu-fast-fdiv - Command line option to enable faster 2.5 ulp fdiv.
40 static cl::opt<bool> EnableAMDGPUFastFDIV(
42 cl::desc("Enable faster 2.5 ulp fdiv"),
45 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
46 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
47 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
48 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
49 return AMDGPU::SGPR0 + Reg;
52 llvm_unreachable("Cannot allocate sgpr");
55 SITargetLowering::SITargetLowering(const TargetMachine &TM,
56 const SISubtarget &STI)
57 : AMDGPUTargetLowering(TM, STI) {
58 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
59 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
61 addRegisterClass(MVT::i32, &AMDGPU::SReg_32RegClass);
62 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
64 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
65 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
66 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
68 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
69 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
71 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
72 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
74 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
75 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
77 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
78 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
80 computeRegisterProperties(STI.getRegisterInfo());
82 // We need to custom lower vector stores from local memory
83 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
84 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
85 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
86 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
87 setOperationAction(ISD::LOAD, MVT::i1, Custom);
89 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
90 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
91 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
93 setOperationAction(ISD::STORE, MVT::i1, Custom);
95 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
96 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
97 setOperationAction(ISD::FrameIndex, MVT::i32, Custom);
98 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand);
100 setOperationAction(ISD::SELECT, MVT::i1, Promote);
101 setOperationAction(ISD::SELECT, MVT::i64, Custom);
102 setOperationAction(ISD::SELECT, MVT::f64, Promote);
103 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
105 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
106 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
107 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
108 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
109 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
111 setOperationAction(ISD::SETCC, MVT::i1, Promote);
112 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
113 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
115 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
116 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
118 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
119 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
120 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
121 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
122 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
123 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
127 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
128 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
130 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
131 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
132 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
133 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
134 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
135 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
137 // We only support LOAD/STORE and vector manipulation ops for vectors
138 // with > 4 elements.
139 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
140 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
144 case ISD::BUILD_VECTOR:
146 case ISD::EXTRACT_VECTOR_ELT:
147 case ISD::INSERT_VECTOR_ELT:
148 case ISD::INSERT_SUBVECTOR:
149 case ISD::EXTRACT_SUBVECTOR:
150 case ISD::SCALAR_TO_VECTOR:
152 case ISD::CONCAT_VECTORS:
153 setOperationAction(Op, VT, Custom);
156 setOperationAction(Op, VT, Expand);
162 // Most operations are naturally 32-bit vector operations. We only support
163 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
164 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
165 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
166 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
168 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
169 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
171 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
172 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
174 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
175 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
178 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
179 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
180 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
181 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
183 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
184 // and output demarshalling
185 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
186 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
188 // We can't return success/failure, only the old value,
189 // let LLVM add the comparison
190 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
191 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
193 if (getSubtarget()->hasFlatAddressSpace()) {
194 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
195 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
198 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
199 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
201 // On SI this is s_memtime and s_memrealtime on VI.
202 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
203 setOperationAction(ISD::TRAP, MVT::Other, Custom);
205 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
206 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
208 if (Subtarget->getGeneration() >= SISubtarget::SEA_ISLANDS) {
209 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
210 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
211 setOperationAction(ISD::FRINT, MVT::f64, Legal);
214 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
216 setOperationAction(ISD::FSIN, MVT::f32, Custom);
217 setOperationAction(ISD::FCOS, MVT::f32, Custom);
218 setOperationAction(ISD::FDIV, MVT::f32, Custom);
219 setOperationAction(ISD::FDIV, MVT::f64, Custom);
221 setTargetDAGCombine(ISD::FADD);
222 setTargetDAGCombine(ISD::FSUB);
223 setTargetDAGCombine(ISD::FMINNUM);
224 setTargetDAGCombine(ISD::FMAXNUM);
225 setTargetDAGCombine(ISD::SMIN);
226 setTargetDAGCombine(ISD::SMAX);
227 setTargetDAGCombine(ISD::UMIN);
228 setTargetDAGCombine(ISD::UMAX);
229 setTargetDAGCombine(ISD::SETCC);
230 setTargetDAGCombine(ISD::AND);
231 setTargetDAGCombine(ISD::OR);
232 setTargetDAGCombine(ISD::UINT_TO_FP);
233 setTargetDAGCombine(ISD::FCANONICALIZE);
235 // All memory operations. Some folding on the pointer operand is done to help
236 // matching the constant offsets in the addressing modes.
237 setTargetDAGCombine(ISD::LOAD);
238 setTargetDAGCombine(ISD::STORE);
239 setTargetDAGCombine(ISD::ATOMIC_LOAD);
240 setTargetDAGCombine(ISD::ATOMIC_STORE);
241 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
242 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
243 setTargetDAGCombine(ISD::ATOMIC_SWAP);
244 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
245 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
246 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
247 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
248 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
249 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
250 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
251 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
252 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
253 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
255 setSchedulingPreference(Sched::RegPressure);
258 const SISubtarget *SITargetLowering::getSubtarget() const {
259 return static_cast<const SISubtarget *>(Subtarget);
262 //===----------------------------------------------------------------------===//
263 // TargetLowering queries
264 //===----------------------------------------------------------------------===//
266 bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
268 unsigned IntrID) const {
270 case Intrinsic::amdgcn_atomic_inc:
271 case Intrinsic::amdgcn_atomic_dec:
272 Info.opc = ISD::INTRINSIC_W_CHAIN;
273 Info.memVT = MVT::getVT(CI.getType());
274 Info.ptrVal = CI.getOperand(0);
278 Info.writeMem = true;
285 bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
287 // SI has some legal vector types, but no legal vector operations. Say no
288 // shuffles are legal in order to prefer scalarizing some vector operations.
292 bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
293 // Flat instructions do not have offsets, and only have the register
295 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
298 bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
299 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
300 // additionally can do r + r + i with addr64. 32-bit has more addressing
301 // mode options. Depending on the resource constant, it can also do
302 // (i64 r0) + (i32 r1) * (i14 i).
304 // Private arrays end up using a scratch buffer most of the time, so also
305 // assume those use MUBUF instructions. Scratch loads / stores are currently
306 // implemented as mubuf instructions with offen bit set, so slightly
307 // different than the normal addr64.
308 if (!isUInt<12>(AM.BaseOffs))
311 // FIXME: Since we can split immediate into soffset and immediate offset,
312 // would it make sense to allow any immediate?
315 case 0: // r + i or just i, depending on HasBaseReg.
318 return true; // We have r + r or r + i.
325 // Allow 2 * r as r + r
326 // Or 2 * r + i is allowed as r + r + i.
328 default: // Don't allow n * r
333 bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
334 const AddrMode &AM, Type *Ty,
336 // No global is ever allowed as a base.
341 case AMDGPUAS::GLOBAL_ADDRESS: {
342 if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS) {
343 // Assume the we will use FLAT for all global memory accesses
345 // FIXME: This assumption is currently wrong. On VI we still use
346 // MUBUF instructions for the r + i addressing mode. As currently
347 // implemented, the MUBUF instructions only work on buffer < 4GB.
348 // It may be possible to support > 4GB buffers with MUBUF instructions,
349 // by setting the stride value in the resource descriptor which would
350 // increase the size limit to (stride * 4GB). However, this is risky,
351 // because it has never been validated.
352 return isLegalFlatAddressingMode(AM);
355 return isLegalMUBUFAddressingMode(AM);
357 case AMDGPUAS::CONSTANT_ADDRESS: {
358 // If the offset isn't a multiple of 4, it probably isn't going to be
359 // correctly aligned.
360 if (AM.BaseOffs % 4 != 0)
361 return isLegalMUBUFAddressingMode(AM);
363 // There are no SMRD extloads, so if we have to do a small type access we
364 // will use a MUBUF load.
365 // FIXME?: We also need to do this if unaligned, but we don't know the
367 if (DL.getTypeStoreSize(Ty) < 4)
368 return isLegalMUBUFAddressingMode(AM);
370 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS) {
371 // SMRD instructions have an 8-bit, dword offset on SI.
372 if (!isUInt<8>(AM.BaseOffs / 4))
374 } else if (Subtarget->getGeneration() == SISubtarget::SEA_ISLANDS) {
375 // On CI+, this can also be a 32-bit literal constant offset. If it fits
376 // in 8-bits, it can use a smaller encoding.
377 if (!isUInt<32>(AM.BaseOffs / 4))
379 } else if (Subtarget->getGeneration() == SISubtarget::VOLCANIC_ISLANDS) {
380 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
381 if (!isUInt<20>(AM.BaseOffs))
384 llvm_unreachable("unhandled generation");
386 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
389 if (AM.Scale == 1 && AM.HasBaseReg)
395 case AMDGPUAS::PRIVATE_ADDRESS:
396 return isLegalMUBUFAddressingMode(AM);
398 case AMDGPUAS::LOCAL_ADDRESS:
399 case AMDGPUAS::REGION_ADDRESS: {
400 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
402 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
403 // an 8-bit dword offset but we don't know the alignment here.
404 if (!isUInt<16>(AM.BaseOffs))
407 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
410 if (AM.Scale == 1 && AM.HasBaseReg)
415 case AMDGPUAS::FLAT_ADDRESS:
416 case AMDGPUAS::UNKNOWN_ADDRESS_SPACE:
417 // For an unknown address space, this usually means that this is for some
418 // reason being used for pure arithmetic, and not based on some addressing
419 // computation. We don't have instructions that compute pointers with any
420 // addressing modes, so treat them as having no offset like flat
422 return isLegalFlatAddressingMode(AM);
425 llvm_unreachable("unhandled address space");
429 bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
432 bool *IsFast) const {
436 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
437 // which isn't a simple VT.
438 if (!VT.isSimple() || VT == MVT::Other)
441 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
442 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
443 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
444 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
445 // with adjacent offsets.
446 bool AlignedBy4 = (Align % 4 == 0);
448 *IsFast = AlignedBy4;
453 if (Subtarget->hasUnalignedBufferAccess()) {
454 // If we have an uniform constant load, it still requires using a slow
455 // buffer instruction if unaligned.
457 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS) ?
458 (Align % 4 == 0) : true;
464 // Smaller than dword value must be aligned.
465 if (VT.bitsLT(MVT::i32))
468 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
469 // byte-address are ignored, thus forcing Dword alignment.
470 // This applies to private, global, and constant memory.
474 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
477 EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
478 unsigned SrcAlign, bool IsMemset,
481 MachineFunction &MF) const {
482 // FIXME: Should account for address space here.
484 // The default fallback uses the private pointer size as a guess for a type to
485 // use. Make sure we switch these to 64-bit accesses.
487 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
490 if (Size >= 8 && DstAlign >= 4)
497 static bool isFlatGlobalAddrSpace(unsigned AS) {
498 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
499 AS == AMDGPUAS::FLAT_ADDRESS ||
500 AS == AMDGPUAS::CONSTANT_ADDRESS;
503 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
504 unsigned DestAS) const {
505 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
508 bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
509 const MemSDNode *MemNode = cast<MemSDNode>(N);
510 const Value *Ptr = MemNode->getMemOperand()->getValue();
512 // UndefValue means this is a load of a kernel input. These are uniform.
513 // Sometimes LDS instructions have constant pointers.
514 // If Ptr is null, then that means this mem operand contains a
515 // PseudoSourceValue like GOT.
516 if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
517 isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
520 const Instruction *I = dyn_cast<Instruction>(Ptr);
521 return I && I->getMetadata("amdgpu.uniform");
524 TargetLoweringBase::LegalizeTypeAction
525 SITargetLowering::getPreferredVectorAction(EVT VT) const {
526 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
527 return TypeSplitVector;
529 return TargetLoweringBase::getPreferredVectorAction(VT);
532 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
534 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
535 return TII->isInlineConstant(Imm);
538 bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
540 // SimplifySetCC uses this function to determine whether or not it should
541 // create setcc with i1 operands. We don't have instructions for i1 setcc.
542 if (VT == MVT::i1 && Op == ISD::SETCC)
545 return TargetLowering::isTypeDesirableForOp(Op, VT);
548 SDValue SITargetLowering::LowerParameterPtr(SelectionDAG &DAG,
549 const SDLoc &SL, SDValue Chain,
550 unsigned Offset) const {
551 const DataLayout &DL = DAG.getDataLayout();
552 MachineFunction &MF = DAG.getMachineFunction();
553 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
554 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
556 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
557 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
558 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
559 MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
560 return DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
561 DAG.getConstant(Offset, SL, PtrVT));
563 SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
564 const SDLoc &SL, SDValue Chain,
565 unsigned Offset, bool Signed) const {
566 const DataLayout &DL = DAG.getDataLayout();
567 Type *Ty = VT.getTypeForEVT(*DAG.getContext());
568 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
569 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
570 SDValue PtrOffset = DAG.getUNDEF(PtrVT);
571 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
573 unsigned Align = DL.getABITypeAlignment(Ty);
575 ISD::LoadExtType ExtTy = Signed ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
576 if (MemVT.isFloatingPoint())
577 ExtTy = ISD::EXTLOAD;
579 SDValue Ptr = LowerParameterPtr(DAG, SL, Chain, Offset);
580 return DAG.getLoad(ISD::UNINDEXED, ExtTy, VT, SL, Chain, Ptr, PtrOffset,
581 PtrInfo, MemVT, Align, MachineMemOperand::MONonTemporal |
582 MachineMemOperand::MOInvariant);
585 SDValue SITargetLowering::LowerFormalArguments(
586 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
587 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
588 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
589 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
591 MachineFunction &MF = DAG.getMachineFunction();
592 FunctionType *FType = MF.getFunction()->getFunctionType();
593 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
594 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
596 if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) {
597 const Function *Fn = MF.getFunction();
598 DiagnosticInfoUnsupported NoGraphicsHSA(
599 *Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
600 DAG.getContext()->diagnose(NoGraphicsHSA);
601 return DAG.getEntryNode();
604 // Create stack objects that are used for emitting debugger prologue if
605 // "amdgpu-debugger-emit-prologue" attribute was specified.
606 if (ST.debuggerEmitPrologue())
607 createDebuggerPrologueStackObjects(MF);
609 SmallVector<ISD::InputArg, 16> Splits;
610 BitVector Skipped(Ins.size());
612 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
613 const ISD::InputArg &Arg = Ins[i];
615 // First check if it's a PS input addr
616 if (CallConv == CallingConv::AMDGPU_PS && !Arg.Flags.isInReg() &&
617 !Arg.Flags.isByVal() && PSInputNum <= 15) {
619 if (!Arg.Used && !Info->isPSInputAllocated(PSInputNum)) {
620 // We can safely skip PS inputs
626 Info->markPSInputAllocated(PSInputNum);
628 Info->PSInputEna |= 1 << PSInputNum;
633 if (AMDGPU::isShader(CallConv)) {
634 // Second split vertices into their elements
635 if (Arg.VT.isVector()) {
636 ISD::InputArg NewArg = Arg;
637 NewArg.Flags.setSplit();
638 NewArg.VT = Arg.VT.getVectorElementType();
640 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
641 // three or five element vertex only needs three or five registers,
642 // NOT four or eight.
643 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
644 unsigned NumElements = ParamType->getVectorNumElements();
646 for (unsigned j = 0; j != NumElements; ++j) {
647 Splits.push_back(NewArg);
648 NewArg.PartOffset += NewArg.VT.getStoreSize();
651 Splits.push_back(Arg);
656 SmallVector<CCValAssign, 16> ArgLocs;
657 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
660 // At least one interpolation mode must be enabled or else the GPU will hang.
662 // Check PSInputAddr instead of PSInputEna. The idea is that if the user set
663 // PSInputAddr, the user wants to enable some bits after the compilation
664 // based on run-time states. Since we can't know what the final PSInputEna
665 // will look like, so we shouldn't do anything here and the user should take
666 // responsibility for the correct programming.
668 // Otherwise, the following restrictions apply:
669 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
670 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
672 if (CallConv == CallingConv::AMDGPU_PS &&
673 ((Info->getPSInputAddr() & 0x7F) == 0 ||
674 ((Info->getPSInputAddr() & 0xF) == 0 && Info->isPSInputAllocated(11)))) {
675 CCInfo.AllocateReg(AMDGPU::VGPR0);
676 CCInfo.AllocateReg(AMDGPU::VGPR1);
677 Info->markPSInputAllocated(0);
678 Info->PSInputEna |= 1;
681 if (!AMDGPU::isShader(CallConv)) {
682 getOriginalFunctionArgs(DAG, DAG.getMachineFunction().getFunction(), Ins,
685 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX());
687 assert(!Info->hasPrivateSegmentBuffer() && !Info->hasDispatchPtr() &&
688 !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() &&
689 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
690 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&
691 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
692 !Info->hasWorkItemIDZ());
695 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
696 if (Info->hasPrivateSegmentBuffer()) {
697 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
698 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
699 CCInfo.AllocateReg(PrivateSegmentBufferReg);
702 if (Info->hasDispatchPtr()) {
703 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
704 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SReg_64RegClass);
705 CCInfo.AllocateReg(DispatchPtrReg);
708 if (Info->hasQueuePtr()) {
709 unsigned QueuePtrReg = Info->addQueuePtr(*TRI);
710 MF.addLiveIn(QueuePtrReg, &AMDGPU::SReg_64RegClass);
711 CCInfo.AllocateReg(QueuePtrReg);
714 if (Info->hasKernargSegmentPtr()) {
715 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
716 MF.addLiveIn(InputPtrReg, &AMDGPU::SReg_64RegClass);
717 CCInfo.AllocateReg(InputPtrReg);
720 if (Info->hasFlatScratchInit()) {
721 unsigned FlatScratchInitReg = Info->addFlatScratchInit(*TRI);
722 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SReg_64RegClass);
723 CCInfo.AllocateReg(FlatScratchInitReg);
726 AnalyzeFormalArguments(CCInfo, Splits);
728 SmallVector<SDValue, 16> Chains;
730 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
732 const ISD::InputArg &Arg = Ins[i];
734 InVals.push_back(DAG.getUNDEF(Arg.VT));
738 CCValAssign &VA = ArgLocs[ArgIdx++];
739 MVT VT = VA.getLocVT();
743 EVT MemVT = Splits[i].VT;
744 const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
745 VA.getLocMemOffset();
746 // The first 36 bytes of the input buffer contains information about
747 // thread group and global sizes.
748 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
749 Offset, Ins[i].Flags.isSExt());
750 Chains.push_back(Arg.getValue(1));
753 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
754 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS &&
755 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
756 // On SI local pointers are just offsets into LDS, so they are always
757 // less than 16-bits. On CI and newer they could potentially be
758 // real pointers, so we can't guarantee their size.
759 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
760 DAG.getValueType(MVT::i16));
763 InVals.push_back(Arg);
764 Info->ABIArgOffset = Offset + MemVT.getStoreSize();
767 assert(VA.isRegLoc() && "Parameter must be in a register!");
769 unsigned Reg = VA.getLocReg();
771 if (VT == MVT::i64) {
772 // For now assume it is a pointer
773 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
774 &AMDGPU::SReg_64RegClass);
775 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass);
776 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
777 InVals.push_back(Copy);
781 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
783 Reg = MF.addLiveIn(Reg, RC);
784 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
786 if (Arg.VT.isVector()) {
788 // Build a vector from the registers
789 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
790 unsigned NumElements = ParamType->getVectorNumElements();
792 SmallVector<SDValue, 4> Regs;
794 for (unsigned j = 1; j != NumElements; ++j) {
795 Reg = ArgLocs[ArgIdx++].getLocReg();
796 Reg = MF.addLiveIn(Reg, RC);
798 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
799 Regs.push_back(Copy);
802 // Fill up the missing vector elements
803 NumElements = Arg.VT.getVectorNumElements() - NumElements;
804 Regs.append(NumElements, DAG.getUNDEF(VT));
806 InVals.push_back(DAG.getBuildVector(Arg.VT, DL, Regs));
810 InVals.push_back(Val);
813 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
814 // these from the dispatch pointer.
816 // Start adding system SGPRs.
817 if (Info->hasWorkGroupIDX()) {
818 unsigned Reg = Info->addWorkGroupIDX();
819 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
820 CCInfo.AllocateReg(Reg);
823 if (Info->hasWorkGroupIDY()) {
824 unsigned Reg = Info->addWorkGroupIDY();
825 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
826 CCInfo.AllocateReg(Reg);
829 if (Info->hasWorkGroupIDZ()) {
830 unsigned Reg = Info->addWorkGroupIDZ();
831 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
832 CCInfo.AllocateReg(Reg);
835 if (Info->hasWorkGroupInfo()) {
836 unsigned Reg = Info->addWorkGroupInfo();
837 MF.addLiveIn(Reg, &AMDGPU::SReg_32RegClass);
838 CCInfo.AllocateReg(Reg);
841 if (Info->hasPrivateSegmentWaveByteOffset()) {
842 // Scratch wave offset passed in system SGPR.
843 unsigned PrivateSegmentWaveByteOffsetReg;
845 if (AMDGPU::isShader(CallConv)) {
846 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
847 Info->setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
849 PrivateSegmentWaveByteOffsetReg = Info->addPrivateSegmentWaveByteOffset();
851 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
852 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
855 // Now that we've figured out where the scratch register inputs are, see if
856 // should reserve the arguments and use them directly.
857 bool HasStackObjects = MF.getFrameInfo()->hasStackObjects();
858 // Record that we know we have non-spill stack objects so we don't need to
859 // check all stack objects later.
861 Info->setHasNonSpillStackObjects(true);
863 if (ST.isAmdHsaOS()) {
864 // TODO: Assume we will spill without optimizations.
865 if (HasStackObjects) {
866 // If we have stack objects, we unquestionably need the private buffer
867 // resource. For the HSA ABI, this will be the first 4 user SGPR
868 // inputs. We can reserve those and use them directly.
870 unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
871 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
872 Info->setScratchRSrcReg(PrivateSegmentBufferReg);
874 unsigned PrivateSegmentWaveByteOffsetReg = TRI->getPreloadedValue(
875 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
876 Info->setScratchWaveOffsetReg(PrivateSegmentWaveByteOffsetReg);
878 unsigned ReservedBufferReg
879 = TRI->reservedPrivateSegmentBufferReg(MF);
880 unsigned ReservedOffsetReg
881 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
883 // We tentatively reserve the last registers (skipping the last two
884 // which may contain VCC). After register allocation, we'll replace
885 // these with the ones immediately after those which were really
886 // allocated. In the prologue copies will be inserted from the argument
887 // to these reserved registers.
888 Info->setScratchRSrcReg(ReservedBufferReg);
889 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
892 unsigned ReservedBufferReg = TRI->reservedPrivateSegmentBufferReg(MF);
894 // Without HSA, relocations are used for the scratch pointer and the
895 // buffer resource setup is always inserted in the prologue. Scratch wave
896 // offset is still in an input SGPR.
897 Info->setScratchRSrcReg(ReservedBufferReg);
899 if (HasStackObjects) {
900 unsigned ScratchWaveOffsetReg = TRI->getPreloadedValue(
901 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
902 Info->setScratchWaveOffsetReg(ScratchWaveOffsetReg);
904 unsigned ReservedOffsetReg
905 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
906 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
910 if (Info->hasWorkItemIDX()) {
911 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X);
912 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
913 CCInfo.AllocateReg(Reg);
916 if (Info->hasWorkItemIDY()) {
917 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y);
918 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
919 CCInfo.AllocateReg(Reg);
922 if (Info->hasWorkItemIDZ()) {
923 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z);
924 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
925 CCInfo.AllocateReg(Reg);
931 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
935 SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
937 const SmallVectorImpl<ISD::OutputArg> &Outs,
938 const SmallVectorImpl<SDValue> &OutVals,
939 const SDLoc &DL, SelectionDAG &DAG) const {
940 MachineFunction &MF = DAG.getMachineFunction();
941 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
943 if (!AMDGPU::isShader(CallConv))
944 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
947 Info->setIfReturnsVoid(Outs.size() == 0);
949 SmallVector<ISD::OutputArg, 48> Splits;
950 SmallVector<SDValue, 48> SplitVals;
952 // Split vectors into their elements.
953 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
954 const ISD::OutputArg &Out = Outs[i];
956 if (Out.VT.isVector()) {
957 MVT VT = Out.VT.getVectorElementType();
958 ISD::OutputArg NewOut = Out;
959 NewOut.Flags.setSplit();
962 // We want the original number of vector elements here, e.g.
963 // three or five, not four or eight.
964 unsigned NumElements = Out.ArgVT.getVectorNumElements();
966 for (unsigned j = 0; j != NumElements; ++j) {
967 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, OutVals[i],
968 DAG.getConstant(j, DL, MVT::i32));
969 SplitVals.push_back(Elem);
970 Splits.push_back(NewOut);
971 NewOut.PartOffset += NewOut.VT.getStoreSize();
974 SplitVals.push_back(OutVals[i]);
975 Splits.push_back(Out);
979 // CCValAssign - represent the assignment of the return value to a location.
980 SmallVector<CCValAssign, 48> RVLocs;
982 // CCState - Info about the registers and stack slots.
983 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
986 // Analyze outgoing return values.
987 AnalyzeReturn(CCInfo, Splits);
990 SmallVector<SDValue, 48> RetOps;
991 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
993 // Copy the result values into the output registers.
994 for (unsigned i = 0, realRVLocIdx = 0;
996 ++i, ++realRVLocIdx) {
997 CCValAssign &VA = RVLocs[i];
998 assert(VA.isRegLoc() && "Can only return in registers!");
1000 SDValue Arg = SplitVals[realRVLocIdx];
1002 // Copied from other backends.
1003 switch (VA.getLocInfo()) {
1004 default: llvm_unreachable("Unknown loc info!");
1005 case CCValAssign::Full:
1007 case CCValAssign::BCvt:
1008 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1012 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
1013 Flag = Chain.getValue(1);
1014 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1017 // Update chain and glue.
1020 RetOps.push_back(Flag);
1022 unsigned Opc = Info->returnsVoid() ? AMDGPUISD::ENDPGM : AMDGPUISD::RETURN;
1023 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
1026 unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
1027 SelectionDAG &DAG) const {
1028 unsigned Reg = StringSwitch<unsigned>(RegName)
1029 .Case("m0", AMDGPU::M0)
1030 .Case("exec", AMDGPU::EXEC)
1031 .Case("exec_lo", AMDGPU::EXEC_LO)
1032 .Case("exec_hi", AMDGPU::EXEC_HI)
1033 .Case("flat_scratch", AMDGPU::FLAT_SCR)
1034 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
1035 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
1036 .Default(AMDGPU::NoRegister);
1038 if (Reg == AMDGPU::NoRegister) {
1039 report_fatal_error(Twine("invalid register name \""
1040 + StringRef(RegName) + "\"."));
1044 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS &&
1045 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
1046 report_fatal_error(Twine("invalid register \""
1047 + StringRef(RegName) + "\" for subtarget."));
1052 case AMDGPU::EXEC_LO:
1053 case AMDGPU::EXEC_HI:
1054 case AMDGPU::FLAT_SCR_LO:
1055 case AMDGPU::FLAT_SCR_HI:
1056 if (VT.getSizeInBits() == 32)
1060 case AMDGPU::FLAT_SCR:
1061 if (VT.getSizeInBits() == 64)
1065 llvm_unreachable("missing register type checking");
1068 report_fatal_error(Twine("invalid type for register \""
1069 + StringRef(RegName) + "\"."));
1072 // If kill is not the last instruction, split the block so kill is always a
1073 // proper terminator.
1074 MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
1075 MachineBasicBlock *BB) const {
1076 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
1078 MachineBasicBlock::iterator SplitPoint(&MI);
1081 if (SplitPoint == BB->end()) {
1082 // Don't bother with a new block.
1083 MI.setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
1087 MachineFunction *MF = BB->getParent();
1088 MachineBasicBlock *SplitBB
1089 = MF->CreateMachineBasicBlock(BB->getBasicBlock());
1091 // Fix the block phi references to point to the new block for the defs in the
1092 // second piece of the block.
1093 for (MachineBasicBlock *Succ : BB->successors()) {
1094 for (MachineInstr &MI : *Succ) {
1098 for (unsigned I = 2, E = MI.getNumOperands(); I != E; I += 2) {
1099 MachineOperand &FromBB = MI.getOperand(I);
1100 if (BB == FromBB.getMBB()) {
1101 FromBB.setMBB(SplitBB);
1108 MF->insert(++MachineFunction::iterator(BB), SplitBB);
1109 SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
1111 SplitBB->transferSuccessors(BB);
1112 BB->addSuccessor(SplitBB);
1114 MI.setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
1118 MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
1119 MachineInstr &MI, MachineBasicBlock *BB) const {
1120 switch (MI.getOpcode()) {
1121 case AMDGPU::SI_INIT_M0: {
1122 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
1123 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
1124 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1125 .addOperand(MI.getOperand(0));
1126 MI.eraseFromParent();
1129 case AMDGPU::BRANCH:
1131 case AMDGPU::GET_GROUPSTATICSIZE: {
1132 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
1134 MachineFunction *MF = BB->getParent();
1135 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
1136 DebugLoc DL = MI.getDebugLoc();
1137 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
1138 .addOperand(MI.getOperand(0))
1139 .addImm(MFI->LDSSize);
1140 MI.eraseFromParent();
1143 case AMDGPU::SI_KILL:
1144 return splitKillBlock(MI, BB);
1146 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1151 bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1152 // This currently forces unfolding various combinations of fsub into fma with
1153 // free fneg'd operands. As long as we have fast FMA (controlled by
1154 // isFMAFasterThanFMulAndFAdd), we should perform these.
1156 // When fma is quarter rate, for f64 where add / sub are at best half rate,
1157 // most of these combines appear to be cycle neutral but save on instruction
1158 // count / code size.
1162 EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
1164 if (!VT.isVector()) {
1167 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
1170 MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
1174 // Answering this is somewhat tricky and depends on the specific device which
1175 // have different rates for fma or all f64 operations.
1177 // v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
1178 // regardless of which device (although the number of cycles differs between
1179 // devices), so it is always profitable for f64.
1181 // v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
1182 // only on full rate devices. Normally, we should prefer selecting v_mad_f32
1183 // which we can always do even without fused FP ops since it returns the same
1184 // result as the separate operations and since it is always full
1185 // rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
1186 // however does not support denormals, so we do report fma as faster if we have
1187 // a fast fma device and require denormals.
1189 bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
1190 VT = VT.getScalarType();
1195 switch (VT.getSimpleVT().SimpleTy) {
1197 // This is as fast on some subtargets. However, we always have full rate f32
1198 // mad available which returns the same result as the separate operations
1199 // which we should prefer over fma. We can't use this if we want to support
1200 // denormals, so only report this in these cases.
1201 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
1211 //===----------------------------------------------------------------------===//
1212 // Custom DAG Lowering Operations
1213 //===----------------------------------------------------------------------===//
1215 SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1216 switch (Op.getOpcode()) {
1217 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1218 case ISD::FrameIndex: return LowerFrameIndex(Op, DAG);
1219 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1221 SDValue Result = LowerLOAD(Op, DAG);
1222 assert((!Result.getNode() ||
1223 Result.getNode()->getNumValues() == 2) &&
1224 "Load should return a value and a chain");
1230 return LowerTrig(Op, DAG);
1231 case ISD::SELECT: return LowerSELECT(Op, DAG);
1232 case ISD::FDIV: return LowerFDIV(Op, DAG);
1233 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
1234 case ISD::STORE: return LowerSTORE(Op, DAG);
1235 case ISD::GlobalAddress: {
1236 MachineFunction &MF = DAG.getMachineFunction();
1237 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1238 return LowerGlobalAddress(MFI, Op, DAG);
1240 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
1241 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
1242 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
1243 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
1244 case ISD::TRAP: return lowerTRAP(Op, DAG);
1249 /// \brief Helper function for LowerBRCOND
1250 static SDNode *findUser(SDValue Value, unsigned Opcode) {
1252 SDNode *Parent = Value.getNode();
1253 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
1256 if (I.getUse().get() != Value)
1259 if (I->getOpcode() == Opcode)
1265 SDValue SITargetLowering::LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const {
1268 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Op);
1269 unsigned FrameIndex = FINode->getIndex();
1271 // A FrameIndex node represents a 32-bit offset into scratch memory. If the
1272 // high bit of a frame index offset were to be set, this would mean that it
1273 // represented an offset of ~2GB * 64 = ~128GB from the start of the scratch
1274 // buffer, with 64 being the number of threads per wave.
1276 // The maximum private allocation for the entire GPU is 4G, and we are
1277 // concerned with the largest the index could ever be for an individual
1278 // workitem. This will occur with the minmum dispatch size. If a program
1279 // requires more, the dispatch size will be reduced.
1281 // With this limit, we can mark the high bit of the FrameIndex node as known
1282 // zero, which is important, because it means in most situations we can prove
1283 // that values derived from FrameIndex nodes are non-negative. This enables us
1284 // to take advantage of more addressing modes when accessing scratch buffers,
1285 // since for scratch reads/writes, the register offset must always be
1288 uint64_t MaxGPUAlloc = UINT64_C(4) * 1024 * 1024 * 1024;
1290 // XXX - It is unclear if partial dispatch works. Assume it works at half wave
1291 // granularity. It is probably a full wave.
1292 uint64_t MinGranularity = 32;
1294 unsigned KnownBits = Log2_64(MaxGPUAlloc / MinGranularity);
1295 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), KnownBits);
1297 SDValue TFI = DAG.getTargetFrameIndex(FrameIndex, MVT::i32);
1298 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, TFI,
1299 DAG.getValueType(ExtVT));
1302 bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
1303 if (Intr->getOpcode() != ISD::INTRINSIC_W_CHAIN)
1306 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
1307 default: return false;
1308 case AMDGPUIntrinsic::amdgcn_if:
1309 case AMDGPUIntrinsic::amdgcn_else:
1310 case AMDGPUIntrinsic::amdgcn_break:
1311 case AMDGPUIntrinsic::amdgcn_if_break:
1312 case AMDGPUIntrinsic::amdgcn_else_break:
1313 case AMDGPUIntrinsic::amdgcn_loop:
1314 case AMDGPUIntrinsic::amdgcn_end_cf:
1319 void SITargetLowering::createDebuggerPrologueStackObjects(
1320 MachineFunction &MF) const {
1321 // Create stack objects that are used for emitting debugger prologue.
1323 // Debugger prologue writes work group IDs and work item IDs to scratch memory
1324 // at fixed location in the following format:
1325 // offset 0: work group ID x
1326 // offset 4: work group ID y
1327 // offset 8: work group ID z
1328 // offset 16: work item ID x
1329 // offset 20: work item ID y
1330 // offset 24: work item ID z
1331 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1334 // For each dimension:
1335 for (unsigned i = 0; i < 3; ++i) {
1336 // Create fixed stack object for work group ID.
1337 ObjectIdx = MF.getFrameInfo()->CreateFixedObject(4, i * 4, true);
1338 Info->setDebuggerWorkGroupIDStackObjectIndex(i, ObjectIdx);
1339 // Create fixed stack object for work item ID.
1340 ObjectIdx = MF.getFrameInfo()->CreateFixedObject(4, i * 4 + 16, true);
1341 Info->setDebuggerWorkItemIDStackObjectIndex(i, ObjectIdx);
1345 /// This transforms the control flow intrinsics to get the branch destination as
1346 /// last parameter, also switches branch target with BR if the need arise
1347 SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1348 SelectionDAG &DAG) const {
1352 SDNode *Intr = BRCOND.getOperand(1).getNode();
1353 SDValue Target = BRCOND.getOperand(2);
1354 SDNode *BR = nullptr;
1355 SDNode *SetCC = nullptr;
1357 if (Intr->getOpcode() == ISD::SETCC) {
1358 // As long as we negate the condition everything is fine
1360 Intr = SetCC->getOperand(0).getNode();
1363 // Get the target from BR if we don't negate the condition
1364 BR = findUser(BRCOND, ISD::BR);
1365 Target = BR->getOperand(1);
1368 if (!isCFIntrinsic(Intr)) {
1369 // This is a uniform branch so we don't need to legalize.
1374 (SetCC->getConstantOperandVal(1) == 1 &&
1375 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
1378 // Build the result and
1379 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
1381 // operands of the new intrinsic call
1382 SmallVector<SDValue, 4> Ops;
1383 Ops.push_back(BRCOND.getOperand(0));
1384 Ops.append(Intr->op_begin() + 1, Intr->op_end());
1385 Ops.push_back(Target);
1387 // build the new intrinsic call
1388 SDNode *Result = DAG.getNode(
1389 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
1390 DAG.getVTList(Res), Ops).getNode();
1393 // Give the branch instruction our target
1396 BRCOND.getOperand(2)
1398 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
1399 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
1400 BR = NewBR.getNode();
1403 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
1405 // Copy the intrinsic results to registers
1406 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
1407 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
1411 Chain = DAG.getCopyToReg(
1413 CopyToReg->getOperand(1),
1414 SDValue(Result, i - 1),
1417 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
1420 // Remove the old intrinsic from the chain
1421 DAG.ReplaceAllUsesOfValueWith(
1422 SDValue(Intr, Intr->getNumValues() - 1),
1423 Intr->getOperand(0));
1428 SDValue SITargetLowering::getSegmentAperture(unsigned AS,
1429 SelectionDAG &DAG) const {
1431 MachineFunction &MF = DAG.getMachineFunction();
1432 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1433 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
1434 assert(UserSGPR != AMDGPU::NoRegister);
1436 SDValue QueuePtr = CreateLiveInRegister(
1437 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
1439 // Offset into amd_queue_t for group_segment_aperture_base_hi /
1440 // private_segment_aperture_base_hi.
1441 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
1443 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, QueuePtr,
1444 DAG.getConstant(StructOffset, SL, MVT::i64));
1446 // TODO: Use custom target PseudoSourceValue.
1447 // TODO: We should use the value from the IR intrinsic call, but it might not
1448 // be available and how do we get it?
1449 Value *V = UndefValue::get(PointerType::get(Type::getInt8Ty(*DAG.getContext()),
1450 AMDGPUAS::CONSTANT_ADDRESS));
1452 MachinePointerInfo PtrInfo(V, StructOffset);
1453 return DAG.getLoad(MVT::i32, SL, QueuePtr.getValue(1), Ptr, PtrInfo,
1454 MinAlign(64, StructOffset),
1455 MachineMemOperand::MOInvariant);
1458 SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
1459 SelectionDAG &DAG) const {
1461 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
1463 SDValue Src = ASC->getOperand(0);
1465 // FIXME: Really support non-0 null pointers.
1466 SDValue SegmentNullPtr = DAG.getConstant(-1, SL, MVT::i32);
1467 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
1469 // flat -> local/private
1470 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
1471 if (ASC->getDestAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1472 ASC->getDestAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1473 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
1474 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
1476 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
1477 NonNull, Ptr, SegmentNullPtr);
1481 // local/private -> flat
1482 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
1483 if (ASC->getSrcAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
1484 ASC->getSrcAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
1486 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
1488 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), DAG);
1490 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
1492 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
1493 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
1498 // global <-> flat are no-ops and never emitted.
1500 const MachineFunction &MF = DAG.getMachineFunction();
1501 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
1502 *MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
1503 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
1505 return DAG.getUNDEF(ASC->getValueType(0));
1508 static bool shouldEmitGOTReloc(const GlobalValue *GV,
1509 const TargetMachine &TM) {
1510 return GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
1511 !TM.shouldAssumeDSOLocal(*GV->getParent(), GV);
1515 SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
1516 // We can fold offsets for anything that doesn't require a GOT relocation.
1517 return GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS &&
1518 !shouldEmitGOTReloc(GA->getGlobal(), getTargetMachine());
1521 static SDValue buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
1522 SDLoc DL, unsigned Offset, EVT PtrVT,
1523 unsigned GAFlags = SIInstrInfo::MO_NONE) {
1524 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
1525 // lowered to the following code sequence:
1526 // s_getpc_b64 s[0:1]
1527 // s_add_u32 s0, s0, $symbol
1528 // s_addc_u32 s1, s1, 0
1530 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
1531 // a fixup or relocation is emitted to replace $symbol with a literal
1532 // constant, which is a pc-relative offset from the encoding of the $symbol
1533 // operand to the global variable.
1535 // What we want here is an offset from the value returned by s_getpc
1536 // (which is the address of the s_add_u32 instruction) to the global
1537 // variable, but since the encoding of $symbol starts 4 bytes after the start
1538 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
1539 // small. This requires us to add 4 to the global variable offset in order to
1540 // compute the correct address.
1541 SDValue GA = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4,
1543 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, GA);
1546 SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
1548 SelectionDAG &DAG) const {
1549 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
1551 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
1552 GSD->getAddressSpace() != AMDGPUAS::GLOBAL_ADDRESS)
1553 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
1556 const GlobalValue *GV = GSD->getGlobal();
1557 EVT PtrVT = Op.getValueType();
1559 if (!shouldEmitGOTReloc(GV, getTargetMachine()))
1560 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
1562 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
1563 SIInstrInfo::MO_GOTPCREL);
1565 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
1566 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
1567 const DataLayout &DataLayout = DAG.getDataLayout();
1568 unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
1569 // FIXME: Use a PseudoSourceValue once those can be assigned an address space.
1570 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
1572 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
1573 MachineMemOperand::MOInvariant);
1576 SDValue SITargetLowering::lowerTRAP(SDValue Op,
1577 SelectionDAG &DAG) const {
1578 const MachineFunction &MF = DAG.getMachineFunction();
1579 DiagnosticInfoUnsupported NoTrap(*MF.getFunction(),
1580 "trap handler not supported",
1583 DAG.getContext()->diagnose(NoTrap);
1587 // FIXME: This should really be selected to s_trap, but that requires
1588 // setting up the trap handler for it o do anything.
1589 return DAG.getNode(AMDGPUISD::ENDPGM, SDLoc(Op), MVT::Other,
1593 SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
1594 const SDLoc &DL, SDValue V) const {
1595 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
1596 // the destination register.
1598 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
1599 // so we will end up with redundant moves to m0.
1601 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
1603 // A Null SDValue creates a glue result.
1604 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
1606 return SDValue(M0, 0);
1609 SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
1612 unsigned Offset) const {
1614 SDValue Param = LowerParameter(DAG, MVT::i32, MVT::i32, SL,
1615 DAG.getEntryNode(), Offset, false);
1616 // The local size values will have the hi 16-bits as zero.
1617 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
1618 DAG.getValueType(VT));
1621 static SDValue emitNonHSAIntrinsicError(SelectionDAG& DAG, SDLoc DL, EVT VT) {
1622 DiagnosticInfoUnsupported BadIntrin(*DAG.getMachineFunction().getFunction(),
1623 "non-hsa intrinsic with hsa target",
1625 DAG.getContext()->diagnose(BadIntrin);
1626 return DAG.getUNDEF(VT);
1629 static SDValue emitRemovedIntrinsicError(SelectionDAG& DAG, SDLoc DL, EVT VT) {
1630 DiagnosticInfoUnsupported BadIntrin(*DAG.getMachineFunction().getFunction(),
1631 "intrinsic not supported on subtarget",
1633 DAG.getContext()->diagnose(BadIntrin);
1634 return DAG.getUNDEF(VT);
1637 SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
1638 SelectionDAG &DAG) const {
1639 MachineFunction &MF = DAG.getMachineFunction();
1640 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
1641 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
1643 EVT VT = Op.getValueType();
1645 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1647 // TODO: Should this propagate fast-math-flags?
1649 switch (IntrinsicID) {
1650 case Intrinsic::amdgcn_dispatch_ptr:
1651 case Intrinsic::amdgcn_queue_ptr: {
1652 if (!Subtarget->isAmdHsaOS()) {
1653 DiagnosticInfoUnsupported BadIntrin(
1654 *MF.getFunction(), "unsupported hsa intrinsic without hsa target",
1656 DAG.getContext()->diagnose(BadIntrin);
1657 return DAG.getUNDEF(VT);
1660 auto Reg = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
1661 SIRegisterInfo::DISPATCH_PTR : SIRegisterInfo::QUEUE_PTR;
1662 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass,
1663 TRI->getPreloadedValue(MF, Reg), VT);
1665 case Intrinsic::amdgcn_implicitarg_ptr: {
1666 unsigned offset = getImplicitParameterOffset(MFI, FIRST_IMPLICIT);
1667 return LowerParameterPtr(DAG, DL, DAG.getEntryNode(), offset);
1669 case Intrinsic::amdgcn_kernarg_segment_ptr: {
1671 = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
1672 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT);
1674 case Intrinsic::amdgcn_rcp:
1675 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
1676 case Intrinsic::amdgcn_rsq:
1677 case AMDGPUIntrinsic::AMDGPU_rsq: // Legacy name
1678 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
1679 case Intrinsic::amdgcn_rsq_legacy: {
1680 if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS)
1681 return emitRemovedIntrinsicError(DAG, DL, VT);
1683 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
1685 case Intrinsic::amdgcn_rsq_clamp: {
1686 if (Subtarget->getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
1687 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
1689 Type *Type = VT.getTypeForEVT(*DAG.getContext());
1690 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
1691 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
1693 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
1694 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
1695 DAG.getConstantFP(Max, DL, VT));
1696 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
1697 DAG.getConstantFP(Min, DL, VT));
1699 case Intrinsic::r600_read_ngroups_x:
1700 if (Subtarget->isAmdHsaOS())
1701 return emitNonHSAIntrinsicError(DAG, DL, VT);
1703 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1704 SI::KernelInputOffsets::NGROUPS_X, false);
1705 case Intrinsic::r600_read_ngroups_y:
1706 if (Subtarget->isAmdHsaOS())
1707 return emitNonHSAIntrinsicError(DAG, DL, VT);
1709 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1710 SI::KernelInputOffsets::NGROUPS_Y, false);
1711 case Intrinsic::r600_read_ngroups_z:
1712 if (Subtarget->isAmdHsaOS())
1713 return emitNonHSAIntrinsicError(DAG, DL, VT);
1715 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1716 SI::KernelInputOffsets::NGROUPS_Z, false);
1717 case Intrinsic::r600_read_global_size_x:
1718 if (Subtarget->isAmdHsaOS())
1719 return emitNonHSAIntrinsicError(DAG, DL, VT);
1721 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1722 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
1723 case Intrinsic::r600_read_global_size_y:
1724 if (Subtarget->isAmdHsaOS())
1725 return emitNonHSAIntrinsicError(DAG, DL, VT);
1727 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1728 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
1729 case Intrinsic::r600_read_global_size_z:
1730 if (Subtarget->isAmdHsaOS())
1731 return emitNonHSAIntrinsicError(DAG, DL, VT);
1733 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
1734 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
1735 case Intrinsic::r600_read_local_size_x:
1736 if (Subtarget->isAmdHsaOS())
1737 return emitNonHSAIntrinsicError(DAG, DL, VT);
1739 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1740 SI::KernelInputOffsets::LOCAL_SIZE_X);
1741 case Intrinsic::r600_read_local_size_y:
1742 if (Subtarget->isAmdHsaOS())
1743 return emitNonHSAIntrinsicError(DAG, DL, VT);
1745 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1746 SI::KernelInputOffsets::LOCAL_SIZE_Y);
1747 case Intrinsic::r600_read_local_size_z:
1748 if (Subtarget->isAmdHsaOS())
1749 return emitNonHSAIntrinsicError(DAG, DL, VT);
1751 return lowerImplicitZextParam(DAG, Op, MVT::i16,
1752 SI::KernelInputOffsets::LOCAL_SIZE_Z);
1753 case Intrinsic::amdgcn_read_workdim:
1754 case AMDGPUIntrinsic::AMDGPU_read_workdim: // Legacy name.
1755 // Really only 2 bits.
1756 return lowerImplicitZextParam(DAG, Op, MVT::i8,
1757 getImplicitParameterOffset(MFI, GRID_DIM));
1758 case Intrinsic::amdgcn_workgroup_id_x:
1759 case Intrinsic::r600_read_tgid_x:
1760 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1761 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT);
1762 case Intrinsic::amdgcn_workgroup_id_y:
1763 case Intrinsic::r600_read_tgid_y:
1764 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1765 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT);
1766 case Intrinsic::amdgcn_workgroup_id_z:
1767 case Intrinsic::r600_read_tgid_z:
1768 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32RegClass,
1769 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT);
1770 case Intrinsic::amdgcn_workitem_id_x:
1771 case Intrinsic::r600_read_tidig_x:
1772 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1773 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT);
1774 case Intrinsic::amdgcn_workitem_id_y:
1775 case Intrinsic::r600_read_tidig_y:
1776 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1777 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT);
1778 case Intrinsic::amdgcn_workitem_id_z:
1779 case Intrinsic::r600_read_tidig_z:
1780 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
1781 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT);
1782 case AMDGPUIntrinsic::SI_load_const: {
1788 MachineMemOperand *MMO = MF.getMachineMemOperand(
1789 MachinePointerInfo(),
1790 MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant,
1791 VT.getStoreSize(), 4);
1792 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
1793 Op->getVTList(), Ops, VT, MMO);
1795 case AMDGPUIntrinsic::amdgcn_fdiv_fast: {
1796 return lowerFDIV_FAST(Op, DAG);
1798 case AMDGPUIntrinsic::SI_vs_load_input:
1799 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
1804 case AMDGPUIntrinsic::SI_fs_constant: {
1805 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1806 SDValue Glue = M0.getValue(1);
1807 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
1808 DAG.getConstant(2, DL, MVT::i32), // P0
1809 Op.getOperand(1), Op.getOperand(2), Glue);
1811 case AMDGPUIntrinsic::SI_packf16:
1812 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
1813 return DAG.getUNDEF(MVT::i32);
1815 case AMDGPUIntrinsic::SI_fs_interp: {
1816 SDValue IJ = Op.getOperand(4);
1817 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1818 DAG.getConstant(0, DL, MVT::i32));
1819 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
1820 DAG.getConstant(1, DL, MVT::i32));
1821 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
1822 SDValue Glue = M0.getValue(1);
1823 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
1824 DAG.getVTList(MVT::f32, MVT::Glue),
1825 I, Op.getOperand(1), Op.getOperand(2), Glue);
1826 Glue = SDValue(P1.getNode(), 1);
1827 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
1828 Op.getOperand(1), Op.getOperand(2), Glue);
1830 case Intrinsic::amdgcn_interp_p1: {
1831 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
1832 SDValue Glue = M0.getValue(1);
1833 return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
1834 Op.getOperand(2), Op.getOperand(3), Glue);
1836 case Intrinsic::amdgcn_interp_p2: {
1837 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
1838 SDValue Glue = SDValue(M0.getNode(), 1);
1839 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
1840 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
1843 case Intrinsic::amdgcn_sin:
1844 return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
1846 case Intrinsic::amdgcn_cos:
1847 return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));
1849 case Intrinsic::amdgcn_log_clamp: {
1850 if (Subtarget->getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
1853 DiagnosticInfoUnsupported BadIntrin(
1854 *MF.getFunction(), "intrinsic not supported on subtarget",
1856 DAG.getContext()->diagnose(BadIntrin);
1857 return DAG.getUNDEF(VT);
1859 case Intrinsic::amdgcn_ldexp:
1860 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT,
1861 Op.getOperand(1), Op.getOperand(2));
1863 case Intrinsic::amdgcn_fract:
1864 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
1866 case Intrinsic::amdgcn_class:
1867 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
1868 Op.getOperand(1), Op.getOperand(2));
1869 case Intrinsic::amdgcn_div_fmas:
1870 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
1871 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
1874 case Intrinsic::amdgcn_div_fixup:
1875 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
1876 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
1878 case Intrinsic::amdgcn_trig_preop:
1879 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
1880 Op.getOperand(1), Op.getOperand(2));
1881 case Intrinsic::amdgcn_div_scale: {
1882 // 3rd parameter required to be a constant.
1883 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
1885 return DAG.getUNDEF(VT);
1887 // Translate to the operands expected by the machine instruction. The
1888 // first parameter must be the same as the first instruction.
1889 SDValue Numerator = Op.getOperand(1);
1890 SDValue Denominator = Op.getOperand(2);
1892 // Note this order is opposite of the machine instruction's operations,
1893 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
1894 // intrinsic has the numerator as the first operand to match a normal
1895 // division operation.
1897 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
1899 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
1900 Denominator, Numerator);
1903 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
1907 SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
1908 SelectionDAG &DAG) const {
1909 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1911 case Intrinsic::amdgcn_atomic_inc:
1912 case Intrinsic::amdgcn_atomic_dec: {
1913 MemSDNode *M = cast<MemSDNode>(Op);
1914 unsigned Opc = (IntrID == Intrinsic::amdgcn_atomic_inc) ?
1915 AMDGPUISD::ATOMIC_INC : AMDGPUISD::ATOMIC_DEC;
1917 M->getOperand(0), // Chain
1918 M->getOperand(2), // Ptr
1919 M->getOperand(3) // Value
1922 return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
1923 M->getMemoryVT(), M->getMemOperand());
1930 SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
1931 SelectionDAG &DAG) const {
1932 MachineFunction &MF = DAG.getMachineFunction();
1934 SDValue Chain = Op.getOperand(0);
1935 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1937 switch (IntrinsicID) {
1938 case AMDGPUIntrinsic::SI_sendmsg: {
1939 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
1940 SDValue Glue = Chain.getValue(1);
1941 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
1942 Op.getOperand(2), Glue);
1944 case AMDGPUIntrinsic::SI_tbuffer_store: {
1962 EVT VT = Op.getOperand(3).getValueType();
1964 MachineMemOperand *MMO = MF.getMachineMemOperand(
1965 MachinePointerInfo(),
1966 MachineMemOperand::MOStore,
1967 VT.getStoreSize(), 4);
1968 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
1969 Op->getVTList(), Ops, VT, MMO);
1971 case AMDGPUIntrinsic::AMDGPU_kill: {
1972 if (const ConstantFPSDNode *K = dyn_cast<ConstantFPSDNode>(Op.getOperand(2))) {
1973 if (!K->isNegative())
1984 SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1986 LoadSDNode *Load = cast<LoadSDNode>(Op);
1987 ISD::LoadExtType ExtType = Load->getExtensionType();
1988 EVT MemVT = Load->getMemoryVT();
1990 if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
1991 assert(MemVT == MVT::i1 && "Only i1 non-extloads expected");
1992 // FIXME: Copied from PPC
1993 // First, load into 32 bits, then truncate to 1 bit.
1995 SDValue Chain = Load->getChain();
1996 SDValue BasePtr = Load->getBasePtr();
1997 MachineMemOperand *MMO = Load->getMemOperand();
1999 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
2000 BasePtr, MVT::i8, MMO);
2003 DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD),
2007 return DAG.getMergeValues(Ops, DL);
2010 if (!MemVT.isVector())
2013 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
2014 "Custom lowering for non-i32 vectors hasn't been implemented.");
2016 unsigned AS = Load->getAddressSpace();
2017 if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
2018 AS, Load->getAlignment())) {
2020 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
2021 return DAG.getMergeValues(Ops, DL);
2024 unsigned NumElements = MemVT.getVectorNumElements();
2026 case AMDGPUAS::CONSTANT_ADDRESS:
2027 if (isMemOpUniform(Load))
2029 // Non-uniform loads will be selected to MUBUF instructions, so they
2030 // have the same legalization requires ments as global and private
2034 case AMDGPUAS::GLOBAL_ADDRESS:
2035 case AMDGPUAS::FLAT_ADDRESS:
2036 if (NumElements > 4)
2037 return SplitVectorLoad(Op, DAG);
2038 // v4 loads are supported for private and global memory.
2040 case AMDGPUAS::PRIVATE_ADDRESS: {
2041 // Depending on the setting of the private_element_size field in the
2042 // resource descriptor, we can only make private accesses up to a certain
2044 switch (Subtarget->getMaxPrivateElementSize()) {
2046 return scalarizeVectorLoad(Load, DAG);
2048 if (NumElements > 2)
2049 return SplitVectorLoad(Op, DAG);
2052 // Same as global/flat
2053 if (NumElements > 4)
2054 return SplitVectorLoad(Op, DAG);
2057 llvm_unreachable("unsupported private_element_size");
2060 case AMDGPUAS::LOCAL_ADDRESS: {
2061 if (NumElements > 2)
2062 return SplitVectorLoad(Op, DAG);
2064 if (NumElements == 2)
2067 // If properly aligned, if we split we might be able to use ds_read_b64.
2068 return SplitVectorLoad(Op, DAG);
2075 SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2076 if (Op.getValueType() != MVT::i64)
2080 SDValue Cond = Op.getOperand(0);
2082 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2083 SDValue One = DAG.getConstant(1, DL, MVT::i32);
2085 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
2086 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
2088 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
2089 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
2091 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
2093 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
2094 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
2096 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
2098 SDValue Res = DAG.getBuildVector(MVT::v2i32, DL, {Lo, Hi});
2099 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
2102 // Catch division cases where we can use shortcuts with rcp and rsq
2104 SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,
2105 SelectionDAG &DAG) const {
2107 SDValue LHS = Op.getOperand(0);
2108 SDValue RHS = Op.getOperand(1);
2109 EVT VT = Op.getValueType();
2110 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
2112 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
2113 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals())) &&
2114 CLHS->isExactlyValue(1.0)) {
2115 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
2116 // the CI documentation has a worst case error of 1 ulp.
2117 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
2118 // use it as long as we aren't trying to use denormals.
2120 // 1.0 / sqrt(x) -> rsq(x)
2122 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
2123 // error seems really high at 2^29 ULP.
2124 if (RHS.getOpcode() == ISD::FSQRT)
2125 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
2127 // 1.0 / x -> rcp(x)
2128 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
2132 const SDNodeFlags *Flags = Op->getFlags();
2134 if (Unsafe || Flags->hasAllowReciprocal()) {
2135 // Turn into multiply by the reciprocal.
2136 // x / y -> x * (1.0 / y)
2138 Flags.setUnsafeAlgebra(true);
2139 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
2140 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, &Flags);
2146 // Faster 2.5 ULP division that does not support denormals.
2147 SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {
2149 SDValue LHS = Op.getOperand(1);
2150 SDValue RHS = Op.getOperand(2);
2152 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
2154 const APFloat K0Val(BitsToFloat(0x6f800000));
2155 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
2157 const APFloat K1Val(BitsToFloat(0x2f800000));
2158 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
2160 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2163 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2165 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
2167 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
2169 // TODO: Should this propagate fast-math-flags?
2170 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
2172 // rcp does not support denormals.
2173 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
2175 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
2177 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
2180 SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
2181 if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
2185 SDValue LHS = Op.getOperand(0);
2186 SDValue RHS = Op.getOperand(1);
2188 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2190 SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
2192 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, RHS, RHS, LHS);
2193 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, LHS, RHS, LHS);
2195 // Denominator is scaled to not be denormal, so using rcp is ok.
2196 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, DenominatorScaled);
2198 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, DenominatorScaled);
2200 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, ApproxRcp, One);
2201 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, ApproxRcp);
2203 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, NumeratorScaled, Fma1);
2205 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, NumeratorScaled);
2206 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul);
2207 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, NumeratorScaled);
2209 SDValue Scale = NumeratorScaled.getValue(1);
2210 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32, Fma4, Fma1, Fma3, Scale);
2212 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS);
2215 SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
2216 if (DAG.getTarget().Options.UnsafeFPMath)
2217 return lowerFastUnsafeFDIV(Op, DAG);
2220 SDValue X = Op.getOperand(0);
2221 SDValue Y = Op.getOperand(1);
2223 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
2225 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
2227 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
2229 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
2231 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
2233 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
2235 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
2237 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
2239 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
2241 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
2242 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
2244 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
2245 NegDivScale0, Mul, DivScale1);
2249 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS) {
2250 // Workaround a hardware bug on SI where the condition output from div_scale
2253 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
2255 // Figure out if the scale to use for div_fmas.
2256 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
2257 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
2258 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
2259 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
2261 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
2262 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
2265 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
2267 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
2269 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
2270 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
2271 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
2273 Scale = DivScale1.getValue(1);
2276 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
2277 Fma4, Fma3, Mul, Scale);
2279 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
2282 SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
2283 EVT VT = Op.getValueType();
2286 return LowerFDIV32(Op, DAG);
2289 return LowerFDIV64(Op, DAG);
2291 llvm_unreachable("Unexpected type for fdiv");
2294 SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
2296 StoreSDNode *Store = cast<StoreSDNode>(Op);
2297 EVT VT = Store->getMemoryVT();
2299 if (VT == MVT::i1) {
2300 return DAG.getTruncStore(Store->getChain(), DL,
2301 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
2302 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
2305 assert(VT.isVector() &&
2306 Store->getValue().getValueType().getScalarType() == MVT::i32);
2308 unsigned AS = Store->getAddressSpace();
2309 if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
2310 AS, Store->getAlignment())) {
2311 return expandUnalignedStore(Store, DAG);
2314 unsigned NumElements = VT.getVectorNumElements();
2316 case AMDGPUAS::GLOBAL_ADDRESS:
2317 case AMDGPUAS::FLAT_ADDRESS:
2318 if (NumElements > 4)
2319 return SplitVectorStore(Op, DAG);
2321 case AMDGPUAS::PRIVATE_ADDRESS: {
2322 switch (Subtarget->getMaxPrivateElementSize()) {
2324 return scalarizeVectorStore(Store, DAG);
2326 if (NumElements > 2)
2327 return SplitVectorStore(Op, DAG);
2330 if (NumElements > 4)
2331 return SplitVectorStore(Op, DAG);
2334 llvm_unreachable("unsupported private_element_size");
2337 case AMDGPUAS::LOCAL_ADDRESS: {
2338 if (NumElements > 2)
2339 return SplitVectorStore(Op, DAG);
2341 if (NumElements == 2)
2344 // If properly aligned, if we split we might be able to use ds_write_b64.
2345 return SplitVectorStore(Op, DAG);
2348 llvm_unreachable("unhandled address space");
2352 SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
2354 EVT VT = Op.getValueType();
2355 SDValue Arg = Op.getOperand(0);
2356 // TODO: Should this propagate fast-math-flags?
2357 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
2358 DAG.getNode(ISD::FMUL, DL, VT, Arg,
2359 DAG.getConstantFP(0.5/M_PI, DL,
2362 switch (Op.getOpcode()) {
2364 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
2366 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
2368 llvm_unreachable("Wrong trig opcode");
2372 SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
2373 AtomicSDNode *AtomicNode = cast<AtomicSDNode>(Op);
2374 assert(AtomicNode->isCompareAndSwap());
2375 unsigned AS = AtomicNode->getAddressSpace();
2377 // No custom lowering required for local address space
2378 if (!isFlatGlobalAddrSpace(AS))
2381 // Non-local address space requires custom lowering for atomic compare
2382 // and swap; cmp and swap should be in a v2i32 or v2i64 in case of _X2
2384 SDValue ChainIn = Op.getOperand(0);
2385 SDValue Addr = Op.getOperand(1);
2386 SDValue Old = Op.getOperand(2);
2387 SDValue New = Op.getOperand(3);
2388 EVT VT = Op.getValueType();
2389 MVT SimpleVT = VT.getSimpleVT();
2390 MVT VecType = MVT::getVectorVT(SimpleVT, 2);
2392 SDValue NewOld = DAG.getBuildVector(VecType, DL, {New, Old});
2393 SDValue Ops[] = { ChainIn, Addr, NewOld };
2395 return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(),
2396 Ops, VT, AtomicNode->getMemOperand());
2399 //===----------------------------------------------------------------------===//
2400 // Custom DAG optimizations
2401 //===----------------------------------------------------------------------===//
2403 SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
2404 DAGCombinerInfo &DCI) const {
2405 EVT VT = N->getValueType(0);
2406 EVT ScalarVT = VT.getScalarType();
2407 if (ScalarVT != MVT::f32)
2410 SelectionDAG &DAG = DCI.DAG;
2413 SDValue Src = N->getOperand(0);
2414 EVT SrcVT = Src.getValueType();
2416 // TODO: We could try to match extracting the higher bytes, which would be
2417 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
2418 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
2419 // about in practice.
2420 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
2421 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
2422 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
2423 DCI.AddToWorklist(Cvt.getNode());
2431 /// \brief Return true if the given offset Size in bytes can be folded into
2432 /// the immediate offsets of a memory instruction for the given address space.
2433 static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
2434 const SISubtarget &STI) {
2436 case AMDGPUAS::GLOBAL_ADDRESS: {
2437 // MUBUF instructions a 12-bit offset in bytes.
2438 return isUInt<12>(OffsetSize);
2440 case AMDGPUAS::CONSTANT_ADDRESS: {
2441 // SMRD instructions have an 8-bit offset in dwords on SI and
2442 // a 20-bit offset in bytes on VI.
2443 if (STI.getGeneration() >= SISubtarget::VOLCANIC_ISLANDS)
2444 return isUInt<20>(OffsetSize);
2446 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
2448 case AMDGPUAS::LOCAL_ADDRESS:
2449 case AMDGPUAS::REGION_ADDRESS: {
2450 // The single offset versions have a 16-bit offset in bytes.
2451 return isUInt<16>(OffsetSize);
2453 case AMDGPUAS::PRIVATE_ADDRESS:
2454 // Indirect register addressing does not use any offsets.
2460 // (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
2462 // This is a variant of
2463 // (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
2465 // The normal DAG combiner will do this, but only if the add has one use since
2466 // that would increase the number of instructions.
2468 // This prevents us from seeing a constant offset that can be folded into a
2469 // memory instruction's addressing mode. If we know the resulting add offset of
2470 // a pointer can be folded into an addressing offset, we can replace the pointer
2471 // operand with the add of new constant offset. This eliminates one of the uses,
2472 // and may allow the remaining use to also be simplified.
2474 SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
2476 DAGCombinerInfo &DCI) const {
2477 SDValue N0 = N->getOperand(0);
2478 SDValue N1 = N->getOperand(1);
2480 if (N0.getOpcode() != ISD::ADD)
2483 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
2487 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
2491 // If the resulting offset is too large, we can't fold it into the addressing
2493 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
2494 if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *getSubtarget()))
2497 SelectionDAG &DAG = DCI.DAG;
2499 EVT VT = N->getValueType(0);
2501 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
2502 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
2504 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
2507 SDValue SITargetLowering::performAndCombine(SDNode *N,
2508 DAGCombinerInfo &DCI) const {
2509 if (DCI.isBeforeLegalize())
2512 if (SDValue Base = AMDGPUTargetLowering::performAndCombine(N, DCI))
2515 SelectionDAG &DAG = DCI.DAG;
2517 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
2518 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
2519 SDValue LHS = N->getOperand(0);
2520 SDValue RHS = N->getOperand(1);
2522 if (LHS.getOpcode() == ISD::SETCC &&
2523 RHS.getOpcode() == ISD::SETCC) {
2524 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
2525 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
2527 SDValue X = LHS.getOperand(0);
2528 SDValue Y = RHS.getOperand(0);
2529 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
2532 if (LCC == ISD::SETO) {
2533 if (X != LHS.getOperand(1))
2536 if (RCC == ISD::SETUNE) {
2537 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
2538 if (!C1 || !C1->isInfinity() || C1->isNegative())
2541 const uint32_t Mask = SIInstrFlags::N_NORMAL |
2542 SIInstrFlags::N_SUBNORMAL |
2543 SIInstrFlags::N_ZERO |
2544 SIInstrFlags::P_ZERO |
2545 SIInstrFlags::P_SUBNORMAL |
2546 SIInstrFlags::P_NORMAL;
2548 static_assert(((~(SIInstrFlags::S_NAN |
2549 SIInstrFlags::Q_NAN |
2550 SIInstrFlags::N_INFINITY |
2551 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
2555 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
2556 X, DAG.getConstant(Mask, DL, MVT::i32));
2564 SDValue SITargetLowering::performOrCombine(SDNode *N,
2565 DAGCombinerInfo &DCI) const {
2566 SelectionDAG &DAG = DCI.DAG;
2567 SDValue LHS = N->getOperand(0);
2568 SDValue RHS = N->getOperand(1);
2570 EVT VT = N->getValueType(0);
2571 if (VT == MVT::i64) {
2572 // TODO: This could be a generic combine with a predicate for extracting the
2573 // high half of an integer being free.
2575 // (or i64:x, (zero_extend i32:y)) ->
2576 // i64 (bitcast (v2i32 build_vector (or i32:y, lo_32(x)), hi_32(x)))
2577 if (LHS.getOpcode() == ISD::ZERO_EXTEND &&
2578 RHS.getOpcode() != ISD::ZERO_EXTEND)
2579 std::swap(LHS, RHS);
2581 if (RHS.getOpcode() == ISD::ZERO_EXTEND) {
2582 SDValue ExtSrc = RHS.getOperand(0);
2583 EVT SrcVT = ExtSrc.getValueType();
2584 if (SrcVT == MVT::i32) {
2586 SDValue LowLHS, HiBits;
2587 std::tie(LowLHS, HiBits) = split64BitValue(LHS, DAG);
2588 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc);
2590 DCI.AddToWorklist(LowOr.getNode());
2591 DCI.AddToWorklist(HiBits.getNode());
2593 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
2595 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
2600 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
2601 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
2602 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
2603 SDValue Src = LHS.getOperand(0);
2604 if (Src != RHS.getOperand(0))
2607 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
2608 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
2612 // Only 10 bits are used.
2613 static const uint32_t MaxMask = 0x3ff;
2615 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
2617 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
2618 Src, DAG.getConstant(NewMask, DL, MVT::i32));
2624 SDValue SITargetLowering::performClassCombine(SDNode *N,
2625 DAGCombinerInfo &DCI) const {
2626 SelectionDAG &DAG = DCI.DAG;
2627 SDValue Mask = N->getOperand(1);
2629 // fp_class x, 0 -> false
2630 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
2631 if (CMask->isNullValue())
2632 return DAG.getConstant(0, SDLoc(N), MVT::i1);
2635 if (N->getOperand(0).isUndef())
2636 return DAG.getUNDEF(MVT::i1);
2641 // Constant fold canonicalize.
2642 SDValue SITargetLowering::performFCanonicalizeCombine(
2644 DAGCombinerInfo &DCI) const {
2645 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
2649 SelectionDAG &DAG = DCI.DAG;
2650 const APFloat &C = CFP->getValueAPF();
2652 // Flush denormals to 0 if not enabled.
2653 if (C.isDenormal()) {
2654 EVT VT = N->getValueType(0);
2655 if (VT == MVT::f32 && !Subtarget->hasFP32Denormals())
2656 return DAG.getConstantFP(0.0, SDLoc(N), VT);
2658 if (VT == MVT::f64 && !Subtarget->hasFP64Denormals())
2659 return DAG.getConstantFP(0.0, SDLoc(N), VT);
2663 EVT VT = N->getValueType(0);
2664 APFloat CanonicalQNaN = APFloat::getQNaN(C.getSemantics());
2665 if (C.isSignaling()) {
2666 // Quiet a signaling NaN.
2667 return DAG.getConstantFP(CanonicalQNaN, SDLoc(N), VT);
2670 // Make sure it is the canonical NaN bitpattern.
2672 // TODO: Can we use -1 as the canonical NaN value since it's an inline
2674 if (C.bitcastToAPInt() != CanonicalQNaN.bitcastToAPInt())
2675 return DAG.getConstantFP(CanonicalQNaN, SDLoc(N), VT);
2678 return SDValue(CFP, 0);
2681 static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
2684 return AMDGPUISD::FMAX3;
2686 return AMDGPUISD::SMAX3;
2688 return AMDGPUISD::UMAX3;
2690 return AMDGPUISD::FMIN3;
2692 return AMDGPUISD::SMIN3;
2694 return AMDGPUISD::UMIN3;
2696 llvm_unreachable("Not a min/max opcode");
2700 static SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
2701 SDValue Op0, SDValue Op1, bool Signed) {
2702 ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
2706 ConstantSDNode *K0 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
2711 if (K0->getAPIntValue().sge(K1->getAPIntValue()))
2714 if (K0->getAPIntValue().uge(K1->getAPIntValue()))
2718 EVT VT = K0->getValueType(0);
2719 return DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, VT,
2720 Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
2723 static bool isKnownNeverSNan(SelectionDAG &DAG, SDValue Op) {
2724 if (!DAG.getTargetLoweringInfo().hasFloatingPointExceptions())
2727 return DAG.isKnownNeverNaN(Op);
2730 static SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
2731 SDValue Op0, SDValue Op1) {
2732 ConstantFPSDNode *K1 = dyn_cast<ConstantFPSDNode>(Op1);
2736 ConstantFPSDNode *K0 = dyn_cast<ConstantFPSDNode>(Op0.getOperand(1));
2740 // Ordered >= (although NaN inputs should have folded away by now).
2741 APFloat::cmpResult Cmp = K0->getValueAPF().compare(K1->getValueAPF());
2742 if (Cmp == APFloat::cmpGreaterThan)
2745 // This isn't safe with signaling NaNs because in IEEE mode, min/max on a
2746 // signaling NaN gives a quiet NaN. The quiet NaN input to the min would then
2747 // give the other result, which is different from med3 with a NaN input.
2748 SDValue Var = Op0.getOperand(0);
2749 if (!isKnownNeverSNan(DAG, Var))
2752 return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0),
2753 Var, SDValue(K0, 0), SDValue(K1, 0));
2756 SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
2757 DAGCombinerInfo &DCI) const {
2758 SelectionDAG &DAG = DCI.DAG;
2760 unsigned Opc = N->getOpcode();
2761 SDValue Op0 = N->getOperand(0);
2762 SDValue Op1 = N->getOperand(1);
2764 // Only do this if the inner op has one use since this will just increases
2765 // register pressure for no benefit.
2767 if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY) {
2768 // max(max(a, b), c) -> max3(a, b, c)
2769 // min(min(a, b), c) -> min3(a, b, c)
2770 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
2772 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
2781 // max(a, max(b, c)) -> max3(a, b, c)
2782 // min(a, min(b, c)) -> min3(a, b, c)
2783 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
2785 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
2794 // min(max(x, K0), K1), K0 < K1 -> med3(x, K0, K1)
2795 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
2796 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, true))
2800 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
2801 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, false))
2805 // fminnum(fmaxnum(x, K0), K1), K0 < K1 && !is_snan(x) -> fmed3(x, K0, K1)
2806 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) ||
2807 (Opc == AMDGPUISD::FMIN_LEGACY &&
2808 Op0.getOpcode() == AMDGPUISD::FMAX_LEGACY)) &&
2809 N->getValueType(0) == MVT::f32 && Op0.hasOneUse()) {
2810 if (SDValue Res = performFPMed3ImmCombine(DAG, SDLoc(N), Op0, Op1))
2817 SDValue SITargetLowering::performSetCCCombine(SDNode *N,
2818 DAGCombinerInfo &DCI) const {
2819 SelectionDAG &DAG = DCI.DAG;
2822 SDValue LHS = N->getOperand(0);
2823 SDValue RHS = N->getOperand(1);
2824 EVT VT = LHS.getValueType();
2826 if (VT != MVT::f32 && VT != MVT::f64)
2829 // Match isinf pattern
2830 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
2831 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
2832 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
2833 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
2837 const APFloat &APF = CRHS->getValueAPF();
2838 if (APF.isInfinity() && !APF.isNegative()) {
2839 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
2840 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
2841 DAG.getConstant(Mask, SL, MVT::i32));
2848 SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
2849 DAGCombinerInfo &DCI) const {
2850 SelectionDAG &DAG = DCI.DAG;
2853 switch (N->getOpcode()) {
2855 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
2857 return performSetCCCombine(N, DCI);
2864 case AMDGPUISD::FMIN_LEGACY:
2865 case AMDGPUISD::FMAX_LEGACY: {
2866 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
2867 N->getValueType(0) != MVT::f64 &&
2868 getTargetMachine().getOptLevel() > CodeGenOpt::None)
2869 return performMinMaxCombine(N, DCI);
2873 case AMDGPUISD::CVT_F32_UBYTE0:
2874 case AMDGPUISD::CVT_F32_UBYTE1:
2875 case AMDGPUISD::CVT_F32_UBYTE2:
2876 case AMDGPUISD::CVT_F32_UBYTE3: {
2877 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
2878 SDValue Src = N->getOperand(0);
2880 // TODO: Handle (or x, (srl y, 8)) pattern when known bits are zero.
2881 if (Src.getOpcode() == ISD::SRL) {
2882 // cvt_f32_ubyte0 (srl x, 16) -> cvt_f32_ubyte2 x
2883 // cvt_f32_ubyte1 (srl x, 16) -> cvt_f32_ubyte3 x
2884 // cvt_f32_ubyte0 (srl x, 8) -> cvt_f32_ubyte1 x
2886 if (const ConstantSDNode *C = dyn_cast<ConstantSDNode>(Src.getOperand(1))) {
2887 unsigned SrcOffset = C->getZExtValue() + 8 * Offset;
2888 if (SrcOffset < 32 && SrcOffset % 8 == 0) {
2889 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + SrcOffset / 8, DL,
2890 MVT::f32, Src.getOperand(0));
2895 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
2897 APInt KnownZero, KnownOne;
2898 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
2899 !DCI.isBeforeLegalizeOps());
2900 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
2901 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
2902 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
2903 DCI.CommitTargetLoweringOpt(TLO);
2909 case ISD::UINT_TO_FP: {
2910 return performUCharToFloatCombine(N, DCI);
2913 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2916 EVT VT = N->getValueType(0);
2920 // Only do this if we are not trying to support denormals. v_mad_f32 does
2921 // not support denormals ever.
2922 if (Subtarget->hasFP32Denormals())
2925 SDValue LHS = N->getOperand(0);
2926 SDValue RHS = N->getOperand(1);
2928 // These should really be instruction patterns, but writing patterns with
2929 // source modiifiers is a pain.
2931 // fadd (fadd (a, a), b) -> mad 2.0, a, b
2932 if (LHS.getOpcode() == ISD::FADD) {
2933 SDValue A = LHS.getOperand(0);
2934 if (A == LHS.getOperand(1)) {
2935 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2936 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
2940 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
2941 if (RHS.getOpcode() == ISD::FADD) {
2942 SDValue A = RHS.getOperand(0);
2943 if (A == RHS.getOperand(1)) {
2944 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2945 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
2952 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
2955 EVT VT = N->getValueType(0);
2957 // Try to get the fneg to fold into the source modifier. This undoes generic
2958 // DAG combines and folds them into the mad.
2960 // Only do this if we are not trying to support denormals. v_mad_f32 does
2961 // not support denormals ever.
2962 if (VT == MVT::f32 &&
2963 !Subtarget->hasFP32Denormals()) {
2964 SDValue LHS = N->getOperand(0);
2965 SDValue RHS = N->getOperand(1);
2966 if (LHS.getOpcode() == ISD::FADD) {
2967 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
2969 SDValue A = LHS.getOperand(0);
2970 if (A == LHS.getOperand(1)) {
2971 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
2972 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
2974 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
2978 if (RHS.getOpcode() == ISD::FADD) {
2979 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
2981 SDValue A = RHS.getOperand(0);
2982 if (A == RHS.getOperand(1)) {
2983 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
2984 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
2995 case ISD::ATOMIC_LOAD:
2996 case ISD::ATOMIC_STORE:
2997 case ISD::ATOMIC_CMP_SWAP:
2998 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
2999 case ISD::ATOMIC_SWAP:
3000 case ISD::ATOMIC_LOAD_ADD:
3001 case ISD::ATOMIC_LOAD_SUB:
3002 case ISD::ATOMIC_LOAD_AND:
3003 case ISD::ATOMIC_LOAD_OR:
3004 case ISD::ATOMIC_LOAD_XOR:
3005 case ISD::ATOMIC_LOAD_NAND:
3006 case ISD::ATOMIC_LOAD_MIN:
3007 case ISD::ATOMIC_LOAD_MAX:
3008 case ISD::ATOMIC_LOAD_UMIN:
3009 case ISD::ATOMIC_LOAD_UMAX:
3010 case AMDGPUISD::ATOMIC_INC:
3011 case AMDGPUISD::ATOMIC_DEC: { // TODO: Target mem intrinsics.
3012 if (DCI.isBeforeLegalize())
3015 MemSDNode *MemNode = cast<MemSDNode>(N);
3016 SDValue Ptr = MemNode->getBasePtr();
3018 // TODO: We could also do this for multiplies.
3019 unsigned AS = MemNode->getAddressSpace();
3020 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
3021 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
3023 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
3025 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
3026 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
3032 return performAndCombine(N, DCI);
3034 return performOrCombine(N, DCI);
3035 case AMDGPUISD::FP_CLASS:
3036 return performClassCombine(N, DCI);
3037 case ISD::FCANONICALIZE:
3038 return performFCanonicalizeCombine(N, DCI);
3039 case AMDGPUISD::FRACT:
3040 case AMDGPUISD::RCP:
3041 case AMDGPUISD::RSQ:
3042 case AMDGPUISD::RSQ_LEGACY:
3043 case AMDGPUISD::RSQ_CLAMP:
3044 case AMDGPUISD::LDEXP: {
3045 SDValue Src = N->getOperand(0);
3051 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
3054 /// \brief Analyze the possible immediate value Op
3056 /// Returns -1 if it isn't an immediate, 0 if it's and inline immediate
3057 /// and the immediate value if it's a literal immediate
3058 int32_t SITargetLowering::analyzeImmediate(const SDNode *N) const {
3059 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3061 if (const ConstantSDNode *Node = dyn_cast<ConstantSDNode>(N)) {
3062 if (TII->isInlineConstant(Node->getAPIntValue()))
3065 uint64_t Val = Node->getZExtValue();
3066 return isUInt<32>(Val) ? Val : -1;
3069 if (const ConstantFPSDNode *Node = dyn_cast<ConstantFPSDNode>(N)) {
3070 if (TII->isInlineConstant(Node->getValueAPF().bitcastToAPInt()))
3073 if (Node->getValueType(0) == MVT::f32)
3074 return FloatToBits(Node->getValueAPF().convertToFloat());
3082 /// \brief Helper function for adjustWritemask
3083 static unsigned SubIdx2Lane(unsigned Idx) {
3086 case AMDGPU::sub0: return 0;
3087 case AMDGPU::sub1: return 1;
3088 case AMDGPU::sub2: return 2;
3089 case AMDGPU::sub3: return 3;
3093 /// \brief Adjust the writemask of MIMG instructions
3094 void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
3095 SelectionDAG &DAG) const {
3096 SDNode *Users[4] = { };
3098 unsigned DmaskIdx = (Node->getNumOperands() - Node->getNumValues() == 9) ? 2 : 3;
3099 unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx);
3100 unsigned NewDmask = 0;
3102 // Try to figure out the used register components
3103 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
3106 // Abort if we can't understand the usage
3107 if (!I->isMachineOpcode() ||
3108 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
3111 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
3112 // Note that subregs are packed, i.e. Lane==0 is the first bit set
3113 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
3115 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
3117 // Set which texture component corresponds to the lane.
3119 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
3121 Comp = countTrailingZeros(Dmask);
3122 Dmask &= ~(1 << Comp);
3125 // Abort if we have more than one user per component
3130 NewDmask |= 1 << Comp;
3133 // Abort if there's no change
3134 if (NewDmask == OldDmask)
3137 // Adjust the writemask in the node
3138 std::vector<SDValue> Ops;
3139 Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
3140 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
3141 Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
3142 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
3144 // If we only got one lane, replace it with a copy
3145 // (if NewDmask has only one bit set...)
3146 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
3147 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
3149 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
3150 SDLoc(), Users[Lane]->getValueType(0),
3151 SDValue(Node, 0), RC);
3152 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
3156 // Update the users of the node with the new indices
3157 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
3159 SDNode *User = Users[i];
3163 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
3164 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
3168 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
3169 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
3170 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
3175 static bool isFrameIndexOp(SDValue Op) {
3176 if (Op.getOpcode() == ISD::AssertZext)
3177 Op = Op.getOperand(0);
3179 return isa<FrameIndexSDNode>(Op);
3182 /// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
3183 /// with frame index operands.
3184 /// LLVM assumes that inputs are to these instructions are registers.
3185 void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
3186 SelectionDAG &DAG) const {
3188 SmallVector<SDValue, 8> Ops;
3189 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
3190 if (!isFrameIndexOp(Node->getOperand(i))) {
3191 Ops.push_back(Node->getOperand(i));
3196 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
3197 Node->getOperand(i).getValueType(),
3198 Node->getOperand(i)), 0));
3201 DAG.UpdateNodeOperands(Node, Ops);
3204 /// \brief Fold the instructions after selecting them.
3205 SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
3206 SelectionDAG &DAG) const {
3207 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3208 unsigned Opcode = Node->getMachineOpcode();
3210 if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
3211 !TII->isGather4(Opcode))
3212 adjustWritemask(Node, DAG);
3214 if (Opcode == AMDGPU::INSERT_SUBREG ||
3215 Opcode == AMDGPU::REG_SEQUENCE) {
3216 legalizeTargetIndependentNode(Node, DAG);
3222 /// \brief Assign the register class depending on the number of
3223 /// bits set in the writemask
3224 void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
3225 SDNode *Node) const {
3226 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3228 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
3230 if (TII->isVOP3(MI.getOpcode())) {
3231 // Make sure constant bus requirements are respected.
3232 TII->legalizeOperandsVOP3(MRI, MI);
3236 if (TII->isMIMG(MI)) {
3237 unsigned VReg = MI.getOperand(0).getReg();
3238 unsigned DmaskIdx = MI.getNumOperands() == 12 ? 3 : 4;
3239 unsigned Writemask = MI.getOperand(DmaskIdx).getImm();
3240 unsigned BitsSet = 0;
3241 for (unsigned i = 0; i < 4; ++i)
3242 BitsSet += Writemask & (1 << i) ? 1 : 0;
3244 const TargetRegisterClass *RC;
3247 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
3248 case 2: RC = &AMDGPU::VReg_64RegClass; break;
3249 case 3: RC = &AMDGPU::VReg_96RegClass; break;
3252 unsigned NewOpcode = TII->getMaskedMIMGOp(MI.getOpcode(), BitsSet);
3253 MI.setDesc(TII->get(NewOpcode));
3254 MRI.setRegClass(VReg, RC);
3258 // Replace unused atomics with the no return version.
3259 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode());
3260 if (NoRetAtomicOp != -1) {
3261 if (!Node->hasAnyUseOfValue(0)) {
3262 MI.setDesc(TII->get(NoRetAtomicOp));
3263 MI.RemoveOperand(0);
3267 // For mubuf_atomic_cmpswap, we need to have tablegen use an extract_subreg
3268 // instruction, because the return type of these instructions is a vec2 of
3269 // the memory type, so it can be tied to the input operand.
3270 // This means these instructions always have a use, so we need to add a
3271 // special case to check if the atomic has only one extract_subreg use,
3272 // which itself has no uses.
3273 if ((Node->hasNUsesOfValue(1, 0) &&
3274 Node->use_begin()->isMachineOpcode() &&
3275 Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG &&
3276 !Node->use_begin()->hasAnyUseOfValue(0))) {
3277 unsigned Def = MI.getOperand(0).getReg();
3279 // Change this into a noret atomic.
3280 MI.setDesc(TII->get(NoRetAtomicOp));
3281 MI.RemoveOperand(0);
3283 // If we only remove the def operand from the atomic instruction, the
3284 // extract_subreg will be left with a use of a vreg without a def.
3285 // So we need to insert an implicit_def to avoid machine verifier
3287 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
3288 TII->get(AMDGPU::IMPLICIT_DEF), Def);
3294 static SDValue buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL,
3296 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
3297 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
3300 MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
3302 SDValue Ptr) const {
3303 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3305 // Build the half of the subregister with the constants before building the
3306 // full 128-bit register. If we are building multiple resource descriptors,
3307 // this will allow CSEing of the 2-component register.
3308 const SDValue Ops0[] = {
3309 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
3310 buildSMovImm32(DAG, DL, 0),
3311 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
3312 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
3313 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
3316 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
3317 MVT::v2i32, Ops0), 0);
3319 // Combine the constants and the pointer.
3320 const SDValue Ops1[] = {
3321 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
3323 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
3325 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
3328 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
3331 /// \brief Return a resource descriptor with the 'Add TID' bit enabled
3332 /// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
3333 /// of the resource descriptor) to create an offset, which is added to
3334 /// the resource pointer.
3335 MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
3336 SDValue Ptr, uint32_t RsrcDword1,
3337 uint64_t RsrcDword2And3) const {
3338 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
3339 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
3341 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
3342 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
3346 SDValue DataLo = buildSMovImm32(DAG, DL,
3347 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
3348 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
3350 const SDValue Ops[] = {
3351 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
3353 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
3355 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
3357 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
3359 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
3362 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
3365 SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
3366 const TargetRegisterClass *RC,
3367 unsigned Reg, EVT VT) const {
3368 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
3370 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
3371 cast<RegisterSDNode>(VReg)->getReg(), VT);
3374 //===----------------------------------------------------------------------===//
3375 // SI Inline Assembly Support
3376 //===----------------------------------------------------------------------===//
3378 std::pair<unsigned, const TargetRegisterClass *>
3379 SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3380 StringRef Constraint,
3383 if (Constraint.size() == 1) {
3384 switch (Constraint[0]) {
3387 switch (VT.getSizeInBits()) {
3389 return std::make_pair(0U, nullptr);
3391 return std::make_pair(0U, &AMDGPU::SGPR_32RegClass);
3393 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
3395 return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
3397 return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
3401 switch (VT.getSizeInBits()) {
3403 return std::make_pair(0U, nullptr);
3405 return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
3407 return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
3409 return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
3411 return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
3413 return std::make_pair(0U, &AMDGPU::VReg_256RegClass);
3415 return std::make_pair(0U, &AMDGPU::VReg_512RegClass);
3420 if (Constraint.size() > 1) {
3421 const TargetRegisterClass *RC = nullptr;
3422 if (Constraint[1] == 'v') {
3423 RC = &AMDGPU::VGPR_32RegClass;
3424 } else if (Constraint[1] == 's') {
3425 RC = &AMDGPU::SGPR_32RegClass;
3430 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
3431 if (!Failed && Idx < RC->getNumRegs())
3432 return std::make_pair(RC->getRegister(Idx), RC);
3435 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3438 SITargetLowering::ConstraintType
3439 SITargetLowering::getConstraintType(StringRef Constraint) const {
3440 if (Constraint.size() == 1) {
3441 switch (Constraint[0]) {
3445 return C_RegisterClass;
3448 return TargetLowering::getConstraintType(Constraint);