1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering final : public AMDGPUTargetLowering {
24 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
25 SDValue Chain, uint64_t Offset) const;
26 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
27 const SDLoc &SL, SDValue Chain,
28 uint64_t Offset, bool Signed,
29 const ISD::InputArg *Arg = nullptr) const;
31 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
32 const SDLoc &SL, SDValue Chain,
33 const ISD::InputArg &Arg) const;
35 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
36 SelectionDAG &DAG) const override;
37 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
38 MVT VT, unsigned Offset) const;
40 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
41 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
43 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
44 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
45 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
46 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
51 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
52 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
57 /// \brief Converts \p Op, which must be of floating point type, to the
58 /// floating point type \p VT, by either extending or truncating it.
59 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
64 SDValue convertArgType(
65 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
66 bool Signed, const ISD::InputArg *Arg = nullptr) const;
68 /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16.
69 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
71 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
72 SelectionDAG &DAG) const;
74 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
75 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
76 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
77 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
79 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
81 SDValue performUCharToFloatCombine(SDNode *N,
82 DAGCombinerInfo &DCI) const;
83 SDValue performSHLPtrCombine(SDNode *N,
85 DAGCombinerInfo &DCI) const;
87 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
89 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
90 unsigned Opc, SDValue LHS,
91 const ConstantSDNode *CRHS) const;
93 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
94 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
95 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
96 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
97 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
98 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
100 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
101 SDValue Op0, SDValue Op1) const;
102 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
103 SDValue Op0, SDValue Op1, bool Signed) const;
104 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
105 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
106 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
107 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
109 unsigned getFusedOpcode(const SelectionDAG &DAG,
110 const SDNode *N0, const SDNode *N1) const;
111 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
112 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
113 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
114 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
115 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
116 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
117 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
119 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
120 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
122 unsigned isCFIntrinsic(const SDNode *Intr) const;
124 void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
126 /// \returns True if fixup needs to be emitted for given global value \p GV,
128 bool shouldEmitFixup(const GlobalValue *GV) const;
130 /// \returns True if GOT relocation needs to be emitted for given global value
131 /// \p GV, false otherwise.
132 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
134 /// \returns True if PC-relative relocation needs to be emitted for given
135 /// global value \p GV, false otherwise.
136 bool shouldEmitPCReloc(const GlobalValue *GV) const;
139 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
141 const SISubtarget *getSubtarget() const;
143 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
144 EVT /*VT*/) const override;
146 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
147 unsigned IntrinsicID) const override;
149 bool getAddrModeArguments(IntrinsicInst * /*I*/,
150 SmallVectorImpl<Value*> &/*Ops*/,
151 Type *&/*AccessTy*/) const override;
153 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
154 unsigned AS) const override;
156 bool canMergeStoresTo(unsigned AS, EVT MemVT,
157 const SelectionDAG &DAG) const override;
159 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
161 bool *IsFast) const override;
163 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
164 unsigned SrcAlign, bool IsMemset,
167 MachineFunction &MF) const override;
169 bool isMemOpUniform(const SDNode *N) const;
170 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
171 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
172 bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
174 TargetLoweringBase::LegalizeTypeAction
175 getPreferredVectorAction(EVT VT) const override;
177 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
178 Type *Ty) const override;
180 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
182 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
184 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
186 const SmallVectorImpl<ISD::InputArg> &Ins,
187 const SDLoc &DL, SelectionDAG &DAG,
188 SmallVectorImpl<SDValue> &InVals) const override;
190 bool CanLowerReturn(CallingConv::ID CallConv,
191 MachineFunction &MF, bool isVarArg,
192 const SmallVectorImpl<ISD::OutputArg> &Outs,
193 LLVMContext &Context) const override;
195 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
196 const SmallVectorImpl<ISD::OutputArg> &Outs,
197 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
198 SelectionDAG &DAG) const override;
200 unsigned getRegisterByName(const char* RegName, EVT VT,
201 SelectionDAG &DAG) const override;
203 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
204 MachineBasicBlock *BB) const;
207 EmitInstrWithCustomInserter(MachineInstr &MI,
208 MachineBasicBlock *BB) const override;
209 bool enableAggressiveFMAFusion(EVT VT) const override;
210 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
211 EVT VT) const override;
212 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
213 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
214 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
215 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
216 SelectionDAG &DAG) const override;
218 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
219 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
220 void AdjustInstrPostInstrSelection(MachineInstr &MI,
221 SDNode *Node) const override;
223 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
225 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
227 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
228 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
229 std::pair<unsigned, const TargetRegisterClass *>
230 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
231 StringRef Constraint, MVT VT) const override;
232 ConstraintType getConstraintType(StringRef Constraint) const override;
233 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
236 void finalizeLowering(MachineFunction &MF) const override;
239 } // End namespace llvm