1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "AMDGPUArgumentUsageInfo.h"
20 #include "SIInstrInfo.h"
24 class SITargetLowering final : public AMDGPUTargetLowering {
25 SDValue lowerKernArgParameterPtr(SelectionDAG &DAG, const SDLoc &SL,
26 SDValue Chain, uint64_t Offset) const;
27 SDValue getImplicitArgPtr(SelectionDAG &DAG, const SDLoc &SL) const;
28 SDValue lowerKernargMemParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
29 const SDLoc &SL, SDValue Chain,
30 uint64_t Offset, bool Signed,
31 const ISD::InputArg *Arg = nullptr) const;
33 SDValue lowerStackParameter(SelectionDAG &DAG, CCValAssign &VA,
34 const SDLoc &SL, SDValue Chain,
35 const ISD::InputArg &Arg) const;
36 SDValue getPreloadedValue(SelectionDAG &DAG,
37 const SIMachineFunctionInfo &MFI,
39 AMDGPUFunctionArgInfo::PreloadedValue) const;
41 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
42 SelectionDAG &DAG) const override;
43 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
44 MVT VT, unsigned Offset) const;
46 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
49 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
50 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
51 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
52 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
53 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
54 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
55 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
56 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
57 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
58 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
59 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
60 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
61 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
63 /// \brief Converts \p Op, which must be of floating point type, to the
64 /// floating point type \p VT, by either extending or truncating it.
65 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
70 SDValue convertArgType(
71 SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL, SDValue Val,
72 bool Signed, const ISD::InputArg *Arg = nullptr) const;
74 /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16.
75 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
77 SDValue getSegmentAperture(unsigned AS, const SDLoc &DL,
78 SelectionDAG &DAG) const;
80 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
81 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
82 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
83 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
85 SDNode *adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
87 SDValue performUCharToFloatCombine(SDNode *N,
88 DAGCombinerInfo &DCI) const;
89 SDValue performSHLPtrCombine(SDNode *N,
92 DAGCombinerInfo &DCI) const;
94 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
96 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
97 unsigned Opc, SDValue LHS,
98 const ConstantSDNode *CRHS) const;
100 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
101 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
102 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
103 SDValue performZeroExtendCombine(SDNode *N, DAGCombinerInfo &DCI) const;
104 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
105 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
107 SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
108 SDValue Op0, SDValue Op1) const;
109 SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
110 SDValue Op0, SDValue Op1, bool Signed) const;
111 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
112 SDValue performFMed3Combine(SDNode *N, DAGCombinerInfo &DCI) const;
113 SDValue performCvtPkRTZCombine(SDNode *N, DAGCombinerInfo &DCI) const;
114 SDValue performExtractVectorEltCombine(SDNode *N, DAGCombinerInfo &DCI) const;
115 SDValue performBuildVectorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
117 unsigned getFusedOpcode(const SelectionDAG &DAG,
118 const SDNode *N0, const SDNode *N1) const;
119 SDValue performAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
120 SDValue performAddCarrySubCarryCombine(SDNode *N, DAGCombinerInfo &DCI) const;
121 SDValue performSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
122 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
123 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
124 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
125 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
127 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
128 bool isLegalGlobalAddressingMode(const AddrMode &AM) const;
129 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
131 unsigned isCFIntrinsic(const SDNode *Intr) const;
133 void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
135 /// \returns True if fixup needs to be emitted for given global value \p GV,
137 bool shouldEmitFixup(const GlobalValue *GV) const;
139 /// \returns True if GOT relocation needs to be emitted for given global value
140 /// \p GV, false otherwise.
141 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
143 /// \returns True if PC-relative relocation needs to be emitted for given
144 /// global value \p GV, false otherwise.
145 bool shouldEmitPCReloc(const GlobalValue *GV) const;
148 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
150 const SISubtarget *getSubtarget() const;
152 bool isShuffleMaskLegal(ArrayRef<int> /*Mask*/, EVT /*VT*/) const override;
154 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
156 unsigned IntrinsicID) const override;
158 bool getAddrModeArguments(IntrinsicInst * /*I*/,
159 SmallVectorImpl<Value*> &/*Ops*/,
160 Type *&/*AccessTy*/) const override;
162 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
164 Instruction *I = nullptr) const override;
166 bool canMergeStoresTo(unsigned AS, EVT MemVT,
167 const SelectionDAG &DAG) const override;
169 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
171 bool *IsFast) const override;
173 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
174 unsigned SrcAlign, bool IsMemset,
177 MachineFunction &MF) const override;
179 bool isMemOpUniform(const SDNode *N) const;
180 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
181 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
182 bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
184 TargetLoweringBase::LegalizeTypeAction
185 getPreferredVectorAction(EVT VT) const override;
187 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
188 Type *Ty) const override;
190 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
192 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
194 bool supportSplitCSR(MachineFunction *MF) const override;
195 void initializeSplitCSR(MachineBasicBlock *Entry) const override;
196 void insertCopiesSplitCSR(
197 MachineBasicBlock *Entry,
198 const SmallVectorImpl<MachineBasicBlock *> &Exits) const override;
200 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
202 const SmallVectorImpl<ISD::InputArg> &Ins,
203 const SDLoc &DL, SelectionDAG &DAG,
204 SmallVectorImpl<SDValue> &InVals) const override;
206 bool CanLowerReturn(CallingConv::ID CallConv,
207 MachineFunction &MF, bool isVarArg,
208 const SmallVectorImpl<ISD::OutputArg> &Outs,
209 LLVMContext &Context) const override;
211 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
212 const SmallVectorImpl<ISD::OutputArg> &Outs,
213 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
214 SelectionDAG &DAG) const override;
216 void passSpecialInputs(
217 CallLoweringInfo &CLI,
218 const SIMachineFunctionInfo &Info,
219 SmallVectorImpl<std::pair<unsigned, SDValue>> &RegsToPass,
220 SmallVectorImpl<SDValue> &MemOpChains,
222 SDValue StackPtr) const;
224 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
225 CallingConv::ID CallConv, bool isVarArg,
226 const SmallVectorImpl<ISD::InputArg> &Ins,
227 const SDLoc &DL, SelectionDAG &DAG,
228 SmallVectorImpl<SDValue> &InVals, bool isThisReturn,
229 SDValue ThisVal) const;
231 bool mayBeEmittedAsTailCall(const CallInst *) const override;
233 bool isEligibleForTailCallOptimization(
234 SDValue Callee, CallingConv::ID CalleeCC, bool isVarArg,
235 const SmallVectorImpl<ISD::OutputArg> &Outs,
236 const SmallVectorImpl<SDValue> &OutVals,
237 const SmallVectorImpl<ISD::InputArg> &Ins, SelectionDAG &DAG) const;
239 SDValue LowerCall(CallLoweringInfo &CLI,
240 SmallVectorImpl<SDValue> &InVals) const override;
242 unsigned getRegisterByName(const char* RegName, EVT VT,
243 SelectionDAG &DAG) const override;
245 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
246 MachineBasicBlock *BB) const;
249 EmitInstrWithCustomInserter(MachineInstr &MI,
250 MachineBasicBlock *BB) const override;
252 bool hasBitPreservingFPLogic(EVT VT) const override;
253 bool enableAggressiveFMAFusion(EVT VT) const override;
254 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
255 EVT VT) const override;
256 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
257 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
258 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
259 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue> &Results,
260 SelectionDAG &DAG) const override;
262 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
263 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
264 void AdjustInstrPostInstrSelection(MachineInstr &MI,
265 SDNode *Node) const override;
267 SDNode *legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
269 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
271 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
272 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
273 std::pair<unsigned, const TargetRegisterClass *>
274 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
275 StringRef Constraint, MVT VT) const override;
276 ConstraintType getConstraintType(StringRef Constraint) const override;
277 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
280 void finalizeLowering(MachineFunction &MF) const override;
282 void computeKnownBitsForFrameIndex(const SDValue Op,
284 const APInt &DemandedElts,
285 const SelectionDAG &DAG,
286 unsigned Depth = 0) const override;
289 } // End namespace llvm