1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering final : public AMDGPUTargetLowering {
24 SDValue LowerParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain,
25 unsigned Offset) const;
26 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL,
27 SDValue Chain, unsigned Offset, bool Signed) const;
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
30 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
31 MVT VT, unsigned Offset) const;
33 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerFrameIndex(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
38 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
39 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
40 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
41 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
43 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
44 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
45 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
50 SDValue getSegmentAperture(unsigned AS, SelectionDAG &DAG) const;
51 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
52 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
54 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
56 SDValue performUCharToFloatCombine(SDNode *N,
57 DAGCombinerInfo &DCI) const;
58 SDValue performSHLPtrCombine(SDNode *N,
60 DAGCombinerInfo &DCI) const;
61 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
62 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
63 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
64 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
66 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
68 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
70 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
71 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
73 bool isCFIntrinsic(const SDNode *Intr) const;
75 void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
77 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
79 const SISubtarget *getSubtarget() const;
81 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
82 unsigned IntrinsicID) const override;
84 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
85 EVT /*VT*/) const override;
87 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
88 unsigned AS) const override;
90 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
92 bool *IsFast) const override;
94 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
95 unsigned SrcAlign, bool IsMemset,
98 MachineFunction &MF) const override;
100 bool isMemOpUniform(const SDNode *N) const;
101 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
103 TargetLoweringBase::LegalizeTypeAction
104 getPreferredVectorAction(EVT VT) const override;
106 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
107 Type *Ty) const override;
109 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
111 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
113 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
115 const SmallVectorImpl<ISD::InputArg> &Ins,
116 const SDLoc &DL, SelectionDAG &DAG,
117 SmallVectorImpl<SDValue> &InVals) const override;
119 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
120 const SmallVectorImpl<ISD::OutputArg> &Outs,
121 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
122 SelectionDAG &DAG) const override;
124 unsigned getRegisterByName(const char* RegName, EVT VT,
125 SelectionDAG &DAG) const override;
127 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
128 MachineBasicBlock *BB) const;
131 EmitInstrWithCustomInserter(MachineInstr &MI,
132 MachineBasicBlock *BB) const override;
133 bool enableAggressiveFMAFusion(EVT VT) const override;
134 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
135 EVT VT) const override;
136 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
137 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
138 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
139 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
140 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
141 void AdjustInstrPostInstrSelection(MachineInstr &MI,
142 SDNode *Node) const override;
144 int32_t analyzeImmediate(const SDNode *N) const;
145 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
146 unsigned Reg, EVT VT) const override;
147 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
149 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
151 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
152 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
153 std::pair<unsigned, const TargetRegisterClass *>
154 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
155 StringRef Constraint, MVT VT) const override;
156 ConstraintType getConstraintType(StringRef Constraint) const override;
157 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
161 } // End namespace llvm