1 //===-- SIISelLowering.h - SI DAG Lowering Interface ------------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief SI DAG Lowering interface definition
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIISELLOWERING_H
18 #include "AMDGPUISelLowering.h"
19 #include "SIInstrInfo.h"
23 class SITargetLowering final : public AMDGPUTargetLowering {
24 SDValue LowerParameterPtr(SelectionDAG &DAG, const SDLoc &SL, SDValue Chain,
25 unsigned Offset) const;
26 SDValue LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT, const SDLoc &SL,
27 SDValue Chain, unsigned Offset, bool Signed) const;
28 SDValue LowerGlobalAddress(AMDGPUMachineFunction *MFI, SDValue Op,
29 SelectionDAG &DAG) const override;
30 SDValue lowerImplicitZextParam(SelectionDAG &DAG, SDValue Op,
31 MVT VT, unsigned Offset) const;
33 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
34 SDValue LowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
35 SDValue LowerINTRINSIC_VOID(SDValue Op, SelectionDAG &DAG) const;
36 SDValue LowerLOAD(SDValue Op, SelectionDAG &DAG) const;
37 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
38 SDValue lowerFastUnsafeFDIV(SDValue Op, SelectionDAG &DAG) const;
39 SDValue lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const;
40 SDValue LowerFDIV16(SDValue Op, SelectionDAG &DAG) const;
41 SDValue LowerFDIV32(SDValue Op, SelectionDAG &DAG) const;
42 SDValue LowerFDIV64(SDValue Op, SelectionDAG &DAG) const;
43 SDValue LowerFDIV(SDValue Op, SelectionDAG &DAG) const;
44 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG, bool Signed) const;
45 SDValue LowerSTORE(SDValue Op, SelectionDAG &DAG) const;
46 SDValue LowerTrig(SDValue Op, SelectionDAG &DAG) const;
47 SDValue LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
48 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
50 /// \brief Converts \p Op, which must be of floating point type, to the
51 /// floating point type \p VT, by either extending or truncating it.
52 SDValue getFPExtOrFPTrunc(SelectionDAG &DAG,
57 /// \brief Custom lowering for ISD::FP_ROUND for MVT::f16.
58 SDValue lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
60 SDValue getSegmentAperture(unsigned AS, SelectionDAG &DAG) const;
61 SDValue lowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) const;
62 SDValue lowerTRAP(SDValue Op, SelectionDAG &DAG) const;
64 void adjustWritemask(MachineSDNode *&N, SelectionDAG &DAG) const;
66 SDValue performUCharToFloatCombine(SDNode *N,
67 DAGCombinerInfo &DCI) const;
68 SDValue performSHLPtrCombine(SDNode *N,
70 DAGCombinerInfo &DCI) const;
72 SDValue performMemSDNodeCombine(MemSDNode *N, DAGCombinerInfo &DCI) const;
74 SDValue splitBinaryBitConstantOp(DAGCombinerInfo &DCI, const SDLoc &SL,
75 unsigned Opc, SDValue LHS,
76 const ConstantSDNode *CRHS) const;
78 SDValue performAndCombine(SDNode *N, DAGCombinerInfo &DCI) const;
79 SDValue performOrCombine(SDNode *N, DAGCombinerInfo &DCI) const;
80 SDValue performXorCombine(SDNode *N, DAGCombinerInfo &DCI) const;
81 SDValue performClassCombine(SDNode *N, DAGCombinerInfo &DCI) const;
82 SDValue performFCanonicalizeCombine(SDNode *N, DAGCombinerInfo &DCI) const;
84 SDValue performMinMaxCombine(SDNode *N, DAGCombinerInfo &DCI) const;
86 unsigned getFusedOpcode(const SelectionDAG &DAG,
87 const SDNode *N0, const SDNode *N1) const;
88 SDValue performFAddCombine(SDNode *N, DAGCombinerInfo &DCI) const;
89 SDValue performFSubCombine(SDNode *N, DAGCombinerInfo &DCI) const;
90 SDValue performSetCCCombine(SDNode *N, DAGCombinerInfo &DCI) const;
91 SDValue performCvtF32UByteNCombine(SDNode *N, DAGCombinerInfo &DCI) const;
93 bool isLegalFlatAddressingMode(const AddrMode &AM) const;
94 bool isLegalMUBUFAddressingMode(const AddrMode &AM) const;
96 bool isCFIntrinsic(const SDNode *Intr) const;
98 void createDebuggerPrologueStackObjects(MachineFunction &MF) const;
100 /// \returns True if fixup needs to be emitted for given global value \p GV,
102 bool shouldEmitFixup(const GlobalValue *GV) const;
104 /// \returns True if GOT relocation needs to be emitted for given global value
105 /// \p GV, false otherwise.
106 bool shouldEmitGOTReloc(const GlobalValue *GV) const;
108 /// \returns True if PC-relative relocation needs to be emitted for given
109 /// global value \p GV, false otherwise.
110 bool shouldEmitPCReloc(const GlobalValue *GV) const;
113 SITargetLowering(const TargetMachine &tm, const SISubtarget &STI);
115 const SISubtarget *getSubtarget() const;
117 bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &,
118 unsigned IntrinsicID) const override;
120 bool isShuffleMaskLegal(const SmallVectorImpl<int> &/*Mask*/,
121 EVT /*VT*/) const override;
123 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM, Type *Ty,
124 unsigned AS) const override;
126 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
128 bool *IsFast) const override;
130 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
131 unsigned SrcAlign, bool IsMemset,
134 MachineFunction &MF) const override;
136 bool isMemOpUniform(const SDNode *N) const;
137 bool isMemOpHasNoClobberedMemOperand(const SDNode *N) const;
138 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
139 bool isCheapAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
141 TargetLoweringBase::LegalizeTypeAction
142 getPreferredVectorAction(EVT VT) const override;
144 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
145 Type *Ty) const override;
147 bool isTypeDesirableForOp(unsigned Op, EVT VT) const override;
149 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
151 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
153 const SmallVectorImpl<ISD::InputArg> &Ins,
154 const SDLoc &DL, SelectionDAG &DAG,
155 SmallVectorImpl<SDValue> &InVals) const override;
157 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
158 const SmallVectorImpl<ISD::OutputArg> &Outs,
159 const SmallVectorImpl<SDValue> &OutVals, const SDLoc &DL,
160 SelectionDAG &DAG) const override;
162 unsigned getRegisterByName(const char* RegName, EVT VT,
163 SelectionDAG &DAG) const override;
165 MachineBasicBlock *splitKillBlock(MachineInstr &MI,
166 MachineBasicBlock *BB) const;
169 EmitInstrWithCustomInserter(MachineInstr &MI,
170 MachineBasicBlock *BB) const override;
171 bool enableAggressiveFMAFusion(EVT VT) const override;
172 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
173 EVT VT) const override;
174 MVT getScalarShiftAmountTy(const DataLayout &, EVT) const override;
175 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
176 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
177 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
178 SDNode *PostISelFolding(MachineSDNode *N, SelectionDAG &DAG) const override;
179 void AdjustInstrPostInstrSelection(MachineInstr &MI,
180 SDNode *Node) const override;
182 SDValue CreateLiveInRegister(SelectionDAG &DAG, const TargetRegisterClass *RC,
183 unsigned Reg, EVT VT) const override;
184 void legalizeTargetIndependentNode(SDNode *Node, SelectionDAG &DAG) const;
186 MachineSDNode *wrapAddr64Rsrc(SelectionDAG &DAG, const SDLoc &DL,
188 MachineSDNode *buildRSRC(SelectionDAG &DAG, const SDLoc &DL, SDValue Ptr,
189 uint32_t RsrcDword1, uint64_t RsrcDword2And3) const;
190 std::pair<unsigned, const TargetRegisterClass *>
191 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
192 StringRef Constraint, MVT VT) const override;
193 ConstraintType getConstraintType(StringRef Constraint) const override;
194 SDValue copyToM0(SelectionDAG &DAG, SDValue Chain, const SDLoc &DL,
198 } // End namespace llvm