1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= SISubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "SISubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
17 // Execpt for the NONE field, this must be kept in sync with the
18 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
19 def SIEncodingFamily {
27 //===----------------------------------------------------------------------===//
29 //===----------------------------------------------------------------------===//
31 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
32 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
33 [SDNPMayLoad, SDNPMemOperand]
36 def SIatomic_inc : SDNode<"AMDGPUISD::ATOMIC_INC", SDTAtomic2,
37 [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
40 def SIatomic_dec : SDNode<"AMDGPUISD::ATOMIC_DEC", SDTAtomic2,
41 [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
44 def SItbuffer_load : SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT",
47 SDTCisVT<1, v4i32>, // rsrc
48 SDTCisVT<2, i32>, // vindex(VGPR)
49 SDTCisVT<3, i32>, // voffset(VGPR)
50 SDTCisVT<4, i32>, // soffset(SGPR)
51 SDTCisVT<5, i32>, // offset(imm)
52 SDTCisVT<6, i32>, // dfmt(imm)
53 SDTCisVT<7, i32>, // nfmt(imm)
54 SDTCisVT<8, i32>, // glc(imm)
55 SDTCisVT<9, i32> // slc(imm)
57 [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
60 def SDTtbuffer_store : SDTypeProfile<0, 10,
62 SDTCisVT<1, v4i32>, // rsrc
63 SDTCisVT<2, i32>, // vindex(VGPR)
64 SDTCisVT<3, i32>, // voffset(VGPR)
65 SDTCisVT<4, i32>, // soffset(SGPR)
66 SDTCisVT<5, i32>, // offset(imm)
67 SDTCisVT<6, i32>, // dfmt(imm)
68 SDTCisVT<7, i32>, // nfmt(imm)
69 SDTCisVT<8, i32>, // glc(imm)
70 SDTCisVT<9, i32> // slc(imm)
73 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", SDTtbuffer_store,
74 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
75 def SItbuffer_store_x3 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_X3",
77 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
79 def SDTBufferLoad : SDTypeProfile<1, 5,
81 SDTCisVT<1, v4i32>, // rsrc
82 SDTCisVT<2, i32>, // vindex
83 SDTCisVT<3, i32>, // offset
84 SDTCisVT<4, i1>, // glc
85 SDTCisVT<5, i1>]>; // slc
87 def SIbuffer_load : SDNode <"AMDGPUISD::BUFFER_LOAD", SDTBufferLoad,
88 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
89 def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad,
90 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
92 class SDSample<string opcode> : SDNode <opcode,
93 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v8i32>,
94 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
97 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
98 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
99 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
100 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
102 def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET",
103 SDTypeProfile<1, 2, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>
106 //===----------------------------------------------------------------------===//
107 // PatFrags for global memory operations
108 //===----------------------------------------------------------------------===//
110 defm atomic_inc_global : global_binary_atomic_op<SIatomic_inc>;
111 defm atomic_dec_global : global_binary_atomic_op<SIatomic_dec>;
113 //===----------------------------------------------------------------------===//
114 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
115 // to be glued to the memory instructions.
116 //===----------------------------------------------------------------------===//
118 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
119 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
122 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
123 return cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUASI.LOCAL_ADDRESS;
126 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
127 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
128 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
131 def si_load_local_align8 : Aligned8Bytes <
132 (ops node:$ptr), (si_load_local node:$ptr)
135 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
136 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
138 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
140 multiclass SIExtLoadLocal <PatFrag ld_node> {
142 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
143 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
146 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
147 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
151 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
152 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
154 def SIst_local : SDNode <"ISD::STORE", SDTStore,
155 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
158 def si_st_local : PatFrag <
159 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
160 return cast<StoreSDNode>(N)->getAddressSpace() == AMDGPUASI.LOCAL_ADDRESS;
163 def si_store_local : PatFrag <
164 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
165 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
166 !cast<StoreSDNode>(N)->isTruncatingStore();
169 def si_store_local_align8 : Aligned8Bytes <
170 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
173 def si_truncstore_local : PatFrag <
174 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
175 return cast<StoreSDNode>(N)->isTruncatingStore();
178 def si_truncstore_local_i8 : PatFrag <
179 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
180 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
183 def si_truncstore_local_i16 : PatFrag <
184 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
185 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
188 def si_setcc_uniform : PatFrag <
189 (ops node:$lhs, node:$rhs, node:$cond),
190 (setcc node:$lhs, node:$rhs, node:$cond), [{
191 for (SDNode *Use : N->uses()) {
192 if (Use->isMachineOpcode() || Use->getOpcode() != ISD::CopyToReg)
195 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
196 if (Reg != AMDGPU::SCC)
202 def si_uniform_br : PatFrag <
203 (ops node:$cond, node:$bb), (brcond node:$cond, node:$bb), [{
204 return isUniformBr(N);
207 def si_uniform_br_scc : PatFrag <
208 (ops node:$cond, node:$bb), (si_uniform_br node:$cond, node:$bb), [{
209 return isCBranchSCC(N);
212 def lshr_rev : PatFrag <
213 (ops node:$src1, node:$src0),
217 def ashr_rev : PatFrag <
218 (ops node:$src1, node:$src0),
222 def lshl_rev : PatFrag <
223 (ops node:$src1, node:$src0),
227 multiclass SIAtomicM0Glue2 <string op_name, bit is_amdgpu = 0> {
230 !if(is_amdgpu, "AMDGPUISD", "ISD")#"::ATOMIC_"#op_name, SDTAtomic2,
231 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
234 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
237 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
238 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
239 defm si_atomic_inc : SIAtomicM0Glue2 <"INC", 1>;
240 defm si_atomic_dec : SIAtomicM0Glue2 <"DEC", 1>;
241 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
242 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
243 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
244 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
245 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
246 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
247 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
248 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
250 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
251 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
254 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
256 def as_i1imm : SDNodeXForm<imm, [{
257 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
260 def as_i8imm : SDNodeXForm<imm, [{
261 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
264 def as_i16imm : SDNodeXForm<imm, [{
265 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
268 def as_i32imm: SDNodeXForm<imm, [{
269 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
272 def as_i64imm: SDNodeXForm<imm, [{
273 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
276 // Copied from the AArch64 backend:
277 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
278 return CurDAG->getTargetConstant(
279 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
282 def frameindex_to_targetframeindex : SDNodeXForm<frameindex, [{
283 auto FI = cast<FrameIndexSDNode>(N);
284 return CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
287 // Copied from the AArch64 backend:
288 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
289 return CurDAG->getTargetConstant(
290 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
293 def SIMM16bit : PatLeaf <(imm),
294 [{return isInt<16>(N->getSExtValue());}]
297 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
298 return isInlineImmediate(N);
301 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
302 return isInlineImmediate(N);
305 class VGPRImm <dag frag> : PatLeaf<frag, [{
306 if (Subtarget->getGeneration() < SISubtarget::SOUTHERN_ISLANDS) {
309 const SIRegisterInfo *SIRI =
310 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
312 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
313 Limit < 10 && U != E; ++U, ++Limit) {
314 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
316 // If the register class is unknown, it could be an unknown
317 // register class that needs to be an SGPR, e.g. an inline asm
319 if (!RC || SIRI->isSGPRClass(RC))
326 def NegateImm : SDNodeXForm<imm, [{
327 return CurDAG->getConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
330 // TODO: When FP inline imm values work?
331 def NegSubInlineConst32 : ImmLeaf<i32, [{
332 return Imm < -16 && Imm >= -64;
335 def NegSubInlineConst16 : ImmLeaf<i16, [{
336 return Imm < -16 && Imm >= -64;
339 def ShiftAmt32Imm : PatLeaf <(imm), [{
340 return N->getZExtValue() < 32;
343 //===----------------------------------------------------------------------===//
345 //===----------------------------------------------------------------------===//
347 def SoppBrTarget : AsmOperandClass {
348 let Name = "SoppBrTarget";
349 let ParserMethod = "parseSOppBrTarget";
352 def sopp_brtarget : Operand<OtherVT> {
353 let EncoderMethod = "getSOPPBrEncoding";
354 let DecoderMethod = "decodeSoppBrTarget";
355 let OperandType = "OPERAND_PCREL";
356 let ParserMatchClass = SoppBrTarget;
359 def si_ga : Operand<iPTR>;
361 def InterpSlotMatchClass : AsmOperandClass {
362 let Name = "InterpSlot";
363 let PredicateMethod = "isInterpSlot";
364 let ParserMethod = "parseInterpSlot";
365 let RenderMethod = "addImmOperands";
368 def InterpSlot : Operand<i32> {
369 let PrintMethod = "printInterpSlot";
370 let ParserMatchClass = InterpSlotMatchClass;
371 let OperandType = "OPERAND_IMMEDIATE";
374 def AttrMatchClass : AsmOperandClass {
376 let PredicateMethod = "isInterpAttr";
377 let ParserMethod = "parseInterpAttr";
378 let RenderMethod = "addImmOperands";
381 // It appears to be necessary to create a separate operand for this to
382 // be able to parse attr<num> with no space.
383 def Attr : Operand<i32> {
384 let PrintMethod = "printInterpAttr";
385 let ParserMatchClass = AttrMatchClass;
386 let OperandType = "OPERAND_IMMEDIATE";
389 def AttrChanMatchClass : AsmOperandClass {
390 let Name = "AttrChan";
391 let PredicateMethod = "isAttrChan";
392 let RenderMethod = "addImmOperands";
395 def AttrChan : Operand<i32> {
396 let PrintMethod = "printInterpAttrChan";
397 let ParserMatchClass = AttrChanMatchClass;
398 let OperandType = "OPERAND_IMMEDIATE";
401 def SendMsgMatchClass : AsmOperandClass {
402 let Name = "SendMsg";
403 let PredicateMethod = "isSendMsg";
404 let ParserMethod = "parseSendMsgOp";
405 let RenderMethod = "addImmOperands";
408 def SwizzleMatchClass : AsmOperandClass {
409 let Name = "Swizzle";
410 let PredicateMethod = "isSwizzle";
411 let ParserMethod = "parseSwizzleOp";
412 let RenderMethod = "addImmOperands";
416 def ExpTgtMatchClass : AsmOperandClass {
418 let PredicateMethod = "isExpTgt";
419 let ParserMethod = "parseExpTgt";
420 let RenderMethod = "printExpTgt";
423 def SendMsgImm : Operand<i32> {
424 let PrintMethod = "printSendMsg";
425 let ParserMatchClass = SendMsgMatchClass;
428 def SwizzleImm : Operand<i16> {
429 let PrintMethod = "printSwizzle";
430 let ParserMatchClass = SwizzleMatchClass;
433 def SWaitMatchClass : AsmOperandClass {
434 let Name = "SWaitCnt";
435 let RenderMethod = "addImmOperands";
436 let ParserMethod = "parseSWaitCntOps";
439 def VReg32OrOffClass : AsmOperandClass {
440 let Name = "VReg32OrOff";
441 let ParserMethod = "parseVReg32OrOff";
444 def WAIT_FLAG : Operand <i32> {
445 let ParserMatchClass = SWaitMatchClass;
446 let PrintMethod = "printWaitFlag";
449 include "SIInstrFormats.td"
450 include "VIInstrFormats.td"
452 // ===----------------------------------------------------------------------===//
453 // ExpSrc* Special cases for exp src operands which are printed as
454 // "off" depending on en operand.
455 // ===----------------------------------------------------------------------===//
457 def ExpSrc0 : RegisterOperand<VGPR_32> {
458 let PrintMethod = "printExpSrc0";
459 let ParserMatchClass = VReg32OrOffClass;
462 def ExpSrc1 : RegisterOperand<VGPR_32> {
463 let PrintMethod = "printExpSrc1";
464 let ParserMatchClass = VReg32OrOffClass;
467 def ExpSrc2 : RegisterOperand<VGPR_32> {
468 let PrintMethod = "printExpSrc2";
469 let ParserMatchClass = VReg32OrOffClass;
472 def ExpSrc3 : RegisterOperand<VGPR_32> {
473 let PrintMethod = "printExpSrc3";
474 let ParserMatchClass = VReg32OrOffClass;
477 class SDWASrc : RegisterOperand<VS_32> {
478 let OperandNamespace = "AMDGPU";
479 let OperandType = "OPERAND_SDWA_SRC";
480 let EncoderMethod = "getSDWASrcEncoding";
483 def SDWASrc32 : SDWASrc {
484 let DecoderMethod = "decodeSDWASrc32";
487 def SDWASrc16 : SDWASrc {
488 let DecoderMethod = "decodeSDWASrc16";
491 def SDWAVopcDst : VOPDstOperand<SReg_64> {
492 let OperandNamespace = "AMDGPU";
493 let OperandType = "OPERAND_SDWA_VOPC_DST";
494 let EncoderMethod = "getSDWAVopcDstEncoding";
495 let DecoderMethod = "decodeSDWAVopcDst";
498 class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
499 let Name = "Imm"#CName;
500 let PredicateMethod = "is"#CName;
501 let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName);
502 let RenderMethod = "addImmOperands";
503 let IsOptional = Optional;
504 let DefaultMethod = !if(Optional, "default"#CName, ?);
507 class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> {
508 let PrintMethod = "print"#Name;
509 let ParserMatchClass = MatchClass;
512 class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> {
513 let PrintMethod = "print"#Name;
514 let ParserMatchClass = MatchClass;
517 class NamedOperandU12<string Name, AsmOperandClass MatchClass> : Operand<i16> {
518 let PrintMethod = "print"#Name;
519 let ParserMatchClass = MatchClass;
522 class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
523 let PrintMethod = "print"#Name;
524 let ParserMatchClass = MatchClass;
527 class NamedOperandS13<string Name, AsmOperandClass MatchClass> : Operand<i16> {
528 let PrintMethod = "print"#Name;
529 let ParserMatchClass = MatchClass;
532 class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
533 let PrintMethod = "print"#Name;
534 let ParserMatchClass = MatchClass;
537 class NamedOperandU32Default0<string Name, AsmOperandClass MatchClass> :
538 OperandWithDefaultOps<i32, (ops (i32 0))> {
539 let PrintMethod = "print"#Name;
540 let ParserMatchClass = MatchClass;
543 let OperandType = "OPERAND_IMMEDIATE" in {
545 def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>;
546 def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
547 def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
549 def offset_u12 : NamedOperandU12<"Offset", NamedMatchClass<"OffsetU12">>;
550 def offset_s13 : NamedOperandS13<"OffsetS13", NamedMatchClass<"OffsetS13">>;
551 def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
552 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
553 def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
555 def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
557 def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
558 def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
560 def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
561 def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
562 def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
563 def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
564 def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
565 def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
566 def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
567 def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
568 def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
570 def DFMT : NamedOperandU8<"DFMT", NamedMatchClass<"DFMT">>;
571 def NFMT : NamedOperandU8<"NFMT", NamedMatchClass<"NFMT">>;
573 def dmask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
575 def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
576 def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;
577 def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>;
578 def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>;
580 def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>;
581 def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>;
582 def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
583 def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
585 def op_sel : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
586 def op_sel_hi : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
587 def neg_lo : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
588 def neg_hi : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
590 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
592 def exp_tgt : NamedOperandU8<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
596 } // End OperandType = "OPERAND_IMMEDIATE"
598 class KImmMatchClass<int size> : AsmOperandClass {
599 let Name = "KImmFP"#size;
600 let PredicateMethod = "isKImmFP"#size;
601 let ParserMethod = "parseImm";
602 let RenderMethod = "addKImmFP"#size#"Operands";
605 class kimmOperand<ValueType vt> : Operand<vt> {
606 let OperandNamespace = "AMDGPU";
607 let OperandType = "OPERAND_KIMM"#vt.Size;
608 let PrintMethod = "printU"#vt.Size#"ImmOperand";
609 let ParserMatchClass = !cast<AsmOperandClass>("KImmFP"#vt.Size#"MatchClass");
612 // 32-bit VALU immediate operand that uses the constant bus.
613 def KImmFP32MatchClass : KImmMatchClass<32>;
614 def f32kimm : kimmOperand<i32>;
616 // 32-bit VALU immediate operand with a 16-bit value that uses the
618 def KImmFP16MatchClass : KImmMatchClass<16>;
619 def f16kimm : kimmOperand<i16>;
622 def VOPDstS64 : VOPDstOperand <SReg_64>;
624 class FPInputModsMatchClass <int opSize> : AsmOperandClass {
625 let Name = "RegOrImmWithFP"#opSize#"InputMods";
626 let ParserMethod = "parseRegOrImmWithFPInputMods";
627 let PredicateMethod = "isRegOrImmWithFP"#opSize#"InputMods";
630 def FP16InputModsMatchClass : FPInputModsMatchClass<16>;
631 def FP32InputModsMatchClass : FPInputModsMatchClass<32>;
632 def FP64InputModsMatchClass : FPInputModsMatchClass<64>;
634 class InputMods <AsmOperandClass matchClass> : Operand <i32> {
635 let OperandNamespace = "AMDGPU";
636 let OperandType = "OPERAND_INPUT_MODS";
637 let ParserMatchClass = matchClass;
640 class FPInputMods <FPInputModsMatchClass matchClass> : InputMods <matchClass> {
641 let PrintMethod = "printOperandAndFPInputMods";
644 def FP16InputMods : FPInputMods<FP16InputModsMatchClass>;
645 def FP32InputMods : FPInputMods<FP32InputModsMatchClass>;
646 def FP64InputMods : FPInputMods<FP64InputModsMatchClass>;
648 class IntInputModsMatchClass <int opSize> : AsmOperandClass {
649 let Name = "RegOrImmWithInt"#opSize#"InputMods";
650 let ParserMethod = "parseRegOrImmWithIntInputMods";
651 let PredicateMethod = "isRegOrImmWithInt"#opSize#"InputMods";
653 def Int32InputModsMatchClass : IntInputModsMatchClass<32>;
654 def Int64InputModsMatchClass : IntInputModsMatchClass<64>;
656 class IntInputMods <IntInputModsMatchClass matchClass> : InputMods <matchClass> {
657 let PrintMethod = "printOperandAndIntInputMods";
659 def Int32InputMods : IntInputMods<Int32InputModsMatchClass>;
660 def Int64InputMods : IntInputMods<Int64InputModsMatchClass>;
662 def FPRegSDWAInputModsMatchClass : AsmOperandClass {
663 let Name = "SDWARegWithFPInputMods";
664 let ParserMethod = "parseRegWithFPInputMods";
665 let PredicateMethod = "isSDWARegKind";
668 def FPRegSDWAInputMods : InputMods <FPRegSDWAInputModsMatchClass> {
669 let PrintMethod = "printOperandAndFPInputMods";
672 def FPVRegInputModsMatchClass : AsmOperandClass {
673 let Name = "VRegWithFPInputMods";
674 let ParserMethod = "parseRegWithFPInputMods";
675 let PredicateMethod = "isVReg";
678 def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
679 let PrintMethod = "printOperandAndFPInputMods";
683 def IntRegSDWAInputModsMatchClass : AsmOperandClass {
684 let Name = "SDWARegWithIntInputMods";
685 let ParserMethod = "parseRegWithIntInputMods";
686 let PredicateMethod = "isSDWARegKind";
689 def IntRegSDWAInputMods : InputMods <IntRegSDWAInputModsMatchClass> {
690 let PrintMethod = "printOperandAndIntInputMods";
693 def IntVRegInputModsMatchClass : AsmOperandClass {
694 let Name = "VRegWithIntInputMods";
695 let ParserMethod = "parseRegWithIntInputMods";
696 let PredicateMethod = "isVReg";
699 def IntVRegInputMods : InputMods <IntVRegInputModsMatchClass> {
700 let PrintMethod = "printOperandAndIntInputMods";
703 class PackedFPInputModsMatchClass <int opSize> : AsmOperandClass {
704 let Name = "PackedFP"#opSize#"InputMods";
705 let ParserMethod = "parseRegOrImm";
706 let PredicateMethod = "isRegOrImm";
707 // let PredicateMethod = "isPackedFP"#opSize#"InputMods";
710 class PackedIntInputModsMatchClass <int opSize> : AsmOperandClass {
711 let Name = "PackedInt"#opSize#"InputMods";
712 let ParserMethod = "parseRegOrImm";
713 let PredicateMethod = "isRegOrImm";
714 // let PredicateMethod = "isPackedInt"#opSize#"InputMods";
717 def PackedF16InputModsMatchClass : PackedFPInputModsMatchClass<16>;
718 def PackedI16InputModsMatchClass : PackedIntInputModsMatchClass<16>;
720 class PackedFPInputMods <PackedFPInputModsMatchClass matchClass> : InputMods <matchClass> {
721 // let PrintMethod = "printPackedFPInputMods";
724 class PackedIntInputMods <PackedIntInputModsMatchClass matchClass> : InputMods <matchClass> {
725 //let PrintMethod = "printPackedIntInputMods";
728 def PackedF16InputMods : PackedFPInputMods<PackedF16InputModsMatchClass>;
729 def PackedI16InputMods : PackedIntInputMods<PackedI16InputModsMatchClass>;
731 //===----------------------------------------------------------------------===//
733 //===----------------------------------------------------------------------===//
735 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
736 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
738 def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
740 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
741 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
742 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
743 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
744 def VOP3NoMods : ComplexPattern<untyped, 1, "SelectVOP3NoMods">;
745 // VOP3Mods, but the input source is known to never be NaN.
746 def VOP3Mods_nnan : ComplexPattern<fAny, 2, "SelectVOP3Mods_NNaN">;
748 def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
750 def VOP3PMods : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
751 def VOP3PMods0 : ComplexPattern<untyped, 3, "SelectVOP3PMods0">;
754 //===----------------------------------------------------------------------===//
755 // SI assembler operands
756 //===----------------------------------------------------------------------===//
764 // This should be kept in sync with SISrcMods enum
787 int LLVM_DEBUG_TRAP = 3;
790 //===----------------------------------------------------------------------===//
792 // SI Instruction multiclass helpers.
794 // Instructions with _32 take 32-bit operands.
795 // Instructions with _64 take 64-bit operands.
797 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
798 // encoding is the standard encoding, but instruction that make use of
799 // any of the instruction modifiers must use the 64-bit encoding.
801 // Instructions with _e32 use the 32-bit encoding.
802 // Instructions with _e64 use the 64-bit encoding.
804 //===----------------------------------------------------------------------===//
806 class SIMCInstr <string pseudo, int subtarget> {
807 string PseudoInstr = pseudo;
808 int Subtarget = subtarget;
811 //===----------------------------------------------------------------------===//
813 //===----------------------------------------------------------------------===//
815 class EXP_Helper<bit done, SDPatternOperator node = null_frag> : EXPCommon<
818 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
819 exp_vm:$vm, exp_compr:$compr, i8imm:$en),
820 "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm",
821 [(node (i8 timm:$tgt), (i8 timm:$en),
822 f32:$src0, f32:$src1, f32:$src2, f32:$src3,
823 (i1 timm:$compr), (i1 timm:$vm))]> {
824 let AsmMatchConverter = "cvtExp";
827 // Split EXP instruction into EXP and EXP_DONE so we can set
828 // mayLoad for done=1.
829 multiclass EXP_m<bit done, SDPatternOperator node> {
830 let mayLoad = done in {
831 let isPseudo = 1, isCodeGenOnly = 1 in {
832 def "" : EXP_Helper<done, node>,
833 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.NONE>;
837 def _si : EXP_Helper<done>,
838 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>,
840 let AssemblerPredicates = [isSICI];
841 let DecoderNamespace = "SICI";
842 let DisableDecoder = DisableSIDecoder;
845 def _vi : EXP_Helper<done>,
846 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
848 let AssemblerPredicates = [isVI];
849 let DecoderNamespace = "VI";
850 let DisableDecoder = DisableVIDecoder;
856 //===----------------------------------------------------------------------===//
857 // Vector ALU classes
858 //===----------------------------------------------------------------------===//
860 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
862 !if (!eq(Src0.Value, untyped.Value), 0,
863 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
864 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
868 // Returns the register class to use for the destination of VOP[123C]
869 // instructions for the given VT.
870 class getVALUDstForVT<ValueType VT> {
871 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
872 !if(!eq(VT.Size, 128), VOPDstOperand<VReg_128>,
873 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
874 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
875 VOPDstOperand<SReg_64>)))); // else VT == i1
878 // Returns the register class to use for the destination of VOP[12C]
879 // instructions with SDWA extension
880 class getSDWADstForVT<ValueType VT> {
881 RegisterOperand ret = !if(!eq(VT.Size, 1),
883 VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst
886 // Returns the register class to use for source 0 of VOP[12C]
887 // instructions for the given VT.
888 class getVOPSrc0ForVT<ValueType VT> {
889 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
890 !if(!eq(VT.Value, v2f16.Value), 1,
891 !if(!eq(VT.Value, f32.Value), 1,
892 !if(!eq(VT.Value, f64.Value), 1,
895 RegisterOperand ret =
897 !if(!eq(VT.Size, 64),
899 !if(!eq(VT.Value, f16.Value),
901 !if(!eq(VT.Value, v2f16.Value),
907 !if(!eq(VT.Size, 64),
909 !if(!eq(VT.Value, i16.Value),
911 !if(!eq(VT.Value, v2i16.Value),
920 // Returns the vreg register class to use for source operand given VT
921 class getVregSrcForVT<ValueType VT> {
922 RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128,
923 !if(!eq(VT.Size, 64), VReg_64, VGPR_32));
926 class getSDWASrcForVT <ValueType VT> {
927 RegisterOperand ret = !if(!eq(VT.Size, 16), SDWASrc16, SDWASrc32);
930 // Returns the register class to use for sources of VOP3 instructions for the
932 class getVOP3SrcForVT<ValueType VT> {
933 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
934 !if(!eq(VT.Value, v2f16.Value), 1,
935 !if(!eq(VT.Value, f32.Value), 1,
936 !if(!eq(VT.Value, f64.Value), 1,
938 RegisterOperand ret =
939 !if(!eq(VT.Size, 128),
941 !if(!eq(VT.Size, 64),
945 !if(!eq(VT.Value, i1.Value),
948 !if(!eq(VT.Value, f16.Value),
950 !if(!eq(VT.Value, v2f16.Value),
955 !if(!eq(VT.Value, i16.Value),
957 !if(!eq(VT.Value, v2i16.Value),
968 // Returns 1 if the source arguments have modifiers, 0 if they do not.
969 // XXX - do f16 instructions?
970 class isFloatType<ValueType SrcVT> {
972 !if(!eq(SrcVT.Value, f16.Value), 1,
973 !if(!eq(SrcVT.Value, f32.Value), 1,
974 !if(!eq(SrcVT.Value, f64.Value), 1,
975 !if(!eq(SrcVT.Value, v2f16.Value), 1,
979 class isIntType<ValueType SrcVT> {
981 !if(!eq(SrcVT.Value, i16.Value), 1,
982 !if(!eq(SrcVT.Value, i32.Value), 1,
983 !if(!eq(SrcVT.Value, i64.Value), 1,
987 class isPackedType<ValueType SrcVT> {
989 !if(!eq(SrcVT.Value, v2i16.Value), 1,
990 !if(!eq(SrcVT.Value, v2f16.Value), 1, 0)
994 // Float or packed int
995 class isModifierType<ValueType SrcVT> {
997 !if(!eq(SrcVT.Value, f16.Value), 1,
998 !if(!eq(SrcVT.Value, f32.Value), 1,
999 !if(!eq(SrcVT.Value, f64.Value), 1,
1000 !if(!eq(SrcVT.Value, v2f16.Value), 1,
1001 !if(!eq(SrcVT.Value, v2i16.Value), 1,
1005 // Return type of input modifiers operand for specified input operand
1006 class getSrcMod <ValueType VT> {
1007 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
1008 !if(!eq(VT.Value, f32.Value), 1,
1009 !if(!eq(VT.Value, f64.Value), 1,
1011 bit isPacked = isPackedType<VT>.ret;
1012 Operand ret = !if(!eq(VT.Size, 64),
1013 !if(isFP, FP64InputMods, Int64InputMods),
1015 !if(!eq(VT.Value, f16.Value),
1023 // Return type of input modifiers operand specified input operand for DPP
1024 class getSrcModExt <ValueType VT> {
1025 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
1026 !if(!eq(VT.Value, f32.Value), 1,
1027 !if(!eq(VT.Value, f64.Value), 1,
1029 Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
1032 // Return type of input modifiers operand specified input operand for SDWA
1033 class getSrcModSDWA <ValueType VT> {
1034 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
1035 !if(!eq(VT.Value, f32.Value), 1,
1036 !if(!eq(VT.Value, f64.Value), 1,
1038 Operand ret = !if(isFP, FPRegSDWAInputMods, IntRegSDWAInputMods);
1041 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
1042 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1043 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1044 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1048 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1049 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1050 RegisterOperand Src2RC, int NumSrcArgs,
1051 bit HasModifiers, bit HasOMod,
1052 Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1055 !if (!eq(NumSrcArgs, 0),
1056 // VOP1 without input operands (V_NOP, V_CLREXCP)
1059 !if (!eq(NumSrcArgs, 1),
1060 !if (!eq(HasModifiers, 1),
1061 // VOP1 with modifiers
1062 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1063 clampmod:$clamp, omod:$omod)
1065 // VOP1 without modifiers
1068 !if (!eq(NumSrcArgs, 2),
1069 !if (!eq(HasModifiers, 1),
1070 // VOP 2 with modifiers
1071 !if( !eq(HasOMod, 1),
1072 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1073 Src1Mod:$src1_modifiers, Src1RC:$src1,
1074 clampmod:$clamp, omod:$omod),
1075 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1076 Src1Mod:$src1_modifiers, Src1RC:$src1,
1079 // VOP2 without modifiers
1080 (ins Src0RC:$src0, Src1RC:$src1)
1082 /* NumSrcArgs == 3 */,
1083 !if (!eq(HasModifiers, 1),
1084 // VOP3 with modifiers
1085 !if (!eq(HasOMod, 1),
1086 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1087 Src1Mod:$src1_modifiers, Src1RC:$src1,
1088 Src2Mod:$src2_modifiers, Src2RC:$src2,
1089 clampmod:$clamp, omod:$omod),
1090 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1091 Src1Mod:$src1_modifiers, Src1RC:$src1,
1092 Src2Mod:$src2_modifiers, Src2RC:$src2,
1095 // VOP3 without modifiers
1096 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
1100 /// XXX - src1 may only allow VGPRs?
1102 // The modifiers (except clamp) are dummy operands for the benefit of
1103 // printing and parsing. They defer their values to looking at the
1104 // srcN_modifiers for what to print.
1105 class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC,
1106 RegisterOperand Src2RC, int NumSrcArgs,
1108 Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1109 dag ret = !if (!eq(NumSrcArgs, 2),
1111 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1112 Src1Mod:$src1_modifiers, Src1RC:$src1,
1114 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1115 neg_lo:$neg_lo, neg_hi:$neg_hi),
1116 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1117 Src1Mod:$src1_modifiers, Src1RC:$src1,
1118 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1119 neg_lo:$neg_lo, neg_hi:$neg_hi)),
1120 // else NumSrcArgs == 3
1122 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1123 Src1Mod:$src1_modifiers, Src1RC:$src1,
1124 Src2Mod:$src2_modifiers, Src2RC:$src2,
1126 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1127 neg_lo:$neg_lo, neg_hi:$neg_hi),
1128 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1129 Src1Mod:$src1_modifiers, Src1RC:$src1,
1130 Src2Mod:$src2_modifiers, Src2RC:$src2,
1131 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1132 neg_lo:$neg_lo, neg_hi:$neg_hi))
1136 class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
1137 bit HasModifiers, Operand Src0Mod, Operand Src1Mod> {
1139 dag ret = !if (!eq(NumSrcArgs, 0),
1140 // VOP1 without input operands (V_NOP)
1141 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1142 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl),
1143 !if (!eq(NumSrcArgs, 1),
1144 !if (!eq(HasModifiers, 1),
1145 // VOP1_DPP with modifiers
1146 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1147 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1148 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1150 // VOP1_DPP without modifiers
1151 (ins Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1152 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1154 /* NumSrcArgs == 2 */,
1155 !if (!eq(HasModifiers, 1),
1156 // VOP2_DPP with modifiers
1157 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1158 Src1Mod:$src1_modifiers, Src1RC:$src1,
1159 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1160 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1162 // VOP2_DPP without modifiers
1163 (ins Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
1164 row_mask:$row_mask, bank_mask:$bank_mask,
1165 bound_ctrl:$bound_ctrl)
1172 class getInsSDWA <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs,
1173 bit HasSDWAOMod, Operand Src0Mod, Operand Src1Mod,
1176 dag ret = !if(!eq(NumSrcArgs, 0),
1177 // VOP1 without input operands (V_NOP)
1179 !if(!eq(NumSrcArgs, 1),
1181 !if(!eq(HasSDWAOMod, 0),
1182 // VOP1_SDWA without omod
1183 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1185 dst_sel:$dst_sel, dst_unused:$dst_unused,
1186 src0_sel:$src0_sel),
1187 // VOP1_SDWA with omod
1188 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1189 clampmod:$clamp, omod:$omod,
1190 dst_sel:$dst_sel, dst_unused:$dst_unused,
1191 src0_sel:$src0_sel)),
1192 !if(!eq(NumSrcArgs, 2),
1193 !if(!eq(DstVT.Size, 1),
1195 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1196 Src1Mod:$src1_modifiers, Src1RC:$src1,
1197 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1199 !if(!eq(HasSDWAOMod, 0),
1200 // VOP2_SDWA without omod
1201 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1202 Src1Mod:$src1_modifiers, Src1RC:$src1,
1204 dst_sel:$dst_sel, dst_unused:$dst_unused,
1205 src0_sel:$src0_sel, src1_sel:$src1_sel),
1206 // VOP2_SDWA with omod
1207 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1208 Src1Mod:$src1_modifiers, Src1RC:$src1,
1209 clampmod:$clamp, omod:$omod,
1210 dst_sel:$dst_sel, dst_unused:$dst_unused,
1211 src0_sel:$src0_sel, src1_sel:$src1_sel))),
1212 (ins)/* endif */)));
1215 // Outs for DPP and SDWA
1216 class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCExt> {
1217 dag ret = !if(HasDst,
1218 !if(!eq(DstVT.Size, 1),
1219 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1220 (outs DstRCExt:$vdst)),
1225 class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
1226 dag ret = !if(HasDst,
1227 !if(!eq(DstVT.Size, 1),
1228 (outs DstRCSDWA:$sdst),
1229 (outs DstRCSDWA:$vdst)),
1233 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1234 // instruction. This does not add the _e32 suffix, so it can be reused
1236 class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1237 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1238 string src0 = ", $src0";
1239 string src1 = ", $src1";
1240 string src2 = ", $src2";
1241 string ret = !if(HasDst, dst, "") #
1242 !if(!eq(NumSrcArgs, 1), src0, "") #
1243 !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1244 !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
1247 // Returns the assembly string for the inputs and outputs of a VOP3
1249 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers,
1250 bit HasOMod, ValueType DstVT = i32> {
1251 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1252 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1253 string src1 = !if(!eq(NumSrcArgs, 1), "",
1254 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1255 " $src1_modifiers,"));
1256 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1258 !if(!eq(HasModifiers, 0),
1259 getAsm32<HasDst, NumSrcArgs, DstVT>.ret,
1260 dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", ""));
1263 // Returns the assembly string for the inputs and outputs of a VOP3P
1265 class getAsmVOP3P <bit HasDst, int NumSrcArgs, bit HasModifiers,
1266 bit HasClamp, ValueType DstVT = i32> {
1267 string dst = " $vdst";
1268 string src0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1269 string src1 = !if(!eq(NumSrcArgs, 1), "",
1270 !if(!eq(NumSrcArgs, 2), " $src1",
1272 string src2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1274 string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
1275 string clamp = !if(HasClamp, "$clamp", "");
1277 // Each modifier is printed as an array of bits for each operand, so
1278 // all operands are printed as part of src0_modifiers.
1279 string ret = dst#", "#src0#src1#src2#"$op_sel$op_sel_hi"#mods#clamp;
1282 class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
1283 string dst = !if(HasDst,
1284 !if(!eq(DstVT.Size, 1),
1287 ""); // use $sdst for VOPC
1288 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1289 string src1 = !if(!eq(NumSrcArgs, 1), "",
1290 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1291 " $src1_modifiers,"));
1292 string args = !if(!eq(HasModifiers, 0),
1293 getAsm32<0, NumSrcArgs, DstVT>.ret,
1295 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
1298 class getAsmSDWA <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1299 string dst = !if(HasDst,
1300 !if(!eq(DstVT.Size, 1),
1301 " vcc", // use vcc token as dst for VOPC instructioins
1304 string src0 = "$src0_modifiers";
1305 string src1 = "$src1_modifiers";
1306 string args = !if(!eq(NumSrcArgs, 0),
1308 !if(!eq(NumSrcArgs, 1),
1310 ", "#src0#", "#src1#"$clamp"
1313 string sdwa = !if(!eq(NumSrcArgs, 0),
1315 !if(!eq(NumSrcArgs, 1),
1316 " $dst_sel $dst_unused $src0_sel",
1317 !if(!eq(DstVT.Size, 1),
1318 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1319 " $dst_sel $dst_unused $src0_sel $src1_sel"
1323 string ret = dst#args#sdwa;
1326 class getAsmSDWA9 <bit HasDst, bit HasOMod, int NumSrcArgs,
1327 ValueType DstVT = i32> {
1328 string dst = !if(HasDst,
1329 !if(!eq(DstVT.Size, 1),
1333 string src0 = "$src0_modifiers";
1334 string src1 = "$src1_modifiers";
1335 string out_mods = !if(!eq(HasOMod, 0), "$clamp", "$clamp$omod");
1336 string args = !if(!eq(NumSrcArgs, 0), "",
1337 !if(!eq(NumSrcArgs, 1),
1342 string sdwa = !if(!eq(NumSrcArgs, 0), "",
1343 !if(!eq(NumSrcArgs, 1),
1344 out_mods#" $dst_sel $dst_unused $src0_sel",
1345 !if(!eq(DstVT.Size, 1),
1346 " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
1347 out_mods#" $dst_sel $dst_unused $src0_sel $src1_sel"
1351 string ret = dst#args#sdwa;
1355 // Function that checks if instruction supports DPP and SDWA
1356 class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
1357 ValueType Src1VT = i32> {
1358 bit ret = !if(!eq(NumSrcArgs, 3),
1359 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
1360 !if(!eq(DstVT.Size, 64),
1361 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
1362 !if(!eq(Src0VT.Size, 64),
1364 !if(!eq(Src0VT.Size, 64),
1373 class BitOr<bit a, bit b> {
1374 bit ret = !if(a, 1, !if(b, 1, 0));
1377 class BitAnd<bit a, bit b> {
1378 bit ret = !if(a, !if(b, 1, 0), 0);
1381 class VOPProfile <list<ValueType> _ArgVT> {
1383 field list<ValueType> ArgVT = _ArgVT;
1385 field ValueType DstVT = ArgVT[0];
1386 field ValueType Src0VT = ArgVT[1];
1387 field ValueType Src1VT = ArgVT[2];
1388 field ValueType Src2VT = ArgVT[3];
1389 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1390 field RegisterOperand DstRCDPP = getVALUDstForVT<DstVT>.ret;
1391 field RegisterOperand DstRCSDWA = getSDWADstForVT<DstVT>.ret;
1392 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1393 field RegisterClass Src1RC32 = getVregSrcForVT<Src1VT>.ret;
1394 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1395 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1396 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1397 field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
1398 field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
1399 field RegisterOperand Src0SDWA = getSDWASrcForVT<Src0VT>.ret;
1400 field RegisterOperand Src1SDWA = getSDWASrcForVT<Src0VT>.ret;
1401 field Operand Src0Mod = getSrcMod<Src0VT>.ret;
1402 field Operand Src1Mod = getSrcMod<Src1VT>.ret;
1403 field Operand Src2Mod = getSrcMod<Src2VT>.ret;
1404 field Operand Src0ModDPP = getSrcModExt<Src0VT>.ret;
1405 field Operand Src1ModDPP = getSrcModExt<Src1VT>.ret;
1406 field Operand Src0ModSDWA = getSrcModSDWA<Src0VT>.ret;
1407 field Operand Src1ModSDWA = getSrcModSDWA<Src1VT>.ret;
1410 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
1411 field bit HasDst32 = HasDst;
1412 field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
1413 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1414 field bit HasSrc0 = !if(!eq(Src0VT.Value, untyped.Value), 0, 1);
1415 field bit HasSrc1 = !if(!eq(Src1VT.Value, untyped.Value), 0, 1);
1416 field bit HasSrc2 = !if(!eq(Src2VT.Value, untyped.Value), 0, 1);
1418 // TODO: Modifiers logic is somewhat adhoc here, to be refined later
1419 field bit HasModifiers = isModifierType<Src0VT>.ret;
1421 field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
1422 field bit HasSrc1FloatMods = isFloatType<Src1VT>.ret;
1423 field bit HasSrc2FloatMods = isFloatType<Src2VT>.ret;
1425 field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
1426 field bit HasSrc1IntMods = isIntType<Src1VT>.ret;
1427 field bit HasSrc2IntMods = isIntType<Src2VT>.ret;
1429 field bit HasSrc0Mods = HasModifiers;
1430 field bit HasSrc1Mods = !if(HasModifiers, BitOr<HasSrc1FloatMods, HasSrc1IntMods>.ret, 0);
1431 field bit HasSrc2Mods = !if(HasModifiers, BitOr<HasSrc2FloatMods, HasSrc2IntMods>.ret, 0);
1433 field bit HasClamp = HasModifiers;
1434 field bit HasSDWAClamp = EmitDst;
1435 field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
1437 field bit IsPacked = isPackedType<Src0VT>.ret;
1438 field bit HasOpSel = IsPacked;
1439 field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);
1440 field bit HasSDWAOMod = isFloatType<DstVT>.ret;
1442 field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
1443 field bit HasSDWA9 = HasExt;
1445 field Operand Src0PackedMod = !if(HasSrc0FloatMods, PackedF16InputMods, PackedI16InputMods);
1446 field Operand Src1PackedMod = !if(HasSrc1FloatMods, PackedF16InputMods, PackedI16InputMods);
1447 field Operand Src2PackedMod = !if(HasSrc2FloatMods, PackedF16InputMods, PackedI16InputMods);
1449 field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
1451 // VOP3b instructions are a special case with a second explicit
1452 // output. This is manually overridden for them.
1453 field dag Outs32 = Outs;
1454 field dag Outs64 = Outs;
1455 field dag OutsDPP = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
1456 field dag OutsSDWA = getOutsSDWA<HasDst, DstVT, DstRCSDWA>.ret;
1458 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1459 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1460 HasModifiers, HasOMod, Src0Mod, Src1Mod,
1462 field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64,
1463 NumSrcArgs, HasClamp,
1464 Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
1466 field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs,
1467 HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
1468 field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs,
1469 HasSDWAOMod, Src0ModSDWA, Src1ModSDWA,
1473 field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
1474 field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, HasOMod, DstVT>.ret;
1475 field string AsmVOP3P = getAsmVOP3P<HasDst, NumSrcArgs, HasModifiers, HasClamp, DstVT>.ret;
1476 field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
1477 field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;
1478 field string AsmSDWA9 = getAsmSDWA9<HasDst, HasSDWAOMod, NumSrcArgs, DstVT>.ret;
1481 class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
1486 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
1487 def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
1488 def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
1490 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
1491 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
1492 def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
1493 def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
1495 def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
1496 def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
1498 def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
1499 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
1500 def VOP_B32_F16_F16 : VOPProfile <[i32, f16, f16, untyped]>;
1502 def VOP_V2F16_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, v2f16]>;
1503 def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>;
1505 def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
1507 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
1509 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1510 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1511 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1512 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1513 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1514 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1515 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1516 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1517 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1518 def VOP_F16_F32 : VOPProfile <[f16, f32, untyped, untyped]>;
1519 def VOP_F32_F16 : VOPProfile <[f32, f16, untyped, untyped]>;
1521 def VOP_F32_F32_F16 : VOPProfile <[f32, f32, f16, untyped]>;
1522 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1523 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1524 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1525 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1526 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1527 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1528 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1529 def VOP_V2F16_F32_F32 : VOPProfile <[v2f16, f32, f32, untyped]>;
1531 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1532 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1533 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1535 def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
1536 def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
1537 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1538 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1539 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1540 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1541 def VOP_I32_F32_I32_I32 : VOPProfile <[i32, f32, i32, i32]>;
1542 def VOP_I64_I64_I32_I64 : VOPProfile <[i64, i64, i32, i64]>;
1543 def VOP_V4I32_I64_I32_V4I32 : VOPProfile <[v4i32, i64, i32, v4i32]>;
1545 class Commutable_REV <string revOp, bit isOrig> {
1546 string RevOp = revOp;
1547 bit IsOrig = isOrig;
1550 class AtomicNoRet <string noRetOp, bit isRet> {
1551 string NoRetOp = noRetOp;
1555 //===----------------------------------------------------------------------===//
1556 // Interpolation opcodes
1557 //===----------------------------------------------------------------------===//
1559 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1560 VINTRPCommon <outs, ins, "", pattern>,
1561 SIMCInstr<opName, SIEncodingFamily.NONE> {
1563 let isCodeGenOnly = 1;
1566 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1568 VINTRPCommon <outs, ins, asm, []>,
1570 SIMCInstr<opName, SIEncodingFamily.SI> {
1571 let AssemblerPredicate = SIAssemblerPredicate;
1572 let DecoderNamespace = "SICI";
1573 let DisableDecoder = DisableSIDecoder;
1576 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1578 VINTRPCommon <outs, ins, asm, []>,
1580 SIMCInstr<opName, SIEncodingFamily.VI> {
1581 let AssemblerPredicate = VIAssemblerPredicate;
1582 let DecoderNamespace = "VI";
1583 let DisableDecoder = DisableVIDecoder;
1586 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1587 list<dag> pattern = []> {
1588 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1590 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1592 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1595 //===----------------------------------------------------------------------===//
1596 // Vector instruction mappings
1597 //===----------------------------------------------------------------------===//
1599 // Maps an opcode in e32 form to its e64 equivalent
1600 def getVOPe64 : InstrMapping {
1601 let FilterClass = "VOP";
1602 let RowFields = ["OpName"];
1603 let ColFields = ["Size", "VOP3"];
1604 let KeyCol = ["4", "0"];
1605 let ValueCols = [["8", "1"]];
1608 // Maps an opcode in e64 form to its e32 equivalent
1609 def getVOPe32 : InstrMapping {
1610 let FilterClass = "VOP";
1611 let RowFields = ["OpName"];
1612 let ColFields = ["Size", "VOP3"];
1613 let KeyCol = ["8", "1"];
1614 let ValueCols = [["4", "0"]];
1617 // Maps ordinary instructions to their SDWA counterparts
1618 def getSDWAOp : InstrMapping {
1619 let FilterClass = "VOP";
1620 let RowFields = ["OpName"];
1621 let ColFields = ["AsmVariantName"];
1622 let KeyCol = ["Default"];
1623 let ValueCols = [["SDWA"]];
1626 // Maps SDWA instructions to their ordinary counterparts
1627 def getBasicFromSDWAOp : InstrMapping {
1628 let FilterClass = "VOP";
1629 let RowFields = ["OpName"];
1630 let ColFields = ["AsmVariantName"];
1631 let KeyCol = ["SDWA"];
1632 let ValueCols = [["Default"]];
1635 def getMaskedMIMGOp : InstrMapping {
1636 let FilterClass = "MIMG_Mask";
1637 let RowFields = ["Op"];
1638 let ColFields = ["Channels"];
1640 let ValueCols = [["1"], ["2"], ["3"] ];
1643 // Maps an commuted opcode to its original version
1644 def getCommuteOrig : InstrMapping {
1645 let FilterClass = "Commutable_REV";
1646 let RowFields = ["RevOp"];
1647 let ColFields = ["IsOrig"];
1649 let ValueCols = [["1"]];
1652 // Maps an original opcode to its commuted version
1653 def getCommuteRev : InstrMapping {
1654 let FilterClass = "Commutable_REV";
1655 let RowFields = ["RevOp"];
1656 let ColFields = ["IsOrig"];
1658 let ValueCols = [["0"]];
1661 def getMCOpcodeGen : InstrMapping {
1662 let FilterClass = "SIMCInstr";
1663 let RowFields = ["PseudoInstr"];
1664 let ColFields = ["Subtarget"];
1665 let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
1666 let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
1667 [!cast<string>(SIEncodingFamily.VI)],
1668 [!cast<string>(SIEncodingFamily.SDWA)],
1669 [!cast<string>(SIEncodingFamily.SDWA9)]];
1672 // Get equivalent SOPK instruction.
1673 def getSOPKOp : InstrMapping {
1674 let FilterClass = "SOPKInstTable";
1675 let RowFields = ["BaseCmpOp"];
1676 let ColFields = ["IsSOPK"];
1678 let ValueCols = [["1"]];
1681 def getAddr64Inst : InstrMapping {
1682 let FilterClass = "MUBUFAddr64Table";
1683 let RowFields = ["OpName"];
1684 let ColFields = ["IsAddr64"];
1686 let ValueCols = [["1"]];
1689 // Maps an atomic opcode to its version with a return value.
1690 def getAtomicRetOp : InstrMapping {
1691 let FilterClass = "AtomicNoRet";
1692 let RowFields = ["NoRetOp"];
1693 let ColFields = ["IsRet"];
1695 let ValueCols = [["1"]];
1698 // Maps an atomic opcode to its returnless version.
1699 def getAtomicNoRetOp : InstrMapping {
1700 let FilterClass = "AtomicNoRet";
1701 let RowFields = ["NoRetOp"];
1702 let ColFields = ["IsRet"];
1704 let ValueCols = [["0"]];
1707 include "SIInstructions.td"
1708 include "CIInstructions.td"
1710 include "DSInstructions.td"
1711 include "MIMGInstructions.td"