1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= SISubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "SISubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
15 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
17 // Execpt for the NONE field, this must be kept in sync with the
18 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
19 def SIEncodingFamily {
25 //===----------------------------------------------------------------------===//
27 //===----------------------------------------------------------------------===//
29 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
30 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
31 [SDNPMayLoad, SDNPMemOperand]
34 def SIatomic_inc : SDNode<"AMDGPUISD::ATOMIC_INC", SDTAtomic2,
35 [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
38 def SIatomic_dec : SDNode<"AMDGPUISD::ATOMIC_DEC", SDTAtomic2,
39 [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
42 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT",
44 [SDTCisVT<0, v4i32>, // rsrc(SGPR)
45 SDTCisVT<1, iAny>, // vdata(VGPR)
46 SDTCisVT<2, i32>, // num_channels(imm)
47 SDTCisVT<3, i32>, // vaddr(VGPR)
48 SDTCisVT<4, i32>, // soffset(SGPR)
49 SDTCisVT<5, i32>, // inst_offset(imm)
50 SDTCisVT<6, i32>, // dfmt(imm)
51 SDTCisVT<7, i32>, // nfmt(imm)
52 SDTCisVT<8, i32>, // offen(imm)
53 SDTCisVT<9, i32>, // idxen(imm)
54 SDTCisVT<10, i32>, // glc(imm)
55 SDTCisVT<11, i32>, // slc(imm)
56 SDTCisVT<12, i32> // tfe(imm)
58 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]
61 def SDTBufferLoad : SDTypeProfile<1, 5,
63 SDTCisVT<1, v4i32>, // rsrc
64 SDTCisVT<2, i32>, // vindex
65 SDTCisVT<3, i32>, // offset
66 SDTCisVT<4, i1>, // glc
67 SDTCisVT<5, i1>]>; // slc
69 def SIbuffer_load : SDNode <"AMDGPUISD::BUFFER_LOAD", SDTBufferLoad,
70 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
71 def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad,
72 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
74 def SIload_input : SDNode<"AMDGPUISD::LOAD_INPUT",
75 SDTypeProfile<1, 3, [SDTCisVT<0, v4f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i16>,
79 class SDSample<string opcode> : SDNode <opcode,
80 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v8i32>,
81 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
84 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
85 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
86 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
87 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
89 def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET",
90 SDTypeProfile<1, 2, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>
93 //===----------------------------------------------------------------------===//
94 // PatFrags for global memory operations
95 //===----------------------------------------------------------------------===//
97 defm atomic_inc_global : global_binary_atomic_op<SIatomic_inc>;
98 defm atomic_dec_global : global_binary_atomic_op<SIatomic_dec>;
100 //===----------------------------------------------------------------------===//
101 // SDNodes and PatFrag for local loads and stores to enable s_mov_b32 m0, -1
102 // to be glued to the memory instructions.
103 //===----------------------------------------------------------------------===//
105 def SIld_local : SDNode <"ISD::LOAD", SDTLoad,
106 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
109 def si_ld_local : PatFrag <(ops node:$ptr), (SIld_local node:$ptr), [{
110 return cast<LoadSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
113 def si_load_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
114 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
115 cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
118 def si_load_local_align8 : Aligned8Bytes <
119 (ops node:$ptr), (si_load_local node:$ptr)
122 def si_sextload_local : PatFrag <(ops node:$ptr), (si_ld_local node:$ptr), [{
123 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
125 def si_az_extload_local : AZExtLoadBase <si_ld_local>;
127 multiclass SIExtLoadLocal <PatFrag ld_node> {
129 def _i8 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
130 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;}]
133 def _i16 : PatFrag <(ops node:$ptr), (ld_node node:$ptr),
134 [{return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;}]
138 defm si_sextload_local : SIExtLoadLocal <si_sextload_local>;
139 defm si_az_extload_local : SIExtLoadLocal <si_az_extload_local>;
141 def SIst_local : SDNode <"ISD::STORE", SDTStore,
142 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
145 def si_st_local : PatFrag <
146 (ops node:$val, node:$ptr), (SIst_local node:$val, node:$ptr), [{
147 return cast<StoreSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
150 def si_store_local : PatFrag <
151 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
152 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
153 !cast<StoreSDNode>(N)->isTruncatingStore();
156 def si_store_local_align8 : Aligned8Bytes <
157 (ops node:$val, node:$ptr), (si_store_local node:$val, node:$ptr)
160 def si_truncstore_local : PatFrag <
161 (ops node:$val, node:$ptr), (si_st_local node:$val, node:$ptr), [{
162 return cast<StoreSDNode>(N)->isTruncatingStore();
165 def si_truncstore_local_i8 : PatFrag <
166 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
167 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
170 def si_truncstore_local_i16 : PatFrag <
171 (ops node:$val, node:$ptr), (si_truncstore_local node:$val, node:$ptr), [{
172 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
175 def si_setcc_uniform : PatFrag <
176 (ops node:$lhs, node:$rhs, node:$cond),
177 (setcc node:$lhs, node:$rhs, node:$cond), [{
178 for (SDNode *Use : N->uses()) {
179 if (Use->isMachineOpcode() || Use->getOpcode() != ISD::CopyToReg)
182 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
183 if (Reg != AMDGPU::SCC)
189 def si_uniform_br : PatFrag <
190 (ops node:$cond, node:$bb), (brcond node:$cond, node:$bb), [{
191 return isUniformBr(N);
194 def si_uniform_br_scc : PatFrag <
195 (ops node:$cond, node:$bb), (si_uniform_br node:$cond, node:$bb), [{
196 return isCBranchSCC(N);
199 multiclass SIAtomicM0Glue2 <string op_name, bit is_amdgpu = 0> {
202 !if(is_amdgpu, "AMDGPUISD", "ISD")#"::ATOMIC_"#op_name, SDTAtomic2,
203 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
206 def _local : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
209 defm si_atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
210 defm si_atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
211 defm si_atomic_inc : SIAtomicM0Glue2 <"INC", 1>;
212 defm si_atomic_dec : SIAtomicM0Glue2 <"DEC", 1>;
213 defm si_atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
214 defm si_atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
215 defm si_atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
216 defm si_atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
217 defm si_atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
218 defm si_atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
219 defm si_atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
220 defm si_atomic_swap : SIAtomicM0Glue2 <"SWAP">;
222 def si_atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
223 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
226 defm si_atomic_cmp_swap : AtomicCmpSwapLocal <si_atomic_cmp_swap_glue>;
228 def as_i1imm : SDNodeXForm<imm, [{
229 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
232 def as_i8imm : SDNodeXForm<imm, [{
233 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
236 def as_i16imm : SDNodeXForm<imm, [{
237 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
240 def as_i32imm: SDNodeXForm<imm, [{
241 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
244 def as_i64imm: SDNodeXForm<imm, [{
245 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
248 // Copied from the AArch64 backend:
249 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
250 return CurDAG->getTargetConstant(
251 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
254 def frameindex_to_targetframeindex : SDNodeXForm<frameindex, [{
255 auto FI = cast<FrameIndexSDNode>(N);
256 return CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
259 // Copied from the AArch64 backend:
260 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
261 return CurDAG->getTargetConstant(
262 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
265 def SIMM16bit : PatLeaf <(imm),
266 [{return isInt<16>(N->getSExtValue());}]
269 def IMM20bit : PatLeaf <(imm),
270 [{return isUInt<20>(N->getZExtValue());}]
273 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
274 return isInlineImmediate(N);
277 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
278 return isInlineImmediate(N);
281 class VGPRImm <dag frag> : PatLeaf<frag, [{
282 if (Subtarget->getGeneration() < SISubtarget::SOUTHERN_ISLANDS) {
285 const SIRegisterInfo *SIRI =
286 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
288 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
289 Limit < 10 && U != E; ++U, ++Limit) {
290 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
292 // If the register class is unknown, it could be an unknown
293 // register class that needs to be an SGPR, e.g. an inline asm
295 if (!RC || SIRI->isSGPRClass(RC))
302 //===----------------------------------------------------------------------===//
304 //===----------------------------------------------------------------------===//
306 def SoppBrTarget : AsmOperandClass {
307 let Name = "SoppBrTarget";
308 let ParserMethod = "parseSOppBrTarget";
311 def sopp_brtarget : Operand<OtherVT> {
312 let EncoderMethod = "getSOPPBrEncoding";
313 let DecoderMethod = "decodeSoppBrTarget";
314 let OperandType = "OPERAND_PCREL";
315 let ParserMatchClass = SoppBrTarget;
318 def si_ga : Operand<iPTR>;
320 def InterpSlotMatchClass : AsmOperandClass {
321 let Name = "InterpSlot";
322 let PredicateMethod = "isInterpSlot";
323 let ParserMethod = "parseInterpSlot";
324 let RenderMethod = "addImmOperands";
327 def InterpSlot : Operand<i32> {
328 let PrintMethod = "printInterpSlot";
329 let ParserMatchClass = InterpSlotMatchClass;
330 let OperandType = "OPERAND_IMMEDIATE";
333 def AttrMatchClass : AsmOperandClass {
335 let PredicateMethod = "isInterpAttr";
336 let ParserMethod = "parseInterpAttr";
337 let RenderMethod = "addImmOperands";
340 // It appears to be necessary to create a separate operand for this to
341 // be able to parse attr<num> with no space.
342 def Attr : Operand<i32> {
343 let PrintMethod = "printInterpAttr";
344 let ParserMatchClass = AttrMatchClass;
345 let OperandType = "OPERAND_IMMEDIATE";
348 def AttrChanMatchClass : AsmOperandClass {
349 let Name = "AttrChan";
350 let PredicateMethod = "isAttrChan";
351 let RenderMethod = "addImmOperands";
354 def AttrChan : Operand<i32> {
355 let PrintMethod = "printInterpAttrChan";
356 let ParserMatchClass = AttrChanMatchClass;
357 let OperandType = "OPERAND_IMMEDIATE";
360 def SendMsgMatchClass : AsmOperandClass {
361 let Name = "SendMsg";
362 let PredicateMethod = "isSendMsg";
363 let ParserMethod = "parseSendMsgOp";
364 let RenderMethod = "addImmOperands";
367 def ExpTgtMatchClass : AsmOperandClass {
369 let PredicateMethod = "isExpTgt";
370 let ParserMethod = "parseExpTgt";
371 let RenderMethod = "printExpTgt";
374 def SendMsgImm : Operand<i32> {
375 let PrintMethod = "printSendMsg";
376 let ParserMatchClass = SendMsgMatchClass;
379 def SWaitMatchClass : AsmOperandClass {
380 let Name = "SWaitCnt";
381 let RenderMethod = "addImmOperands";
382 let ParserMethod = "parseSWaitCntOps";
385 def VReg32OrOffClass : AsmOperandClass {
386 let Name = "VReg32OrOff";
387 let ParserMethod = "parseVReg32OrOff";
390 def WAIT_FLAG : Operand <i32> {
391 let ParserMatchClass = SWaitMatchClass;
392 let PrintMethod = "printWaitFlag";
395 include "SIInstrFormats.td"
396 include "VIInstrFormats.td"
398 // ===----------------------------------------------------------------------===//
399 // ExpSrc* Special cases for exp src operands which are printed as
400 // "off" depending on en operand.
401 // ===----------------------------------------------------------------------===//
403 def ExpSrc0 : RegisterOperand<VGPR_32> {
404 let PrintMethod = "printExpSrc0";
405 let ParserMatchClass = VReg32OrOffClass;
408 def ExpSrc1 : RegisterOperand<VGPR_32> {
409 let PrintMethod = "printExpSrc1";
410 let ParserMatchClass = VReg32OrOffClass;
413 def ExpSrc2 : RegisterOperand<VGPR_32> {
414 let PrintMethod = "printExpSrc2";
415 let ParserMatchClass = VReg32OrOffClass;
418 def ExpSrc3 : RegisterOperand<VGPR_32> {
419 let PrintMethod = "printExpSrc3";
420 let ParserMatchClass = VReg32OrOffClass;
423 class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
424 let Name = "Imm"#CName;
425 let PredicateMethod = "is"#CName;
426 let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName);
427 let RenderMethod = "addImmOperands";
428 let IsOptional = Optional;
429 let DefaultMethod = !if(Optional, "default"#CName, ?);
432 class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> {
433 let PrintMethod = "print"#Name;
434 let ParserMatchClass = MatchClass;
437 class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> {
438 let PrintMethod = "print"#Name;
439 let ParserMatchClass = MatchClass;
442 class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
443 let PrintMethod = "print"#Name;
444 let ParserMatchClass = MatchClass;
447 class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
448 let PrintMethod = "print"#Name;
449 let ParserMatchClass = MatchClass;
452 let OperandType = "OPERAND_IMMEDIATE" in {
454 def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>;
455 def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
456 def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
458 def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
459 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
460 def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
462 def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
464 def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
465 def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
467 def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
468 def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
469 def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
470 def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
471 def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
472 def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
473 def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
474 def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
475 def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
477 def dmask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
479 def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
480 def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;
481 def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>;
482 def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>;
484 def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>;
485 def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>;
486 def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
487 def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
489 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
491 def exp_tgt : NamedOperandU8<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
495 } // End OperandType = "OPERAND_IMMEDIATE"
497 class KImmMatchClass<int size> : AsmOperandClass {
498 let Name = "KImmFP"#size;
499 let PredicateMethod = "isKImmFP"#size;
500 let ParserMethod = "parseImm";
501 let RenderMethod = "addKImmFP"#size#"Operands";
504 class kimmOperand<ValueType vt> : Operand<vt> {
505 let OperandNamespace = "AMDGPU";
506 let OperandType = "OPERAND_KIMM"#vt.Size;
507 let PrintMethod = "printU"#vt.Size#"ImmOperand";
508 let ParserMatchClass = !cast<AsmOperandClass>("KImmFP"#vt.Size#"MatchClass");
511 // 32-bit VALU immediate operand that uses the constant bus.
512 def KImmFP32MatchClass : KImmMatchClass<32>;
513 def f32kimm : kimmOperand<i32>;
515 // 32-bit VALU immediate operand with a 16-bit value that uses the
517 def KImmFP16MatchClass : KImmMatchClass<16>;
518 def f16kimm : kimmOperand<i16>;
521 def VOPDstS64 : VOPDstOperand <SReg_64>;
523 class FPInputModsMatchClass <int opSize> : AsmOperandClass {
524 let Name = "RegOrImmWithFP"#opSize#"InputMods";
525 let ParserMethod = "parseRegOrImmWithFPInputMods";
526 let PredicateMethod = "isRegOrImmWithFP"#opSize#"InputMods";
528 def FP16InputModsMatchClass : FPInputModsMatchClass<16>;
529 def FP32InputModsMatchClass : FPInputModsMatchClass<32>;
530 def FP64InputModsMatchClass : FPInputModsMatchClass<64>;
532 class InputMods <AsmOperandClass matchClass> : Operand <i32> {
533 let OperandNamespace = "AMDGPU";
534 let OperandType = "OPERAND_INPUT_MODS";
535 let ParserMatchClass = matchClass;
538 class FPInputMods <FPInputModsMatchClass matchClass> : InputMods <matchClass> {
539 let PrintMethod = "printOperandAndFPInputMods";
542 def FP16InputMods : FPInputMods<FP16InputModsMatchClass>;
543 def FP32InputMods : FPInputMods<FP32InputModsMatchClass>;
544 def FP64InputMods : FPInputMods<FP64InputModsMatchClass>;
546 class IntInputModsMatchClass <int opSize> : AsmOperandClass {
547 let Name = "RegOrImmWithInt"#opSize#"InputMods";
548 let ParserMethod = "parseRegOrImmWithIntInputMods";
549 let PredicateMethod = "isRegOrImmWithInt"#opSize#"InputMods";
551 def Int32InputModsMatchClass : IntInputModsMatchClass<32>;
552 def Int64InputModsMatchClass : IntInputModsMatchClass<64>;
554 class IntInputMods <IntInputModsMatchClass matchClass> : InputMods <matchClass> {
555 let PrintMethod = "printOperandAndIntInputMods";
557 def Int32InputMods : IntInputMods<Int32InputModsMatchClass>;
558 def Int64InputMods : IntInputMods<Int64InputModsMatchClass>;
560 def FPVRegInputModsMatchClass : AsmOperandClass {
561 let Name = "VRegWithFPInputMods";
562 let ParserMethod = "parseRegWithFPInputMods";
563 let PredicateMethod = "isVReg";
566 def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
567 let PrintMethod = "printOperandAndFPInputMods";
570 def IntVRegInputModsMatchClass : AsmOperandClass {
571 let Name = "VRegWithIntInputMods";
572 let ParserMethod = "parseRegWithIntInputMods";
573 let PredicateMethod = "isVReg";
576 def IntVRegInputMods : InputMods <IntVRegInputModsMatchClass> {
577 let PrintMethod = "printOperandAndIntInputMods";
581 //===----------------------------------------------------------------------===//
583 //===----------------------------------------------------------------------===//
585 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
586 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
588 def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
590 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
591 def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
592 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
593 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
594 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
595 def VOP3NoMods : ComplexPattern<untyped, 2, "SelectVOP3NoMods">;
597 //===----------------------------------------------------------------------===//
598 // SI assembler operands
599 //===----------------------------------------------------------------------===//
620 //===----------------------------------------------------------------------===//
622 // SI Instruction multiclass helpers.
624 // Instructions with _32 take 32-bit operands.
625 // Instructions with _64 take 64-bit operands.
627 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
628 // encoding is the standard encoding, but instruction that make use of
629 // any of the instruction modifiers must use the 64-bit encoding.
631 // Instructions with _e32 use the 32-bit encoding.
632 // Instructions with _e64 use the 64-bit encoding.
634 //===----------------------------------------------------------------------===//
636 class SIMCInstr <string pseudo, int subtarget> {
637 string PseudoInstr = pseudo;
638 int Subtarget = subtarget;
641 //===----------------------------------------------------------------------===//
643 //===----------------------------------------------------------------------===//
645 class EXP_Helper<bit done, SDPatternOperator node = null_frag> : EXPCommon<
648 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
649 exp_vm:$vm, exp_compr:$compr, i8imm:$en),
650 "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm",
651 [(node (i8 timm:$en), (i1 timm:$vm), (i8 timm:$tgt), (i1 timm:$compr),
652 f32:$src0, f32:$src1, f32:$src2, f32:$src3)]> {
653 let AsmMatchConverter = "cvtExp";
656 // Split EXP instruction into EXP and EXP_DONE so we can set
657 // mayLoad for done=1.
658 multiclass EXP_m<bit done, SDPatternOperator node> {
659 let mayLoad = done in {
660 let isPseudo = 1, isCodeGenOnly = 1 in {
661 def "" : EXP_Helper<done, node>,
662 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.NONE>;
666 def _si : EXP_Helper<done>,
667 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>,
669 let DecoderNamespace = "SICI";
670 let DisableDecoder = DisableSIDecoder;
673 def _vi : EXP_Helper<done>,
674 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
676 let DecoderNamespace = "VI";
677 let DisableDecoder = DisableVIDecoder;
683 //===----------------------------------------------------------------------===//
684 // Vector ALU classes
685 //===----------------------------------------------------------------------===//
687 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
689 !if (!eq(Src0.Value, untyped.Value), 0,
690 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
691 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
695 // Returns the register class to use for the destination of VOP[123C]
696 // instructions for the given VT.
697 class getVALUDstForVT<ValueType VT> {
698 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
699 !if(!eq(VT.Size, 128), VOPDstOperand<VReg_128>,
700 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
701 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
702 VOPDstOperand<SReg_64>)))); // else VT == i1
705 // Returns the register class to use for source 0 of VOP[12C]
706 // instructions for the given VT.
707 class getVOPSrc0ForVT<ValueType VT> {
708 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
709 !if(!eq(VT.Value, f32.Value), 1,
710 !if(!eq(VT.Value, f64.Value), 1,
712 RegisterOperand ret = !if(isFP,
713 !if(!eq(VT.Size, 64), VSrc_f64, !if(!eq(VT.Size, 16), VSrc_f16, VSrc_f32)),
714 !if(!eq(VT.Size, 64), VSrc_b64, !if(!eq(VT.Size, 16), VSrc_b16, VSrc_b32)));
717 // Returns the vreg register class to use for source operand given VT
718 class getVregSrcForVT<ValueType VT> {
719 RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128,
720 !if(!eq(VT.Size, 64), VReg_64, VGPR_32));
724 // Returns the register class to use for sources of VOP3 instructions for the
726 class getVOP3SrcForVT<ValueType VT> {
727 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
728 !if(!eq(VT.Value, f32.Value), 1,
729 !if(!eq(VT.Value, f64.Value), 1,
731 RegisterOperand ret =
732 !if(!eq(VT.Size, 128),
734 !if(!eq(VT.Size, 64),
738 !if(!eq(VT.Value, i1.Value),
741 !if(!eq(VT.Size, 16), VCSrc_f16, VCSrc_f32),
742 !if(!eq(VT.Size, 16), VCSrc_b16, VCSrc_b32)
749 // Returns 1 if the source arguments have modifiers, 0 if they do not.
750 // XXX - do f16 instructions?
751 class isFloatType<ValueType SrcVT> {
753 !if(!eq(SrcVT.Value, f16.Value), 1,
754 !if(!eq(SrcVT.Value, f32.Value), 1,
755 !if(!eq(SrcVT.Value, f64.Value), 1,
759 class isIntType<ValueType SrcVT> {
761 !if(!eq(SrcVT.Value, i16.Value), 1,
762 !if(!eq(SrcVT.Value, i32.Value), 1,
763 !if(!eq(SrcVT.Value, i64.Value), 1,
768 // Return type of input modifiers operand for specified input operand
769 class getSrcMod <ValueType VT> {
770 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
771 !if(!eq(VT.Value, f32.Value), 1,
772 !if(!eq(VT.Value, f64.Value), 1,
774 Operand ret = !if(!eq(VT.Size, 64),
775 !if(isFP, FP64InputMods, Int64InputMods),
777 !if(!eq(VT.Value, f16.Value),
785 // Return type of input modifiers operand specified input operand for SDWA/DPP
786 class getSrcModExt <ValueType VT> {
787 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
788 !if(!eq(VT.Value, f32.Value), 1,
789 !if(!eq(VT.Value, f64.Value), 1,
791 Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
794 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
795 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
796 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
797 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
801 // Returns the input arguments for VOP3 instructions for the given SrcVT.
802 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
803 RegisterOperand Src2RC, int NumSrcArgs,
804 bit HasModifiers, Operand Src0Mod, Operand Src1Mod,
808 !if (!eq(NumSrcArgs, 0),
809 // VOP1 without input operands (V_NOP, V_CLREXCP)
812 !if (!eq(NumSrcArgs, 1),
813 !if (!eq(HasModifiers, 1),
814 // VOP1 with modifiers
815 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
816 clampmod:$clamp, omod:$omod)
818 // VOP1 without modifiers
821 !if (!eq(NumSrcArgs, 2),
822 !if (!eq(HasModifiers, 1),
823 // VOP 2 with modifiers
824 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
825 Src1Mod:$src1_modifiers, Src1RC:$src1,
826 clampmod:$clamp, omod:$omod)
828 // VOP2 without modifiers
829 (ins Src0RC:$src0, Src1RC:$src1)
831 /* NumSrcArgs == 3 */,
832 !if (!eq(HasModifiers, 1),
833 // VOP3 with modifiers
834 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
835 Src1Mod:$src1_modifiers, Src1RC:$src1,
836 Src2Mod:$src2_modifiers, Src2RC:$src2,
837 clampmod:$clamp, omod:$omod)
839 // VOP3 without modifiers
840 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2)
844 class getInsDPP <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
845 bit HasModifiers, Operand Src0Mod, Operand Src1Mod> {
847 dag ret = !if (!eq(NumSrcArgs, 0),
848 // VOP1 without input operands (V_NOP)
849 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
850 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl),
851 !if (!eq(NumSrcArgs, 1),
852 !if (!eq(HasModifiers, 1),
853 // VOP1_DPP with modifiers
854 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
855 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
856 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
858 // VOP1_DPP without modifiers
859 (ins Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
860 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
862 /* NumSrcArgs == 2 */,
863 !if (!eq(HasModifiers, 1),
864 // VOP2_DPP with modifiers
865 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
866 Src1Mod:$src1_modifiers, Src1RC:$src1,
867 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
868 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
870 // VOP2_DPP without modifiers
871 (ins Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
872 row_mask:$row_mask, bank_mask:$bank_mask,
873 bound_ctrl:$bound_ctrl)
877 class getInsSDWA <RegisterClass Src0RC, RegisterClass Src1RC, int NumSrcArgs,
878 bit HasFloatModifiers, Operand Src0Mod, Operand Src1Mod,
881 dag ret = !if(!eq(NumSrcArgs, 0),
882 // VOP1 without input operands (V_NOP)
884 !if(!eq(NumSrcArgs, 1),
885 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
886 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
888 !if(!eq(NumSrcArgs, 2),
889 !if(!eq(DstVT.Size, 1),
890 // VOPC_SDWA with modifiers
891 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
892 Src1Mod:$src1_modifiers, Src1RC:$src1,
893 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
894 // VOP2_SDWA or VOPC_SDWA with modifiers
895 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
896 Src1Mod:$src1_modifiers, Src1RC:$src1,
897 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
898 src0_sel:$src0_sel, src1_sel:$src1_sel)),
902 // Outs for DPP and SDWA
903 class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCDPP> {
904 dag ret = !if(HasDst,
905 !if(!eq(DstVT.Size, 1),
906 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
907 (outs DstRCDPP:$vdst)),
911 // Returns the assembly string for the inputs and outputs of a VOP[12C]
912 // instruction. This does not add the _e32 suffix, so it can be reused
914 class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
915 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
916 string src0 = ", $src0";
917 string src1 = ", $src1";
918 string src2 = ", $src2";
919 string ret = !if(HasDst, dst, "") #
920 !if(!eq(NumSrcArgs, 1), src0, "") #
921 !if(!eq(NumSrcArgs, 2), src0#src1, "") #
922 !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
925 // Returns the assembly string for the inputs and outputs of a VOP3
927 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
928 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
929 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
930 string src1 = !if(!eq(NumSrcArgs, 1), "",
931 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
932 " $src1_modifiers,"));
933 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
935 !if(!eq(HasModifiers, 0),
936 getAsm32<HasDst, NumSrcArgs, DstVT>.ret,
937 dst#", "#src0#src1#src2#"$clamp"#"$omod");
940 class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
941 string dst = !if(HasDst,
942 !if(!eq(DstVT.Size, 1),
945 ""); // use $sdst for VOPC
946 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
947 string src1 = !if(!eq(NumSrcArgs, 1), "",
948 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
949 " $src1_modifiers,"));
950 string args = !if(!eq(HasModifiers, 0),
951 getAsm32<0, NumSrcArgs, DstVT>.ret,
953 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
956 class getAsmSDWA <bit HasDst, int NumSrcArgs, bit HasFloatModifiers,
957 ValueType DstVT = i32> {
958 string dst = !if(HasDst,
959 !if(!eq(DstVT.Size, 1),
960 " vcc", // use vcc token as dst for VOPC instructioins
963 string src0 = "$src0_modifiers";
964 string src1 = "$src1_modifiers";
965 string args = !if(!eq(NumSrcArgs, 0),
967 !if(!eq(NumSrcArgs, 1),
969 ", "#src0#", "#src1#"$clamp"
972 string sdwa = !if(!eq(NumSrcArgs, 0),
974 !if(!eq(NumSrcArgs, 1),
975 " $dst_sel $dst_unused $src0_sel",
976 !if(!eq(DstVT.Size, 1),
977 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
978 " $dst_sel $dst_unused $src0_sel $src1_sel"
982 string ret = dst#args#sdwa;
985 // Function that checks if instruction supports DPP and SDWA
986 class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
987 ValueType Src1VT = i32> {
988 bit ret = !if(!eq(NumSrcArgs, 3),
989 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
990 !if(!eq(DstVT.Size, 64),
991 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
992 !if(!eq(Src0VT.Size, 64),
994 !if(!eq(Src0VT.Size, 64),
1003 class BitOr<bit a, bit b> {
1004 bit ret = !if(a, 1, !if(b, 1, 0));
1007 class BitAnd<bit a, bit b> {
1008 bit ret = !if(a, !if(b, 1, 0), 0);
1011 class VOPProfile <list<ValueType> _ArgVT> {
1013 field list<ValueType> ArgVT = _ArgVT;
1015 field ValueType DstVT = ArgVT[0];
1016 field ValueType Src0VT = ArgVT[1];
1017 field ValueType Src1VT = ArgVT[2];
1018 field ValueType Src2VT = ArgVT[3];
1019 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1020 field RegisterOperand DstRCDPP = getVALUDstForVT<DstVT>.ret;
1021 field RegisterOperand DstRCSDWA = getVALUDstForVT<DstVT>.ret;
1022 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1023 field RegisterClass Src1RC32 = getVregSrcForVT<Src1VT>.ret;
1024 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1025 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1026 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1027 field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
1028 field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
1029 field RegisterClass Src0SDWA = getVregSrcForVT<Src0VT>.ret;
1030 field RegisterClass Src1SDWA = getVregSrcForVT<Src1VT>.ret;
1031 field Operand Src0Mod = getSrcMod<Src0VT>.ret;
1032 field Operand Src1Mod = getSrcMod<Src1VT>.ret;
1033 field Operand Src2Mod = getSrcMod<Src2VT>.ret;
1034 field Operand Src0ModDPP = getSrcModExt<Src0VT>.ret;
1035 field Operand Src1ModDPP = getSrcModExt<Src1VT>.ret;
1036 field Operand Src0ModSDWA = getSrcModExt<Src0VT>.ret;
1037 field Operand Src1ModSDWA = getSrcModExt<Src1VT>.ret;
1040 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
1041 field bit HasDst32 = HasDst;
1042 field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
1043 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1044 field bit HasSrc0 = !if(!eq(Src0VT.Value, untyped.Value), 0, 1);
1045 field bit HasSrc1 = !if(!eq(Src1VT.Value, untyped.Value), 0, 1);
1046 field bit HasSrc2 = !if(!eq(Src2VT.Value, untyped.Value), 0, 1);
1048 // TODO: Modifiers logic is somewhat adhoc here, to be refined later
1049 field bit HasModifiers = isFloatType<Src0VT>.ret;
1051 field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
1052 field bit HasSrc1FloatMods = isFloatType<Src1VT>.ret;
1053 field bit HasSrc2FloatMods = isFloatType<Src2VT>.ret;
1055 field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
1056 field bit HasSrc1IntMods = isIntType<Src1VT>.ret;
1057 field bit HasSrc2IntMods = isIntType<Src2VT>.ret;
1059 field bit HasSrc0Mods = HasModifiers;
1060 field bit HasSrc1Mods = !if(HasModifiers, BitOr<HasSrc1FloatMods, HasSrc1IntMods>.ret, 0);
1061 field bit HasSrc2Mods = !if(HasModifiers, BitOr<HasSrc2FloatMods, HasSrc2IntMods>.ret, 0);
1063 field bit HasOMod = HasModifiers;
1064 field bit HasClamp = HasModifiers;
1065 field bit HasSDWAClamp = HasSrc0;
1067 field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
1069 field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
1071 // VOP3b instructions are a special case with a second explicit
1072 // output. This is manually overridden for them.
1073 field dag Outs32 = Outs;
1074 field dag Outs64 = Outs;
1075 field dag OutsDPP = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
1076 field dag OutsSDWA = getOutsExt<HasDst, DstVT, DstRCSDWA>.ret;
1078 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1079 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1080 HasModifiers, Src0Mod, Src1Mod, Src2Mod>.ret;
1081 field dag InsDPP = getInsDPP<Src0DPP, Src1DPP, NumSrcArgs,
1082 HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
1083 field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs,
1084 HasModifiers, Src0ModSDWA, Src1ModSDWA,
1087 field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
1088 field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
1089 field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
1090 field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
1093 class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
1097 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
1098 def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
1099 def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
1101 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
1102 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
1103 def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
1104 def VOP_I16_I16_I16 : VOPProfile <[i32, i32, i32, untyped]>;
1106 def VOP_I16_I16_I16_I16 : VOPProfile <[i32, i32, i32, i32, untyped]>;
1107 def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
1109 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
1111 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1112 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1113 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1114 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1115 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1116 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1117 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1118 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1119 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1121 def VOP_F32_F32_F16 : VOPProfile <[f32, f32, f16, untyped]>;
1122 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1123 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1124 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1125 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1126 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1127 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1128 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1130 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1131 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1132 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1134 def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
1135 def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
1136 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1137 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1138 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1139 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1140 def VOP_I32_F32_I32_I32 : VOPProfile <[i32, f32, i32, i32]>;
1141 def VOP_I64_I64_I32_I64 : VOPProfile <[i64, i64, i32, i64]>;
1142 def VOP_V4I32_I64_I32_V4I32 : VOPProfile <[v4i32, i64, i32, v4i32]>;
1144 class Commutable_REV <string revOp, bit isOrig> {
1145 string RevOp = revOp;
1146 bit IsOrig = isOrig;
1149 class AtomicNoRet <string noRetOp, bit isRet> {
1150 string NoRetOp = noRetOp;
1154 //===----------------------------------------------------------------------===//
1155 // Interpolation opcodes
1156 //===----------------------------------------------------------------------===//
1158 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1159 VINTRPCommon <outs, ins, "", pattern>,
1160 SIMCInstr<opName, SIEncodingFamily.NONE> {
1162 let isCodeGenOnly = 1;
1165 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1167 VINTRPCommon <outs, ins, asm, []>,
1169 SIMCInstr<opName, SIEncodingFamily.SI> {
1170 let AssemblerPredicate = SIAssemblerPredicate;
1171 let DecoderNamespace = "SICI";
1172 let DisableDecoder = DisableSIDecoder;
1175 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1177 VINTRPCommon <outs, ins, asm, []>,
1179 SIMCInstr<opName, SIEncodingFamily.VI> {
1180 let AssemblerPredicate = VIAssemblerPredicate;
1181 let DecoderNamespace = "VI";
1182 let DisableDecoder = DisableVIDecoder;
1185 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1186 list<dag> pattern = []> {
1187 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1189 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1191 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1194 //===----------------------------------------------------------------------===//
1195 // Vector instruction mappings
1196 //===----------------------------------------------------------------------===//
1198 // Maps an opcode in e32 form to its e64 equivalent
1199 def getVOPe64 : InstrMapping {
1200 let FilterClass = "VOP";
1201 let RowFields = ["OpName"];
1202 let ColFields = ["Size", "VOP3"];
1203 let KeyCol = ["4", "0"];
1204 let ValueCols = [["8", "1"]];
1207 // Maps an opcode in e64 form to its e32 equivalent
1208 def getVOPe32 : InstrMapping {
1209 let FilterClass = "VOP";
1210 let RowFields = ["OpName"];
1211 let ColFields = ["Size", "VOP3"];
1212 let KeyCol = ["8", "1"];
1213 let ValueCols = [["4", "0"]];
1216 def getMaskedMIMGOp : InstrMapping {
1217 let FilterClass = "MIMG_Mask";
1218 let RowFields = ["Op"];
1219 let ColFields = ["Channels"];
1221 let ValueCols = [["1"], ["2"], ["3"] ];
1224 // Maps an commuted opcode to its original version
1225 def getCommuteOrig : InstrMapping {
1226 let FilterClass = "Commutable_REV";
1227 let RowFields = ["RevOp"];
1228 let ColFields = ["IsOrig"];
1230 let ValueCols = [["1"]];
1233 // Maps an original opcode to its commuted version
1234 def getCommuteRev : InstrMapping {
1235 let FilterClass = "Commutable_REV";
1236 let RowFields = ["RevOp"];
1237 let ColFields = ["IsOrig"];
1239 let ValueCols = [["0"]];
1242 def getMCOpcodeGen : InstrMapping {
1243 let FilterClass = "SIMCInstr";
1244 let RowFields = ["PseudoInstr"];
1245 let ColFields = ["Subtarget"];
1246 let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
1247 let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
1248 [!cast<string>(SIEncodingFamily.VI)]];
1251 // Get equivalent SOPK instruction.
1252 def getSOPKOp : InstrMapping {
1253 let FilterClass = "SOPKInstTable";
1254 let RowFields = ["BaseCmpOp"];
1255 let ColFields = ["IsSOPK"];
1257 let ValueCols = [["1"]];
1260 def getAddr64Inst : InstrMapping {
1261 let FilterClass = "MUBUFAddr64Table";
1262 let RowFields = ["OpName"];
1263 let ColFields = ["IsAddr64"];
1265 let ValueCols = [["1"]];
1268 // Maps an atomic opcode to its version with a return value.
1269 def getAtomicRetOp : InstrMapping {
1270 let FilterClass = "AtomicNoRet";
1271 let RowFields = ["NoRetOp"];
1272 let ColFields = ["IsRet"];
1274 let ValueCols = [["1"]];
1277 // Maps an atomic opcode to its returnless version.
1278 def getAtomicNoRetOp : InstrMapping {
1279 let FilterClass = "AtomicNoRet";
1280 let RowFields = ["NoRetOp"];
1281 let ColFields = ["IsRet"];
1283 let ValueCols = [["0"]];
1286 include "SIInstructions.td"
1287 include "CIInstructions.td"
1289 include "DSInstructions.td"
1290 include "MIMGInstructions.td"