1 //===-- SIInstrInfo.td - SI Instruction Infos -------------*- tablegen -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 def isCI : Predicate<"Subtarget->getGeneration() "
10 ">= SISubtarget::SEA_ISLANDS">;
11 def isCIOnly : Predicate<"Subtarget->getGeneration() =="
12 "SISubtarget::SEA_ISLANDS">,
13 AssemblerPredicate <"FeatureSeaIslands">;
14 def isVIOnly : Predicate<"Subtarget->getGeneration() =="
15 "SISubtarget::VOLCANIC_ISLANDS">,
16 AssemblerPredicate <"FeatureVolcanicIslands">;
18 def DisableInst : Predicate <"false">, AssemblerPredicate<"FeatureDisable">;
20 // Execpt for the NONE field, this must be kept in sync with the
21 // SIEncodingFamily enum in AMDGPUInstrInfo.cpp
22 def SIEncodingFamily {
31 //===----------------------------------------------------------------------===//
33 //===----------------------------------------------------------------------===//
35 def SIload_constant : SDNode<"AMDGPUISD::LOAD_CONSTANT",
36 SDTypeProfile<1, 2, [SDTCisVT<0, f32>, SDTCisVT<1, v4i32>, SDTCisVT<2, i32>]>,
37 [SDNPMayLoad, SDNPMemOperand]
40 def SIatomic_inc : SDNode<"AMDGPUISD::ATOMIC_INC", SDTAtomic2,
41 [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
44 def SIatomic_dec : SDNode<"AMDGPUISD::ATOMIC_DEC", SDTAtomic2,
45 [SDNPMayLoad, SDNPMayStore, SDNPMemOperand, SDNPHasChain]
48 def SItbuffer_load : SDNode<"AMDGPUISD::TBUFFER_LOAD_FORMAT",
51 SDTCisVT<1, v4i32>, // rsrc
52 SDTCisVT<2, i32>, // vindex(VGPR)
53 SDTCisVT<3, i32>, // voffset(VGPR)
54 SDTCisVT<4, i32>, // soffset(SGPR)
55 SDTCisVT<5, i32>, // offset(imm)
56 SDTCisVT<6, i32>, // dfmt(imm)
57 SDTCisVT<7, i32>, // nfmt(imm)
58 SDTCisVT<8, i32>, // glc(imm)
59 SDTCisVT<9, i32> // slc(imm)
61 [SDNPMayLoad, SDNPMemOperand, SDNPHasChain]
64 def SDTtbuffer_store : SDTypeProfile<0, 10,
66 SDTCisVT<1, v4i32>, // rsrc
67 SDTCisVT<2, i32>, // vindex(VGPR)
68 SDTCisVT<3, i32>, // voffset(VGPR)
69 SDTCisVT<4, i32>, // soffset(SGPR)
70 SDTCisVT<5, i32>, // offset(imm)
71 SDTCisVT<6, i32>, // dfmt(imm)
72 SDTCisVT<7, i32>, // nfmt(imm)
73 SDTCisVT<8, i32>, // glc(imm)
74 SDTCisVT<9, i32> // slc(imm)
77 def SItbuffer_store : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT", SDTtbuffer_store,
78 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
79 def SItbuffer_store_x3 : SDNode<"AMDGPUISD::TBUFFER_STORE_FORMAT_X3",
81 [SDNPMayStore, SDNPMemOperand, SDNPHasChain]>;
83 def SDTBufferLoad : SDTypeProfile<1, 5,
85 SDTCisVT<1, v4i32>, // rsrc
86 SDTCisVT<2, i32>, // vindex
87 SDTCisVT<3, i32>, // offset
88 SDTCisVT<4, i1>, // glc
89 SDTCisVT<5, i1>]>; // slc
91 def SIbuffer_load : SDNode <"AMDGPUISD::BUFFER_LOAD", SDTBufferLoad,
92 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
93 def SIbuffer_load_format : SDNode <"AMDGPUISD::BUFFER_LOAD_FORMAT", SDTBufferLoad,
94 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad]>;
96 def SDTBufferStore : SDTypeProfile<0, 6,
98 SDTCisVT<1, v4i32>, // rsrc
99 SDTCisVT<2, i32>, // vindex
100 SDTCisVT<3, i32>, // offset
101 SDTCisVT<4, i1>, // glc
102 SDTCisVT<5, i1>]>; // slc
104 def SIbuffer_store : SDNode <"AMDGPUISD::BUFFER_STORE", SDTBufferStore,
105 [SDNPMemOperand, SDNPHasChain, SDNPMayStore]>;
106 def SIbuffer_store_format : SDNode <"AMDGPUISD::BUFFER_STORE_FORMAT", SDTBufferStore,
107 [SDNPMemOperand, SDNPHasChain, SDNPMayStore]>;
109 class SDBufferAtomic<string opcode> : SDNode <opcode,
111 [SDTCisVT<0, i32>, // dst
112 SDTCisVT<1, i32>, // vdata
113 SDTCisVT<2, v4i32>, // rsrc
114 SDTCisVT<3, i32>, // vindex
115 SDTCisVT<4, i32>, // offset
116 SDTCisVT<5, i1>]>, // slc
117 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
120 def SIbuffer_atomic_swap : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SWAP">;
121 def SIbuffer_atomic_add : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_ADD">;
122 def SIbuffer_atomic_sub : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SUB">;
123 def SIbuffer_atomic_smin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SMIN">;
124 def SIbuffer_atomic_umin : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_UMIN">;
125 def SIbuffer_atomic_smax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_SMAX">;
126 def SIbuffer_atomic_umax : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_UMAX">;
127 def SIbuffer_atomic_and : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_AND">;
128 def SIbuffer_atomic_or : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_OR">;
129 def SIbuffer_atomic_xor : SDBufferAtomic <"AMDGPUISD::BUFFER_ATOMIC_XOR">;
131 def SIbuffer_atomic_cmpswap : SDNode <"AMDGPUISD::BUFFER_ATOMIC_CMPSWAP",
133 [SDTCisVT<0, i32>, // dst
134 SDTCisVT<1, i32>, // src
135 SDTCisVT<2, i32>, // cmp
136 SDTCisVT<3, v4i32>, // rsrc
137 SDTCisVT<4, i32>, // vindex
138 SDTCisVT<5, i32>, // offset
139 SDTCisVT<6, i1>]>, // slc
140 [SDNPMemOperand, SDNPHasChain, SDNPMayLoad, SDNPMayStore]
143 class SDSample<string opcode> : SDNode <opcode,
144 SDTypeProfile<1, 4, [SDTCisVT<0, v4f32>, SDTCisVT<2, v8i32>,
145 SDTCisVT<3, v4i32>, SDTCisVT<4, i32>]>
148 def SIsample : SDSample<"AMDGPUISD::SAMPLE">;
149 def SIsampleb : SDSample<"AMDGPUISD::SAMPLEB">;
150 def SIsampled : SDSample<"AMDGPUISD::SAMPLED">;
151 def SIsamplel : SDSample<"AMDGPUISD::SAMPLEL">;
153 def SIpc_add_rel_offset : SDNode<"AMDGPUISD::PC_ADD_REL_OFFSET",
154 SDTypeProfile<1, 2, [SDTCisVT<0, iPTR>, SDTCisSameAs<0,1>, SDTCisSameAs<0,2>]>
157 //===----------------------------------------------------------------------===//
158 // PatFrags for global memory operations
159 //===----------------------------------------------------------------------===//
161 defm atomic_inc_global : global_binary_atomic_op<SIatomic_inc>;
162 defm atomic_dec_global : global_binary_atomic_op<SIatomic_dec>;
164 def atomic_inc_local : local_binary_atomic_op<SIatomic_inc>;
165 def atomic_dec_local : local_binary_atomic_op<SIatomic_dec>;
167 //===----------------------------------------------------------------------===//
168 // SDNodes PatFrags for loads/stores with a glue input.
169 // This is for SDNodes and PatFrag for local loads and stores to
170 // enable s_mov_b32 m0, -1 to be glued to the memory instructions.
172 // These mirror the regular load/store PatFrags and rely on special
173 // processing during Select() to add the glued copy.
175 //===----------------------------------------------------------------------===//
177 def AMDGPUld_glue : SDNode <"ISD::LOAD", SDTLoad,
178 [SDNPHasChain, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
181 def unindexedload_glue : PatFrag <(ops node:$ptr), (AMDGPUld_glue node:$ptr), [{
182 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
185 def load_glue : PatFrag <(ops node:$ptr), (unindexedload_glue node:$ptr), [{
186 return cast<LoadSDNode>(N)->getExtensionType() == ISD::NON_EXTLOAD;
189 def extload_glue : PatFrag<(ops node:$ptr), (load_glue node:$ptr), [{
190 return cast<LoadSDNode>(N)->getExtensionType() == ISD::EXTLOAD;
193 def sextload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr), [{
194 return cast<LoadSDNode>(N)->getExtensionType() == ISD::SEXTLOAD;
197 def zextload_glue : PatFrag<(ops node:$ptr), (unindexedload_glue node:$ptr), [{
198 return cast<LoadSDNode>(N)->getExtensionType() == ISD::ZEXTLOAD;
201 def az_extload_glue : AZExtLoadBase <unindexedload_glue>;
203 def az_extloadi8_glue : PatFrag<(ops node:$ptr), (az_extload_glue node:$ptr), [{
204 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
207 def az_extloadi16_glue : PatFrag<(ops node:$ptr), (az_extload_glue node:$ptr), [{
208 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
211 def sextloadi8_glue : PatFrag<(ops node:$ptr), (sextload_glue node:$ptr), [{
212 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
215 def sextloadi16_glue : PatFrag<(ops node:$ptr), (sextload_glue node:$ptr), [{
216 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
219 def load_glue_align8 : Aligned8Bytes <
220 (ops node:$ptr), (load_glue node:$ptr)
224 def load_local_m0 : LoadFrag<load_glue>, LocalAddress;
225 def sextloadi8_local_m0 : LoadFrag<sextloadi8_glue>, LocalAddress;
226 def sextloadi16_local_m0 : LoadFrag<sextloadi16_glue>, LocalAddress;
227 def az_extloadi8_local_m0 : LoadFrag<az_extloadi8_glue>, LocalAddress;
228 def az_extloadi16_local_m0 : LoadFrag<az_extloadi16_glue>, LocalAddress;
229 def load_align8_local_m0 : LoadFrag <load_glue_align8>, LocalAddress;
232 def AMDGPUst_glue : SDNode <"ISD::STORE", SDTStore,
233 [SDNPHasChain, SDNPMayStore, SDNPMemOperand, SDNPInGlue]
236 def unindexedstore_glue : PatFrag<(ops node:$val, node:$ptr),
237 (AMDGPUst_glue node:$val, node:$ptr), [{
238 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
241 def store_glue : PatFrag<(ops node:$val, node:$ptr),
242 (unindexedstore_glue node:$val, node:$ptr), [{
243 return !cast<StoreSDNode>(N)->isTruncatingStore();
246 def truncstore_glue : PatFrag<(ops node:$val, node:$ptr),
247 (unindexedstore_glue node:$val, node:$ptr), [{
248 return cast<StoreSDNode>(N)->isTruncatingStore();
251 def truncstorei8_glue : PatFrag<(ops node:$val, node:$ptr),
252 (truncstore_glue node:$val, node:$ptr), [{
253 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i8;
256 def truncstorei16_glue : PatFrag<(ops node:$val, node:$ptr),
257 (truncstore_glue node:$val, node:$ptr), [{
258 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i16;
261 def store_glue_align8 : Aligned8Bytes <
262 (ops node:$value, node:$ptr), (store_glue node:$value, node:$ptr)
265 def store_local_m0 : StoreFrag<store_glue>, LocalAddress;
266 def truncstorei8_local_m0 : StoreFrag<truncstorei8_glue>, LocalAddress;
267 def truncstorei16_local_m0 : StoreFrag<truncstorei16_glue>, LocalAddress;
269 def store_align8_local_m0 : StoreFrag<store_glue_align8>, LocalAddress;
271 def si_setcc_uniform : PatFrag <
272 (ops node:$lhs, node:$rhs, node:$cond),
273 (setcc node:$lhs, node:$rhs, node:$cond), [{
274 for (SDNode *Use : N->uses()) {
275 if (Use->isMachineOpcode() || Use->getOpcode() != ISD::CopyToReg)
278 unsigned Reg = cast<RegisterSDNode>(Use->getOperand(1))->getReg();
279 if (Reg != AMDGPU::SCC)
285 def lshr_rev : PatFrag <
286 (ops node:$src1, node:$src0),
290 def ashr_rev : PatFrag <
291 (ops node:$src1, node:$src0),
295 def lshl_rev : PatFrag <
296 (ops node:$src1, node:$src0),
300 multiclass SIAtomicM0Glue2 <string op_name, bit is_amdgpu = 0> {
303 !if(is_amdgpu, "AMDGPUISD", "ISD")#"::ATOMIC_"#op_name, SDTAtomic2,
304 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
307 def _local_m0 : local_binary_atomic_op <!cast<SDNode>(NAME#"_glue")>;
310 defm atomic_load_add : SIAtomicM0Glue2 <"LOAD_ADD">;
311 defm atomic_load_sub : SIAtomicM0Glue2 <"LOAD_SUB">;
312 defm atomic_inc : SIAtomicM0Glue2 <"INC", 1>;
313 defm atomic_dec : SIAtomicM0Glue2 <"DEC", 1>;
314 defm atomic_load_and : SIAtomicM0Glue2 <"LOAD_AND">;
315 defm atomic_load_min : SIAtomicM0Glue2 <"LOAD_MIN">;
316 defm atomic_load_max : SIAtomicM0Glue2 <"LOAD_MAX">;
317 defm atomic_load_or : SIAtomicM0Glue2 <"LOAD_OR">;
318 defm atomic_load_xor : SIAtomicM0Glue2 <"LOAD_XOR">;
319 defm atomic_load_umin : SIAtomicM0Glue2 <"LOAD_UMIN">;
320 defm atomic_load_umax : SIAtomicM0Glue2 <"LOAD_UMAX">;
321 defm atomic_swap : SIAtomicM0Glue2 <"SWAP">;
323 def atomic_cmp_swap_glue : SDNode <"ISD::ATOMIC_CMP_SWAP", SDTAtomic3,
324 [SDNPHasChain, SDNPMayStore, SDNPMayLoad, SDNPMemOperand, SDNPInGlue]
327 def atomic_cmp_swap_local_m0 : AtomicCmpSwapLocal<atomic_cmp_swap_glue>;
330 def as_i1imm : SDNodeXForm<imm, [{
331 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i1);
334 def as_i8imm : SDNodeXForm<imm, [{
335 return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i8);
338 def as_i16imm : SDNodeXForm<imm, [{
339 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i16);
342 def as_i32imm: SDNodeXForm<imm, [{
343 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i32);
346 def as_i64imm: SDNodeXForm<imm, [{
347 return CurDAG->getTargetConstant(N->getSExtValue(), SDLoc(N), MVT::i64);
350 def cond_as_i32imm: SDNodeXForm<cond, [{
351 return CurDAG->getTargetConstant(N->get(), SDLoc(N), MVT::i32);
354 // Copied from the AArch64 backend:
355 def bitcast_fpimm_to_i32 : SDNodeXForm<fpimm, [{
356 return CurDAG->getTargetConstant(
357 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i32);
360 def frameindex_to_targetframeindex : SDNodeXForm<frameindex, [{
361 auto FI = cast<FrameIndexSDNode>(N);
362 return CurDAG->getTargetFrameIndex(FI->getIndex(), MVT::i32);
365 // Copied from the AArch64 backend:
366 def bitcast_fpimm_to_i64 : SDNodeXForm<fpimm, [{
367 return CurDAG->getTargetConstant(
368 N->getValueAPF().bitcastToAPInt().getZExtValue(), SDLoc(N), MVT::i64);
371 def SIMM16bit : PatLeaf <(imm),
372 [{return isInt<16>(N->getSExtValue());}]
375 class InlineImm <ValueType vt> : PatLeaf <(vt imm), [{
376 return isInlineImmediate(N);
379 class InlineFPImm <ValueType vt> : PatLeaf <(vt fpimm), [{
380 return isInlineImmediate(N);
383 class VGPRImm <dag frag> : PatLeaf<frag, [{
384 if (Subtarget->getGeneration() < SISubtarget::SOUTHERN_ISLANDS) {
387 const SIRegisterInfo *SIRI =
388 static_cast<const SIRegisterInfo *>(Subtarget->getRegisterInfo());
390 for (SDNode::use_iterator U = N->use_begin(), E = SDNode::use_end();
391 Limit < 10 && U != E; ++U, ++Limit) {
392 const TargetRegisterClass *RC = getOperandRegClass(*U, U.getOperandNo());
394 // If the register class is unknown, it could be an unknown
395 // register class that needs to be an SGPR, e.g. an inline asm
397 if (!RC || SIRI->isSGPRClass(RC))
404 def NegateImm : SDNodeXForm<imm, [{
405 return CurDAG->getConstant(-N->getSExtValue(), SDLoc(N), MVT::i32);
408 // TODO: When FP inline imm values work?
409 def NegSubInlineConst32 : ImmLeaf<i32, [{
410 return Imm < -16 && Imm >= -64;
413 def NegSubInlineConst16 : ImmLeaf<i16, [{
414 return Imm < -16 && Imm >= -64;
417 def ShiftAmt32Imm : PatLeaf <(imm), [{
418 return N->getZExtValue() < 32;
421 //===----------------------------------------------------------------------===//
423 //===----------------------------------------------------------------------===//
425 def SoppBrTarget : AsmOperandClass {
426 let Name = "SoppBrTarget";
427 let ParserMethod = "parseSOppBrTarget";
430 def sopp_brtarget : Operand<OtherVT> {
431 let EncoderMethod = "getSOPPBrEncoding";
432 let DecoderMethod = "decodeSoppBrTarget";
433 let OperandType = "OPERAND_PCREL";
434 let ParserMatchClass = SoppBrTarget;
437 def si_ga : Operand<iPTR>;
439 def InterpSlotMatchClass : AsmOperandClass {
440 let Name = "InterpSlot";
441 let PredicateMethod = "isInterpSlot";
442 let ParserMethod = "parseInterpSlot";
443 let RenderMethod = "addImmOperands";
446 def InterpSlot : Operand<i32> {
447 let PrintMethod = "printInterpSlot";
448 let ParserMatchClass = InterpSlotMatchClass;
449 let OperandType = "OPERAND_IMMEDIATE";
452 def AttrMatchClass : AsmOperandClass {
454 let PredicateMethod = "isInterpAttr";
455 let ParserMethod = "parseInterpAttr";
456 let RenderMethod = "addImmOperands";
459 // It appears to be necessary to create a separate operand for this to
460 // be able to parse attr<num> with no space.
461 def Attr : Operand<i32> {
462 let PrintMethod = "printInterpAttr";
463 let ParserMatchClass = AttrMatchClass;
464 let OperandType = "OPERAND_IMMEDIATE";
467 def AttrChanMatchClass : AsmOperandClass {
468 let Name = "AttrChan";
469 let PredicateMethod = "isAttrChan";
470 let RenderMethod = "addImmOperands";
473 def AttrChan : Operand<i32> {
474 let PrintMethod = "printInterpAttrChan";
475 let ParserMatchClass = AttrChanMatchClass;
476 let OperandType = "OPERAND_IMMEDIATE";
479 def SendMsgMatchClass : AsmOperandClass {
480 let Name = "SendMsg";
481 let PredicateMethod = "isSendMsg";
482 let ParserMethod = "parseSendMsgOp";
483 let RenderMethod = "addImmOperands";
486 def SwizzleMatchClass : AsmOperandClass {
487 let Name = "Swizzle";
488 let PredicateMethod = "isSwizzle";
489 let ParserMethod = "parseSwizzleOp";
490 let RenderMethod = "addImmOperands";
494 def ExpTgtMatchClass : AsmOperandClass {
496 let PredicateMethod = "isExpTgt";
497 let ParserMethod = "parseExpTgt";
498 let RenderMethod = "printExpTgt";
501 def SendMsgImm : Operand<i32> {
502 let PrintMethod = "printSendMsg";
503 let ParserMatchClass = SendMsgMatchClass;
506 def SwizzleImm : Operand<i16> {
507 let PrintMethod = "printSwizzle";
508 let ParserMatchClass = SwizzleMatchClass;
511 def SWaitMatchClass : AsmOperandClass {
512 let Name = "SWaitCnt";
513 let RenderMethod = "addImmOperands";
514 let ParserMethod = "parseSWaitCntOps";
517 def VReg32OrOffClass : AsmOperandClass {
518 let Name = "VReg32OrOff";
519 let ParserMethod = "parseVReg32OrOff";
522 def WAIT_FLAG : Operand <i32> {
523 let ParserMatchClass = SWaitMatchClass;
524 let PrintMethod = "printWaitFlag";
527 include "SIInstrFormats.td"
528 include "VIInstrFormats.td"
530 // ===----------------------------------------------------------------------===//
531 // ExpSrc* Special cases for exp src operands which are printed as
532 // "off" depending on en operand.
533 // ===----------------------------------------------------------------------===//
535 def ExpSrc0 : RegisterOperand<VGPR_32> {
536 let PrintMethod = "printExpSrc0";
537 let ParserMatchClass = VReg32OrOffClass;
540 def ExpSrc1 : RegisterOperand<VGPR_32> {
541 let PrintMethod = "printExpSrc1";
542 let ParserMatchClass = VReg32OrOffClass;
545 def ExpSrc2 : RegisterOperand<VGPR_32> {
546 let PrintMethod = "printExpSrc2";
547 let ParserMatchClass = VReg32OrOffClass;
550 def ExpSrc3 : RegisterOperand<VGPR_32> {
551 let PrintMethod = "printExpSrc3";
552 let ParserMatchClass = VReg32OrOffClass;
555 class SDWASrc : RegisterOperand<VS_32> {
556 let OperandNamespace = "AMDGPU";
557 let OperandType = "OPERAND_SDWA_SRC";
558 let EncoderMethod = "getSDWASrcEncoding";
561 def SDWASrc32 : SDWASrc {
562 let DecoderMethod = "decodeSDWASrc32";
565 def SDWASrc16 : SDWASrc {
566 let DecoderMethod = "decodeSDWASrc16";
569 def SDWAVopcDst : VOPDstOperand<SReg_64> {
570 let OperandNamespace = "AMDGPU";
571 let OperandType = "OPERAND_SDWA_VOPC_DST";
572 let EncoderMethod = "getSDWAVopcDstEncoding";
573 let DecoderMethod = "decodeSDWAVopcDst";
576 class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
577 let Name = "Imm"#CName;
578 let PredicateMethod = "is"#CName;
579 let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName);
580 let RenderMethod = "addImmOperands";
581 let IsOptional = Optional;
582 let DefaultMethod = !if(Optional, "default"#CName, ?);
585 class NamedOperandBit<string Name, AsmOperandClass MatchClass> : Operand<i1> {
586 let PrintMethod = "print"#Name;
587 let ParserMatchClass = MatchClass;
590 class NamedOperandU8<string Name, AsmOperandClass MatchClass> : Operand<i8> {
591 let PrintMethod = "print"#Name;
592 let ParserMatchClass = MatchClass;
595 class NamedOperandU12<string Name, AsmOperandClass MatchClass> : Operand<i16> {
596 let PrintMethod = "print"#Name;
597 let ParserMatchClass = MatchClass;
600 class NamedOperandU16<string Name, AsmOperandClass MatchClass> : Operand<i16> {
601 let PrintMethod = "print"#Name;
602 let ParserMatchClass = MatchClass;
605 class NamedOperandS13<string Name, AsmOperandClass MatchClass> : Operand<i16> {
606 let PrintMethod = "print"#Name;
607 let ParserMatchClass = MatchClass;
610 class NamedOperandU32<string Name, AsmOperandClass MatchClass> : Operand<i32> {
611 let PrintMethod = "print"#Name;
612 let ParserMatchClass = MatchClass;
615 class NamedOperandU32Default0<string Name, AsmOperandClass MatchClass> :
616 OperandWithDefaultOps<i32, (ops (i32 0))> {
617 let PrintMethod = "print"#Name;
618 let ParserMatchClass = MatchClass;
621 let OperandType = "OPERAND_IMMEDIATE" in {
623 def offen : NamedOperandBit<"Offen", NamedMatchClass<"Offen">>;
624 def idxen : NamedOperandBit<"Idxen", NamedMatchClass<"Idxen">>;
625 def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
627 def offset_u12 : NamedOperandU12<"Offset", NamedMatchClass<"OffsetU12">>;
628 def offset_s13 : NamedOperandS13<"OffsetS13", NamedMatchClass<"OffsetS13">>;
629 def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
630 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
631 def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
633 def gds : NamedOperandBit<"GDS", NamedMatchClass<"GDS">>;
635 def omod : NamedOperandU32<"OModSI", NamedMatchClass<"OModSI">>;
636 def clampmod : NamedOperandBit<"ClampSI", NamedMatchClass<"ClampSI">>;
637 def highmod : NamedOperandBit<"High", NamedMatchClass<"High">>;
639 def GLC : NamedOperandBit<"GLC", NamedMatchClass<"GLC">>;
640 def slc : NamedOperandBit<"SLC", NamedMatchClass<"SLC">>;
641 def tfe : NamedOperandBit<"TFE", NamedMatchClass<"TFE">>;
642 def unorm : NamedOperandBit<"UNorm", NamedMatchClass<"UNorm">>;
643 def da : NamedOperandBit<"DA", NamedMatchClass<"DA">>;
644 def r128 : NamedOperandBit<"R128", NamedMatchClass<"R128">>;
645 def lwe : NamedOperandBit<"LWE", NamedMatchClass<"LWE">>;
646 def exp_compr : NamedOperandBit<"ExpCompr", NamedMatchClass<"ExpCompr">>;
647 def exp_vm : NamedOperandBit<"ExpVM", NamedMatchClass<"ExpVM">>;
649 def DFMT : NamedOperandU8<"DFMT", NamedMatchClass<"DFMT">>;
650 def NFMT : NamedOperandU8<"NFMT", NamedMatchClass<"NFMT">>;
652 def dmask : NamedOperandU16<"DMask", NamedMatchClass<"DMask">>;
654 def dpp_ctrl : NamedOperandU32<"DPPCtrl", NamedMatchClass<"DPPCtrl", 0>>;
655 def row_mask : NamedOperandU32<"RowMask", NamedMatchClass<"RowMask">>;
656 def bank_mask : NamedOperandU32<"BankMask", NamedMatchClass<"BankMask">>;
657 def bound_ctrl : NamedOperandBit<"BoundCtrl", NamedMatchClass<"BoundCtrl">>;
659 def dst_sel : NamedOperandU32<"SDWADstSel", NamedMatchClass<"SDWADstSel">>;
660 def src0_sel : NamedOperandU32<"SDWASrc0Sel", NamedMatchClass<"SDWASrc0Sel">>;
661 def src1_sel : NamedOperandU32<"SDWASrc1Sel", NamedMatchClass<"SDWASrc1Sel">>;
662 def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
664 def op_sel : NamedOperandU32Default0<"OpSel", NamedMatchClass<"OpSel">>;
665 def op_sel_hi : NamedOperandU32Default0<"OpSelHi", NamedMatchClass<"OpSelHi">>;
666 def neg_lo : NamedOperandU32Default0<"NegLo", NamedMatchClass<"NegLo">>;
667 def neg_hi : NamedOperandU32Default0<"NegHi", NamedMatchClass<"NegHi">>;
669 def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
671 def exp_tgt : NamedOperandU8<"ExpTgt", NamedMatchClass<"ExpTgt", 0>> {
675 } // End OperandType = "OPERAND_IMMEDIATE"
677 class KImmMatchClass<int size> : AsmOperandClass {
678 let Name = "KImmFP"#size;
679 let PredicateMethod = "isKImmFP"#size;
680 let ParserMethod = "parseImm";
681 let RenderMethod = "addKImmFP"#size#"Operands";
684 class kimmOperand<ValueType vt> : Operand<vt> {
685 let OperandNamespace = "AMDGPU";
686 let OperandType = "OPERAND_KIMM"#vt.Size;
687 let PrintMethod = "printU"#vt.Size#"ImmOperand";
688 let ParserMatchClass = !cast<AsmOperandClass>("KImmFP"#vt.Size#"MatchClass");
691 // 32-bit VALU immediate operand that uses the constant bus.
692 def KImmFP32MatchClass : KImmMatchClass<32>;
693 def f32kimm : kimmOperand<i32>;
695 // 32-bit VALU immediate operand with a 16-bit value that uses the
697 def KImmFP16MatchClass : KImmMatchClass<16>;
698 def f16kimm : kimmOperand<i16>;
701 def VOPDstS64 : VOPDstOperand <SReg_64>;
703 class FPInputModsMatchClass <int opSize> : AsmOperandClass {
704 let Name = "RegOrImmWithFP"#opSize#"InputMods";
705 let ParserMethod = "parseRegOrImmWithFPInputMods";
706 let PredicateMethod = "isRegOrImmWithFP"#opSize#"InputMods";
709 def FP16InputModsMatchClass : FPInputModsMatchClass<16>;
710 def FP32InputModsMatchClass : FPInputModsMatchClass<32>;
711 def FP64InputModsMatchClass : FPInputModsMatchClass<64>;
713 class InputMods <AsmOperandClass matchClass> : Operand <i32> {
714 let OperandNamespace = "AMDGPU";
715 let OperandType = "OPERAND_INPUT_MODS";
716 let ParserMatchClass = matchClass;
719 class FPInputMods <FPInputModsMatchClass matchClass> : InputMods <matchClass> {
720 let PrintMethod = "printOperandAndFPInputMods";
723 def FP16InputMods : FPInputMods<FP16InputModsMatchClass>;
724 def FP32InputMods : FPInputMods<FP32InputModsMatchClass>;
725 def FP64InputMods : FPInputMods<FP64InputModsMatchClass>;
727 class IntInputModsMatchClass <int opSize> : AsmOperandClass {
728 let Name = "RegOrImmWithInt"#opSize#"InputMods";
729 let ParserMethod = "parseRegOrImmWithIntInputMods";
730 let PredicateMethod = "isRegOrImmWithInt"#opSize#"InputMods";
732 def Int32InputModsMatchClass : IntInputModsMatchClass<32>;
733 def Int64InputModsMatchClass : IntInputModsMatchClass<64>;
735 class IntInputMods <IntInputModsMatchClass matchClass> : InputMods <matchClass> {
736 let PrintMethod = "printOperandAndIntInputMods";
738 def Int32InputMods : IntInputMods<Int32InputModsMatchClass>;
739 def Int64InputMods : IntInputMods<Int64InputModsMatchClass>;
741 class OpSelModsMatchClass : AsmOperandClass {
742 let Name = "OpSelMods";
743 let ParserMethod = "parseRegOrImm";
744 let PredicateMethod = "isRegOrImm";
747 def IntOpSelModsMatchClass : OpSelModsMatchClass;
748 def IntOpSelMods : InputMods<IntOpSelModsMatchClass>;
750 def FPRegSDWAInputModsMatchClass : AsmOperandClass {
751 let Name = "SDWARegWithFPInputMods";
752 let ParserMethod = "parseRegWithFPInputMods";
753 let PredicateMethod = "isSDWARegKind";
756 def FPRegSDWAInputMods : InputMods <FPRegSDWAInputModsMatchClass> {
757 let PrintMethod = "printOperandAndFPInputMods";
760 def FPVRegInputModsMatchClass : AsmOperandClass {
761 let Name = "VRegWithFPInputMods";
762 let ParserMethod = "parseRegWithFPInputMods";
763 let PredicateMethod = "isVReg";
766 def FPVRegInputMods : InputMods <FPVRegInputModsMatchClass> {
767 let PrintMethod = "printOperandAndFPInputMods";
771 def IntRegSDWAInputModsMatchClass : AsmOperandClass {
772 let Name = "SDWARegWithIntInputMods";
773 let ParserMethod = "parseRegWithIntInputMods";
774 let PredicateMethod = "isSDWARegKind";
777 def IntRegSDWAInputMods : InputMods <IntRegSDWAInputModsMatchClass> {
778 let PrintMethod = "printOperandAndIntInputMods";
781 def IntVRegInputModsMatchClass : AsmOperandClass {
782 let Name = "VRegWithIntInputMods";
783 let ParserMethod = "parseRegWithIntInputMods";
784 let PredicateMethod = "isVReg";
787 def IntVRegInputMods : InputMods <IntVRegInputModsMatchClass> {
788 let PrintMethod = "printOperandAndIntInputMods";
791 class PackedFPInputModsMatchClass <int opSize> : AsmOperandClass {
792 let Name = "PackedFP"#opSize#"InputMods";
793 let ParserMethod = "parseRegOrImm";
794 let PredicateMethod = "isRegOrImm";
795 // let PredicateMethod = "isPackedFP"#opSize#"InputMods";
798 class PackedIntInputModsMatchClass <int opSize> : AsmOperandClass {
799 let Name = "PackedInt"#opSize#"InputMods";
800 let ParserMethod = "parseRegOrImm";
801 let PredicateMethod = "isRegOrImm";
802 // let PredicateMethod = "isPackedInt"#opSize#"InputMods";
805 def PackedF16InputModsMatchClass : PackedFPInputModsMatchClass<16>;
806 def PackedI16InputModsMatchClass : PackedIntInputModsMatchClass<16>;
808 class PackedFPInputMods <PackedFPInputModsMatchClass matchClass> : InputMods <matchClass> {
809 // let PrintMethod = "printPackedFPInputMods";
812 class PackedIntInputMods <PackedIntInputModsMatchClass matchClass> : InputMods <matchClass> {
813 //let PrintMethod = "printPackedIntInputMods";
816 def PackedF16InputMods : PackedFPInputMods<PackedF16InputModsMatchClass>;
817 def PackedI16InputMods : PackedIntInputMods<PackedI16InputModsMatchClass>;
819 //===----------------------------------------------------------------------===//
821 //===----------------------------------------------------------------------===//
823 def DS1Addr1Offset : ComplexPattern<i32, 2, "SelectDS1Addr1Offset">;
824 def DS64Bit4ByteAligned : ComplexPattern<i32, 3, "SelectDS64Bit4ByteAligned">;
826 def MOVRELOffset : ComplexPattern<i32, 2, "SelectMOVRELOffset">;
828 def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
829 def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
830 def VOP3Mods0Clamp0OMod : ComplexPattern<untyped, 4, "SelectVOP3Mods0Clamp0OMod">;
831 def VOP3Mods : ComplexPattern<untyped, 2, "SelectVOP3Mods">;
832 def VOP3NoMods : ComplexPattern<untyped, 1, "SelectVOP3NoMods">;
833 // VOP3Mods, but the input source is known to never be NaN.
834 def VOP3Mods_nnan : ComplexPattern<fAny, 2, "SelectVOP3Mods_NNaN">;
836 def VOP3OMods : ComplexPattern<untyped, 3, "SelectVOP3OMods">;
838 def VOP3PMods : ComplexPattern<untyped, 2, "SelectVOP3PMods">;
839 def VOP3PMods0 : ComplexPattern<untyped, 3, "SelectVOP3PMods0">;
841 def VOP3OpSel : ComplexPattern<untyped, 2, "SelectVOP3OpSel">;
842 def VOP3OpSel0 : ComplexPattern<untyped, 3, "SelectVOP3OpSel0">;
844 def VOP3OpSelMods : ComplexPattern<untyped, 2, "SelectVOP3OpSelMods">;
845 def VOP3OpSelMods0 : ComplexPattern<untyped, 3, "SelectVOP3OpSelMods0">;
847 def VOP3PMadMixMods : ComplexPattern<untyped, 2, "SelectVOP3PMadMixMods">;
850 def Hi16Elt : ComplexPattern<untyped, 1, "SelectHi16Elt">;
852 //===----------------------------------------------------------------------===//
853 // SI assembler operands
854 //===----------------------------------------------------------------------===//
862 // This should be kept in sync with SISrcMods enum
886 int LLVM_DEBUG_TRAP = 3;
889 //===----------------------------------------------------------------------===//
891 // SI Instruction multiclass helpers.
893 // Instructions with _32 take 32-bit operands.
894 // Instructions with _64 take 64-bit operands.
896 // VOP_* instructions can use either a 32-bit or 64-bit encoding. The 32-bit
897 // encoding is the standard encoding, but instruction that make use of
898 // any of the instruction modifiers must use the 64-bit encoding.
900 // Instructions with _e32 use the 32-bit encoding.
901 // Instructions with _e64 use the 64-bit encoding.
903 //===----------------------------------------------------------------------===//
905 class SIMCInstr <string pseudo, int subtarget> {
906 string PseudoInstr = pseudo;
907 int Subtarget = subtarget;
910 //===----------------------------------------------------------------------===//
912 //===----------------------------------------------------------------------===//
914 class EXP_Helper<bit done, SDPatternOperator node = null_frag> : EXPCommon<
917 ExpSrc0:$src0, ExpSrc1:$src1, ExpSrc2:$src2, ExpSrc3:$src3,
918 exp_vm:$vm, exp_compr:$compr, i8imm:$en),
919 "exp$tgt $src0, $src1, $src2, $src3"#!if(done, " done", "")#"$compr$vm",
920 [(node (i8 timm:$tgt), (i8 timm:$en),
921 f32:$src0, f32:$src1, f32:$src2, f32:$src3,
922 (i1 timm:$compr), (i1 timm:$vm))]> {
923 let AsmMatchConverter = "cvtExp";
926 // Split EXP instruction into EXP and EXP_DONE so we can set
927 // mayLoad for done=1.
928 multiclass EXP_m<bit done, SDPatternOperator node> {
929 let mayLoad = done, DisableWQM = 1 in {
930 let isPseudo = 1, isCodeGenOnly = 1 in {
931 def "" : EXP_Helper<done, node>,
932 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.NONE>;
936 def _si : EXP_Helper<done>,
937 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.SI>,
939 let AssemblerPredicates = [isSICI];
940 let DecoderNamespace = "SICI";
941 let DisableDecoder = DisableSIDecoder;
944 def _vi : EXP_Helper<done>,
945 SIMCInstr <"exp"#!if(done, "_done", ""), SIEncodingFamily.VI>,
947 let AssemblerPredicates = [isVI];
948 let DecoderNamespace = "VI";
949 let DisableDecoder = DisableVIDecoder;
955 //===----------------------------------------------------------------------===//
956 // Vector ALU classes
957 //===----------------------------------------------------------------------===//
959 class getNumSrcArgs<ValueType Src0, ValueType Src1, ValueType Src2> {
961 !if (!eq(Src0.Value, untyped.Value), 0,
962 !if (!eq(Src1.Value, untyped.Value), 1, // VOP1
963 !if (!eq(Src2.Value, untyped.Value), 2, // VOP2
967 // Returns the register class to use for the destination of VOP[123C]
968 // instructions for the given VT.
969 class getVALUDstForVT<ValueType VT> {
970 RegisterOperand ret = !if(!eq(VT.Size, 32), VOPDstOperand<VGPR_32>,
971 !if(!eq(VT.Size, 128), VOPDstOperand<VReg_128>,
972 !if(!eq(VT.Size, 64), VOPDstOperand<VReg_64>,
973 !if(!eq(VT.Size, 16), VOPDstOperand<VGPR_32>,
974 VOPDstOperand<SReg_64>)))); // else VT == i1
977 // Returns the register class to use for the destination of VOP[12C]
978 // instructions with SDWA extension
979 class getSDWADstForVT<ValueType VT> {
980 RegisterOperand ret = !if(!eq(VT.Size, 1),
982 VOPDstOperand<VGPR_32>); // VOP1/2 32-bit dst
985 // Returns the register class to use for source 0 of VOP[12C]
986 // instructions for the given VT.
987 class getVOPSrc0ForVT<ValueType VT> {
988 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
989 !if(!eq(VT.Value, v2f16.Value), 1,
990 !if(!eq(VT.Value, f32.Value), 1,
991 !if(!eq(VT.Value, f64.Value), 1,
994 RegisterOperand ret =
996 !if(!eq(VT.Size, 64),
998 !if(!eq(VT.Value, f16.Value),
1000 !if(!eq(VT.Value, v2f16.Value),
1006 !if(!eq(VT.Size, 64),
1008 !if(!eq(VT.Value, i16.Value),
1010 !if(!eq(VT.Value, v2i16.Value),
1019 // Returns the vreg register class to use for source operand given VT
1020 class getVregSrcForVT<ValueType VT> {
1021 RegisterClass ret = !if(!eq(VT.Size, 128), VReg_128,
1022 !if(!eq(VT.Size, 64), VReg_64, VGPR_32));
1025 class getSDWASrcForVT <ValueType VT> {
1026 RegisterOperand ret = !if(!eq(VT.Size, 16), SDWASrc16, SDWASrc32);
1029 // Returns the register class to use for sources of VOP3 instructions for the
1031 class getVOP3SrcForVT<ValueType VT> {
1032 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
1033 !if(!eq(VT.Value, v2f16.Value), 1,
1034 !if(!eq(VT.Value, f32.Value), 1,
1035 !if(!eq(VT.Value, f64.Value), 1,
1037 RegisterOperand ret =
1038 !if(!eq(VT.Size, 128),
1040 !if(!eq(VT.Size, 64),
1044 !if(!eq(VT.Value, i1.Value),
1047 !if(!eq(VT.Value, f16.Value),
1049 !if(!eq(VT.Value, v2f16.Value),
1054 !if(!eq(VT.Value, i16.Value),
1056 !if(!eq(VT.Value, v2i16.Value),
1067 // Returns 1 if the source arguments have modifiers, 0 if they do not.
1068 // XXX - do f16 instructions?
1069 class isFloatType<ValueType SrcVT> {
1071 !if(!eq(SrcVT.Value, f16.Value), 1,
1072 !if(!eq(SrcVT.Value, f32.Value), 1,
1073 !if(!eq(SrcVT.Value, f64.Value), 1,
1074 !if(!eq(SrcVT.Value, v2f16.Value), 1,
1078 class isIntType<ValueType SrcVT> {
1080 !if(!eq(SrcVT.Value, i16.Value), 1,
1081 !if(!eq(SrcVT.Value, i32.Value), 1,
1082 !if(!eq(SrcVT.Value, i64.Value), 1,
1086 class isPackedType<ValueType SrcVT> {
1088 !if(!eq(SrcVT.Value, v2i16.Value), 1,
1089 !if(!eq(SrcVT.Value, v2f16.Value), 1, 0)
1093 // Float or packed int
1094 class isModifierType<ValueType SrcVT> {
1096 !if(!eq(SrcVT.Value, f16.Value), 1,
1097 !if(!eq(SrcVT.Value, f32.Value), 1,
1098 !if(!eq(SrcVT.Value, f64.Value), 1,
1099 !if(!eq(SrcVT.Value, v2f16.Value), 1,
1100 !if(!eq(SrcVT.Value, v2i16.Value), 1,
1104 // Return type of input modifiers operand for specified input operand
1105 class getSrcMod <ValueType VT> {
1106 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
1107 !if(!eq(VT.Value, f32.Value), 1,
1108 !if(!eq(VT.Value, f64.Value), 1,
1110 bit isPacked = isPackedType<VT>.ret;
1111 Operand ret = !if(!eq(VT.Size, 64),
1112 !if(isFP, FP64InputMods, Int64InputMods),
1114 !if(!eq(VT.Value, f16.Value),
1122 class getOpSelMod <ValueType VT> {
1123 Operand ret = !if(!eq(VT.Value, f16.Value), FP16InputMods, IntOpSelMods);
1126 // Return type of input modifiers operand specified input operand for DPP
1127 class getSrcModExt <ValueType VT> {
1128 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
1129 !if(!eq(VT.Value, f32.Value), 1,
1130 !if(!eq(VT.Value, f64.Value), 1,
1132 Operand ret = !if(isFP, FPVRegInputMods, IntVRegInputMods);
1135 // Return type of input modifiers operand specified input operand for SDWA
1136 class getSrcModSDWA <ValueType VT> {
1137 bit isFP = !if(!eq(VT.Value, f16.Value), 1,
1138 !if(!eq(VT.Value, f32.Value), 1,
1139 !if(!eq(VT.Value, f64.Value), 1,
1141 Operand ret = !if(isFP, FPRegSDWAInputMods, IntRegSDWAInputMods);
1144 // Returns the input arguments for VOP[12C] instructions for the given SrcVT.
1145 class getIns32 <RegisterOperand Src0RC, RegisterClass Src1RC, int NumSrcArgs> {
1146 dag ret = !if(!eq(NumSrcArgs, 1), (ins Src0RC:$src0), // VOP1
1147 !if(!eq(NumSrcArgs, 2), (ins Src0RC:$src0, Src1RC:$src1), // VOP2
1151 // Returns the input arguments for VOP3 instructions for the given SrcVT.
1152 class getIns64 <RegisterOperand Src0RC, RegisterOperand Src1RC,
1153 RegisterOperand Src2RC, int NumSrcArgs,
1154 bit HasIntClamp, bit HasModifiers, bit HasOMod,
1155 Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1158 !if (!eq(NumSrcArgs, 0),
1159 // VOP1 without input operands (V_NOP, V_CLREXCP)
1162 !if (!eq(NumSrcArgs, 1),
1163 !if (!eq(HasModifiers, 1),
1164 // VOP1 with modifiers
1165 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1166 clampmod:$clamp, omod:$omod)
1168 // VOP1 without modifiers
1169 !if (!eq(HasIntClamp, 1),
1170 (ins Src0RC:$src0, clampmod:$clamp),
1173 !if (!eq(NumSrcArgs, 2),
1174 !if (!eq(HasModifiers, 1),
1175 // VOP 2 with modifiers
1176 !if( !eq(HasOMod, 1),
1177 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1178 Src1Mod:$src1_modifiers, Src1RC:$src1,
1179 clampmod:$clamp, omod:$omod),
1180 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1181 Src1Mod:$src1_modifiers, Src1RC:$src1,
1184 // VOP2 without modifiers
1185 !if (!eq(HasIntClamp, 1),
1186 (ins Src0RC:$src0, Src1RC:$src1, clampmod:$clamp),
1187 (ins Src0RC:$src0, Src1RC:$src1))
1190 /* NumSrcArgs == 3 */,
1191 !if (!eq(HasModifiers, 1),
1192 // VOP3 with modifiers
1193 !if (!eq(HasOMod, 1),
1194 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1195 Src1Mod:$src1_modifiers, Src1RC:$src1,
1196 Src2Mod:$src2_modifiers, Src2RC:$src2,
1197 clampmod:$clamp, omod:$omod),
1198 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1199 Src1Mod:$src1_modifiers, Src1RC:$src1,
1200 Src2Mod:$src2_modifiers, Src2RC:$src2,
1203 // VOP3 without modifiers
1204 !if (!eq(HasIntClamp, 1),
1205 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2, clampmod:$clamp),
1206 (ins Src0RC:$src0, Src1RC:$src1, Src2RC:$src2))
1210 /// XXX - src1 may only allow VGPRs?
1212 // The modifiers (except clamp) are dummy operands for the benefit of
1213 // printing and parsing. They defer their values to looking at the
1214 // srcN_modifiers for what to print.
1215 class getInsVOP3P <RegisterOperand Src0RC, RegisterOperand Src1RC,
1216 RegisterOperand Src2RC, int NumSrcArgs,
1218 Operand Src0Mod, Operand Src1Mod, Operand Src2Mod> {
1219 dag ret = !if (!eq(NumSrcArgs, 2),
1221 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1222 Src1Mod:$src1_modifiers, Src1RC:$src1,
1224 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1225 neg_lo:$neg_lo, neg_hi:$neg_hi),
1226 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1227 Src1Mod:$src1_modifiers, Src1RC:$src1,
1228 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1229 neg_lo:$neg_lo, neg_hi:$neg_hi)),
1230 // else NumSrcArgs == 3
1232 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1233 Src1Mod:$src1_modifiers, Src1RC:$src1,
1234 Src2Mod:$src2_modifiers, Src2RC:$src2,
1236 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1237 neg_lo:$neg_lo, neg_hi:$neg_hi),
1238 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1239 Src1Mod:$src1_modifiers, Src1RC:$src1,
1240 Src2Mod:$src2_modifiers, Src2RC:$src2,
1241 op_sel:$op_sel, op_sel_hi:$op_sel_hi,
1242 neg_lo:$neg_lo, neg_hi:$neg_hi))
1246 class getInsVOP3OpSel <RegisterOperand Src0RC,
1247 RegisterOperand Src1RC,
1248 RegisterOperand Src2RC,
1254 dag ret = !if (!eq(NumSrcArgs, 2),
1256 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1257 Src1Mod:$src1_modifiers, Src1RC:$src1,
1260 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1261 Src1Mod:$src1_modifiers, Src1RC:$src1,
1263 // else NumSrcArgs == 3
1265 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1266 Src1Mod:$src1_modifiers, Src1RC:$src1,
1267 Src2Mod:$src2_modifiers, Src2RC:$src2,
1270 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1271 Src1Mod:$src1_modifiers, Src1RC:$src1,
1272 Src2Mod:$src2_modifiers, Src2RC:$src2,
1277 class getInsDPP <RegisterOperand DstRC, RegisterClass Src0RC, RegisterClass Src1RC,
1278 int NumSrcArgs, bit HasModifiers,
1279 Operand Src0Mod, Operand Src1Mod> {
1281 dag ret = !if (!eq(NumSrcArgs, 0),
1282 // VOP1 without input operands (V_NOP)
1283 (ins dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1284 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl),
1285 !if (!eq(NumSrcArgs, 1),
1286 !if (!eq(HasModifiers, 1),
1287 // VOP1_DPP with modifiers
1288 (ins DstRC:$old, Src0Mod:$src0_modifiers,
1289 Src0RC:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1290 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1292 // VOP1_DPP without modifiers
1293 (ins DstRC:$old, Src0RC:$src0,
1294 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1295 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1297 /* NumSrcArgs == 2 */,
1298 !if (!eq(HasModifiers, 1),
1299 // VOP2_DPP with modifiers
1301 Src0Mod:$src0_modifiers, Src0RC:$src0,
1302 Src1Mod:$src1_modifiers, Src1RC:$src1,
1303 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
1304 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl)
1306 // VOP2_DPP without modifiers
1308 Src0RC:$src0, Src1RC:$src1, dpp_ctrl:$dpp_ctrl,
1309 row_mask:$row_mask, bank_mask:$bank_mask,
1310 bound_ctrl:$bound_ctrl)
1317 class getInsSDWA <RegisterOperand Src0RC, RegisterOperand Src1RC, int NumSrcArgs,
1318 bit HasSDWAOMod, Operand Src0Mod, Operand Src1Mod,
1321 dag ret = !if(!eq(NumSrcArgs, 0),
1322 // VOP1 without input operands (V_NOP)
1324 !if(!eq(NumSrcArgs, 1),
1326 !if(!eq(HasSDWAOMod, 0),
1327 // VOP1_SDWA without omod
1328 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1330 dst_sel:$dst_sel, dst_unused:$dst_unused,
1331 src0_sel:$src0_sel),
1332 // VOP1_SDWA with omod
1333 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1334 clampmod:$clamp, omod:$omod,
1335 dst_sel:$dst_sel, dst_unused:$dst_unused,
1336 src0_sel:$src0_sel)),
1337 !if(!eq(NumSrcArgs, 2),
1338 !if(!eq(DstVT.Size, 1),
1340 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1341 Src1Mod:$src1_modifiers, Src1RC:$src1,
1342 clampmod:$clamp, src0_sel:$src0_sel, src1_sel:$src1_sel),
1344 !if(!eq(HasSDWAOMod, 0),
1345 // VOP2_SDWA without omod
1346 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1347 Src1Mod:$src1_modifiers, Src1RC:$src1,
1349 dst_sel:$dst_sel, dst_unused:$dst_unused,
1350 src0_sel:$src0_sel, src1_sel:$src1_sel),
1351 // VOP2_SDWA with omod
1352 (ins Src0Mod:$src0_modifiers, Src0RC:$src0,
1353 Src1Mod:$src1_modifiers, Src1RC:$src1,
1354 clampmod:$clamp, omod:$omod,
1355 dst_sel:$dst_sel, dst_unused:$dst_unused,
1356 src0_sel:$src0_sel, src1_sel:$src1_sel))),
1357 (ins)/* endif */)));
1360 // Outs for DPP and SDWA
1361 class getOutsExt <bit HasDst, ValueType DstVT, RegisterOperand DstRCExt> {
1362 dag ret = !if(HasDst,
1363 !if(!eq(DstVT.Size, 1),
1364 (outs), // no dst for VOPC, we use "vcc"-token as dst in SDWA VOPC instructions
1365 (outs DstRCExt:$vdst)),
1370 class getOutsSDWA <bit HasDst, ValueType DstVT, RegisterOperand DstRCSDWA> {
1371 dag ret = !if(HasDst,
1372 !if(!eq(DstVT.Size, 1),
1373 (outs DstRCSDWA:$sdst),
1374 (outs DstRCSDWA:$vdst)),
1378 // Returns the assembly string for the inputs and outputs of a VOP[12C]
1379 // instruction. This does not add the _e32 suffix, so it can be reused
1381 class getAsm32 <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1382 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1383 string src0 = ", $src0";
1384 string src1 = ", $src1";
1385 string src2 = ", $src2";
1386 string ret = !if(HasDst, dst, "") #
1387 !if(!eq(NumSrcArgs, 1), src0, "") #
1388 !if(!eq(NumSrcArgs, 2), src0#src1, "") #
1389 !if(!eq(NumSrcArgs, 3), src0#src1#src2, "");
1392 // Returns the assembly string for the inputs and outputs of a VOP3
1394 class getAsm64 <bit HasDst, int NumSrcArgs, bit HasIntClamp, bit HasModifiers,
1395 bit HasOMod, ValueType DstVT = i32> {
1396 string dst = !if(!eq(DstVT.Size, 1), "$sdst", "$vdst"); // use $sdst for VOPC
1397 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1398 string src1 = !if(!eq(NumSrcArgs, 1), "",
1399 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1400 " $src1_modifiers,"));
1401 string src2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1402 string iclamp = !if(HasIntClamp, "$clamp", "");
1404 !if(!eq(HasModifiers, 0),
1405 getAsm32<HasDst, NumSrcArgs, DstVT>.ret # iclamp,
1406 dst#", "#src0#src1#src2#"$clamp"#!if(HasOMod, "$omod", ""));
1409 // Returns the assembly string for the inputs and outputs of a VOP3P
1411 class getAsmVOP3P <bit HasDst, int NumSrcArgs, bit HasModifiers,
1412 bit HasClamp, ValueType DstVT = i32> {
1413 string dst = " $vdst";
1414 string src0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1415 string src1 = !if(!eq(NumSrcArgs, 1), "",
1416 !if(!eq(NumSrcArgs, 2), " $src1",
1418 string src2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1420 string mods = !if(HasModifiers, "$neg_lo$neg_hi", "");
1421 string clamp = !if(HasClamp, "$clamp", "");
1423 // Each modifier is printed as an array of bits for each operand, so
1424 // all operands are printed as part of src0_modifiers.
1425 string ret = dst#", "#src0#src1#src2#"$op_sel$op_sel_hi"#mods#clamp;
1428 class getAsmVOP3OpSel <int NumSrcArgs,
1433 string dst = " $vdst";
1435 string isrc0 = !if(!eq(NumSrcArgs, 1), "$src0", "$src0,");
1436 string isrc1 = !if(!eq(NumSrcArgs, 1), "",
1437 !if(!eq(NumSrcArgs, 2), " $src1",
1439 string isrc2 = !if(!eq(NumSrcArgs, 3), " $src2", "");
1441 string fsrc0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1442 string fsrc1 = !if(!eq(NumSrcArgs, 1), "",
1443 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1444 " $src1_modifiers,"));
1445 string fsrc2 = !if(!eq(NumSrcArgs, 3), " $src2_modifiers", "");
1447 string src0 = !if(Src0HasMods, fsrc0, isrc0);
1448 string src1 = !if(Src1HasMods, fsrc1, isrc1);
1449 string src2 = !if(Src2HasMods, fsrc2, isrc2);
1451 string clamp = !if(HasClamp, "$clamp", "");
1453 string ret = dst#", "#src0#src1#src2#"$op_sel"#clamp;
1456 class getAsmDPP <bit HasDst, int NumSrcArgs, bit HasModifiers, ValueType DstVT = i32> {
1457 string dst = !if(HasDst,
1458 !if(!eq(DstVT.Size, 1),
1461 ""); // use $sdst for VOPC
1462 string src0 = !if(!eq(NumSrcArgs, 1), "$src0_modifiers", "$src0_modifiers,");
1463 string src1 = !if(!eq(NumSrcArgs, 1), "",
1464 !if(!eq(NumSrcArgs, 2), " $src1_modifiers",
1465 " $src1_modifiers,"));
1466 string args = !if(!eq(HasModifiers, 0),
1467 getAsm32<0, NumSrcArgs, DstVT>.ret,
1469 string ret = dst#args#" $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
1472 class getAsmSDWA <bit HasDst, int NumSrcArgs, ValueType DstVT = i32> {
1473 string dst = !if(HasDst,
1474 !if(!eq(DstVT.Size, 1),
1475 " vcc", // use vcc token as dst for VOPC instructioins
1478 string src0 = "$src0_modifiers";
1479 string src1 = "$src1_modifiers";
1480 string args = !if(!eq(NumSrcArgs, 0),
1482 !if(!eq(NumSrcArgs, 1),
1484 ", "#src0#", "#src1#"$clamp"
1487 string sdwa = !if(!eq(NumSrcArgs, 0),
1489 !if(!eq(NumSrcArgs, 1),
1490 " $dst_sel $dst_unused $src0_sel",
1491 !if(!eq(DstVT.Size, 1),
1492 " $src0_sel $src1_sel", // No dst_sel and dst_unused for VOPC
1493 " $dst_sel $dst_unused $src0_sel $src1_sel"
1497 string ret = dst#args#sdwa;
1500 class getAsmSDWA9 <bit HasDst, bit HasOMod, int NumSrcArgs,
1501 ValueType DstVT = i32> {
1502 string dst = !if(HasDst,
1503 !if(!eq(DstVT.Size, 1),
1507 string src0 = "$src0_modifiers";
1508 string src1 = "$src1_modifiers";
1509 string out_mods = !if(!eq(HasOMod, 0), "$clamp", "$clamp$omod");
1510 string args = !if(!eq(NumSrcArgs, 0), "",
1511 !if(!eq(NumSrcArgs, 1),
1516 string sdwa = !if(!eq(NumSrcArgs, 0), "",
1517 !if(!eq(NumSrcArgs, 1),
1518 out_mods#" $dst_sel $dst_unused $src0_sel",
1519 !if(!eq(DstVT.Size, 1),
1520 " $src0_sel $src1_sel", // No dst_sel, dst_unused and output modifiers for VOPC
1521 out_mods#" $dst_sel $dst_unused $src0_sel $src1_sel"
1525 string ret = dst#args#sdwa;
1529 // Function that checks if instruction supports DPP and SDWA
1530 class getHasExt <int NumSrcArgs, ValueType DstVT = i32, ValueType Src0VT = i32,
1531 ValueType Src1VT = i32> {
1532 bit ret = !if(!eq(NumSrcArgs, 3),
1533 0, // NumSrcArgs == 3 - No DPP or SDWA for VOP3
1534 !if(!eq(DstVT.Size, 64),
1535 0, // 64-bit dst - No DPP or SDWA for 64-bit operands
1536 !if(!eq(Src0VT.Size, 64),
1538 !if(!eq(Src0VT.Size, 64),
1547 class BitOr<bit a, bit b> {
1548 bit ret = !if(a, 1, !if(b, 1, 0));
1551 class BitAnd<bit a, bit b> {
1552 bit ret = !if(a, !if(b, 1, 0), 0);
1555 class VOPProfile <list<ValueType> _ArgVT> {
1557 field list<ValueType> ArgVT = _ArgVT;
1559 field ValueType DstVT = ArgVT[0];
1560 field ValueType Src0VT = ArgVT[1];
1561 field ValueType Src1VT = ArgVT[2];
1562 field ValueType Src2VT = ArgVT[3];
1563 field RegisterOperand DstRC = getVALUDstForVT<DstVT>.ret;
1564 field RegisterOperand DstRCDPP = getVALUDstForVT<DstVT>.ret;
1565 field RegisterOperand DstRCSDWA = getSDWADstForVT<DstVT>.ret;
1566 field RegisterOperand Src0RC32 = getVOPSrc0ForVT<Src0VT>.ret;
1567 field RegisterClass Src1RC32 = getVregSrcForVT<Src1VT>.ret;
1568 field RegisterOperand Src0RC64 = getVOP3SrcForVT<Src0VT>.ret;
1569 field RegisterOperand Src1RC64 = getVOP3SrcForVT<Src1VT>.ret;
1570 field RegisterOperand Src2RC64 = getVOP3SrcForVT<Src2VT>.ret;
1571 field RegisterClass Src0DPP = getVregSrcForVT<Src0VT>.ret;
1572 field RegisterClass Src1DPP = getVregSrcForVT<Src1VT>.ret;
1573 field RegisterOperand Src0SDWA = getSDWASrcForVT<Src0VT>.ret;
1574 field RegisterOperand Src1SDWA = getSDWASrcForVT<Src0VT>.ret;
1575 field Operand Src0Mod = getSrcMod<Src0VT>.ret;
1576 field Operand Src1Mod = getSrcMod<Src1VT>.ret;
1577 field Operand Src2Mod = getSrcMod<Src2VT>.ret;
1578 field Operand Src0ModDPP = getSrcModExt<Src0VT>.ret;
1579 field Operand Src1ModDPP = getSrcModExt<Src1VT>.ret;
1580 field Operand Src0ModSDWA = getSrcModSDWA<Src0VT>.ret;
1581 field Operand Src1ModSDWA = getSrcModSDWA<Src1VT>.ret;
1584 field bit HasDst = !if(!eq(DstVT.Value, untyped.Value), 0, 1);
1585 field bit HasDst32 = HasDst;
1586 field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
1587 field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
1588 field bit HasSrc0 = !if(!eq(Src0VT.Value, untyped.Value), 0, 1);
1589 field bit HasSrc1 = !if(!eq(Src1VT.Value, untyped.Value), 0, 1);
1590 field bit HasSrc2 = !if(!eq(Src2VT.Value, untyped.Value), 0, 1);
1592 // TODO: Modifiers logic is somewhat adhoc here, to be refined later
1593 field bit HasModifiers = isModifierType<Src0VT>.ret;
1595 field bit HasSrc0FloatMods = isFloatType<Src0VT>.ret;
1596 field bit HasSrc1FloatMods = isFloatType<Src1VT>.ret;
1597 field bit HasSrc2FloatMods = isFloatType<Src2VT>.ret;
1599 field bit HasSrc0IntMods = isIntType<Src0VT>.ret;
1600 field bit HasSrc1IntMods = isIntType<Src1VT>.ret;
1601 field bit HasSrc2IntMods = isIntType<Src2VT>.ret;
1603 field bit HasSrc0Mods = HasModifiers;
1604 field bit HasSrc1Mods = !if(HasModifiers, BitOr<HasSrc1FloatMods, HasSrc1IntMods>.ret, 0);
1605 field bit HasSrc2Mods = !if(HasModifiers, BitOr<HasSrc2FloatMods, HasSrc2IntMods>.ret, 0);
1607 field bit HasClamp = HasModifiers;
1608 field bit HasSDWAClamp = EmitDst;
1609 field bit HasFPClamp = BitAnd<isFloatType<DstVT>.ret, HasClamp>.ret;
1610 field bit HasIntClamp = !if(isFloatType<DstVT>.ret, 0, HasClamp);
1611 field bit HasClampLo = HasClamp;
1612 field bit HasClampHi = BitAnd<isPackedType<DstVT>.ret, HasClamp>.ret;
1613 field bit HasHigh = 0;
1615 field bit IsPacked = isPackedType<Src0VT>.ret;
1616 field bit HasOpSel = IsPacked;
1617 field bit HasOMod = !if(HasOpSel, 0, isFloatType<DstVT>.ret);
1618 field bit HasSDWAOMod = isFloatType<DstVT>.ret;
1620 field bit HasExt = getHasExt<NumSrcArgs, DstVT, Src0VT, Src1VT>.ret;
1621 field bit HasSDWA9 = HasExt;
1623 field Operand Src0PackedMod = !if(HasSrc0FloatMods, PackedF16InputMods, PackedI16InputMods);
1624 field Operand Src1PackedMod = !if(HasSrc1FloatMods, PackedF16InputMods, PackedI16InputMods);
1625 field Operand Src2PackedMod = !if(HasSrc2FloatMods, PackedF16InputMods, PackedI16InputMods);
1627 field dag Outs = !if(HasDst,(outs DstRC:$vdst),(outs));
1629 // VOP3b instructions are a special case with a second explicit
1630 // output. This is manually overridden for them.
1631 field dag Outs32 = Outs;
1632 field dag Outs64 = Outs;
1633 field dag OutsDPP = getOutsExt<HasDst, DstVT, DstRCDPP>.ret;
1634 field dag OutsSDWA = getOutsSDWA<HasDst, DstVT, DstRCSDWA>.ret;
1636 field dag Ins32 = getIns32<Src0RC32, Src1RC32, NumSrcArgs>.ret;
1637 field dag Ins64 = getIns64<Src0RC64, Src1RC64, Src2RC64, NumSrcArgs,
1638 HasIntClamp, HasModifiers, HasOMod, Src0Mod, Src1Mod,
1640 field dag InsVOP3P = getInsVOP3P<Src0RC64, Src1RC64, Src2RC64,
1641 NumSrcArgs, HasClamp,
1642 Src0PackedMod, Src1PackedMod, Src2PackedMod>.ret;
1643 field dag InsVOP3OpSel = getInsVOP3OpSel<Src0RC64, Src1RC64, Src2RC64,
1646 getOpSelMod<Src0VT>.ret,
1647 getOpSelMod<Src1VT>.ret,
1648 getOpSelMod<Src2VT>.ret>.ret;
1649 field dag InsDPP = getInsDPP<DstRCDPP, Src0DPP, Src1DPP, NumSrcArgs,
1650 HasModifiers, Src0ModDPP, Src1ModDPP>.ret;
1651 field dag InsSDWA = getInsSDWA<Src0SDWA, Src1SDWA, NumSrcArgs,
1652 HasSDWAOMod, Src0ModSDWA, Src1ModSDWA,
1656 field string Asm32 = getAsm32<HasDst, NumSrcArgs, DstVT>.ret;
1657 field string Asm64 = getAsm64<HasDst, NumSrcArgs, HasIntClamp, HasModifiers, HasOMod, DstVT>.ret;
1658 field string AsmVOP3P = getAsmVOP3P<HasDst, NumSrcArgs, HasModifiers, HasClamp, DstVT>.ret;
1659 field string AsmVOP3OpSel = getAsmVOP3OpSel<NumSrcArgs,
1663 HasSrc2FloatMods>.ret;
1664 field string AsmDPP = getAsmDPP<HasDst, NumSrcArgs, HasModifiers, DstVT>.ret;
1665 field string AsmSDWA = getAsmSDWA<HasDst, NumSrcArgs, DstVT>.ret;
1666 field string AsmSDWA9 = getAsmSDWA9<HasDst, HasSDWAOMod, NumSrcArgs, DstVT>.ret;
1669 class VOP_NO_EXT <VOPProfile p> : VOPProfile <p.ArgVT> {
1674 def VOP_F16_F16 : VOPProfile <[f16, f16, untyped, untyped]>;
1675 def VOP_F16_I16 : VOPProfile <[f16, i16, untyped, untyped]>;
1676 def VOP_I16_F16 : VOPProfile <[i16, f16, untyped, untyped]>;
1678 def VOP_F16_F16_F16 : VOPProfile <[f16, f16, f16, untyped]>;
1679 def VOP_F16_F16_I16 : VOPProfile <[f16, f16, i16, untyped]>;
1680 def VOP_F16_F16_I32 : VOPProfile <[f16, f16, i32, untyped]>;
1681 def VOP_I16_I16_I16 : VOPProfile <[i16, i16, i16, untyped]>;
1683 def VOP_I16_I16_I16_I16 : VOPProfile <[i16, i16, i16, i16, untyped]>;
1684 def VOP_F16_F16_F16_F16 : VOPProfile <[f16, f16, f16, f16, untyped]>;
1686 def VOP_I32_I16_I16_I32 : VOPProfile <[i32, i16, i16, i32, untyped]>;
1688 def VOP_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, untyped]>;
1689 def VOP_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, untyped]>;
1690 def VOP_B32_F16_F16 : VOPProfile <[i32, f16, f16, untyped]>;
1692 def VOP_V2F16_V2F16_V2F16_V2F16 : VOPProfile <[v2f16, v2f16, v2f16, v2f16]>;
1693 def VOP_V2I16_V2I16_V2I16_V2I16 : VOPProfile <[v2i16, v2i16, v2i16, v2i16]>;
1695 def VOP_F32_V2F16_V2F16_V2F16 : VOPProfile <[f32, v2f16, v2f16, v2f16]>;
1697 def VOP_NONE : VOPProfile <[untyped, untyped, untyped, untyped]>;
1699 def VOP_F32_F32 : VOPProfile <[f32, f32, untyped, untyped]>;
1700 def VOP_F32_F64 : VOPProfile <[f32, f64, untyped, untyped]>;
1701 def VOP_F32_I32 : VOPProfile <[f32, i32, untyped, untyped]>;
1702 def VOP_F64_F32 : VOPProfile <[f64, f32, untyped, untyped]>;
1703 def VOP_F64_F64 : VOPProfile <[f64, f64, untyped, untyped]>;
1704 def VOP_F64_I32 : VOPProfile <[f64, i32, untyped, untyped]>;
1705 def VOP_I32_F32 : VOPProfile <[i32, f32, untyped, untyped]>;
1706 def VOP_I32_F64 : VOPProfile <[i32, f64, untyped, untyped]>;
1707 def VOP_I32_I32 : VOPProfile <[i32, i32, untyped, untyped]>;
1708 def VOP_F16_F32 : VOPProfile <[f16, f32, untyped, untyped]>;
1709 def VOP_F32_F16 : VOPProfile <[f32, f16, untyped, untyped]>;
1711 def VOP_F32_F32_F16 : VOPProfile <[f32, f32, f16, untyped]>;
1712 def VOP_F32_F32_F32 : VOPProfile <[f32, f32, f32, untyped]>;
1713 def VOP_F32_F32_I32 : VOPProfile <[f32, f32, i32, untyped]>;
1714 def VOP_F64_F64_F64 : VOPProfile <[f64, f64, f64, untyped]>;
1715 def VOP_F64_F64_I32 : VOPProfile <[f64, f64, i32, untyped]>;
1716 def VOP_I32_F32_F32 : VOPProfile <[i32, f32, f32, untyped]>;
1717 def VOP_I32_F32_I32 : VOPProfile <[i32, f32, i32, untyped]>;
1718 def VOP_I32_I32_I32 : VOPProfile <[i32, i32, i32, untyped]>;
1719 def VOP_V2F16_F32_F32 : VOPProfile <[v2f16, f32, f32, untyped]>;
1720 def VOP_F32_F16_F16_F16 : VOPProfile <[f32, f16, f16, f16]>;
1722 def VOP_I64_I64_I32 : VOPProfile <[i64, i64, i32, untyped]>;
1723 def VOP_I64_I32_I64 : VOPProfile <[i64, i32, i64, untyped]>;
1724 def VOP_I64_I64_I64 : VOPProfile <[i64, i64, i64, untyped]>;
1726 def VOP_F16_F32_F16_F32 : VOPProfile <[f16, f32, f16, f32]>;
1727 def VOP_F32_F32_F16_F16 : VOPProfile <[f32, f32, f16, f16]>;
1728 def VOP_F32_F32_F32_F32 : VOPProfile <[f32, f32, f32, f32]>;
1729 def VOP_F64_F64_F64_F64 : VOPProfile <[f64, f64, f64, f64]>;
1730 def VOP_I32_I32_I32_I32 : VOPProfile <[i32, i32, i32, i32]>;
1731 def VOP_I64_I32_I32_I64 : VOPProfile <[i64, i32, i32, i64]>;
1732 def VOP_I32_F32_I32_I32 : VOPProfile <[i32, f32, i32, i32]>;
1733 def VOP_I64_I64_I32_I64 : VOPProfile <[i64, i64, i32, i64]>;
1734 def VOP_V4I32_I64_I32_V4I32 : VOPProfile <[v4i32, i64, i32, v4i32]>;
1736 class Commutable_REV <string revOp, bit isOrig> {
1737 string RevOp = revOp;
1738 bit IsOrig = isOrig;
1741 class AtomicNoRet <string noRetOp, bit isRet> {
1742 string NoRetOp = noRetOp;
1746 //===----------------------------------------------------------------------===//
1747 // Interpolation opcodes
1748 //===----------------------------------------------------------------------===//
1750 class VINTRP_Pseudo <string opName, dag outs, dag ins, list<dag> pattern> :
1751 VINTRPCommon <outs, ins, "", pattern>,
1752 SIMCInstr<opName, SIEncodingFamily.NONE> {
1754 let isCodeGenOnly = 1;
1757 class VINTRP_Real_si <bits <2> op, string opName, dag outs, dag ins,
1759 VINTRPCommon <outs, ins, asm, []>,
1761 SIMCInstr<opName, SIEncodingFamily.SI> {
1762 let AssemblerPredicate = SIAssemblerPredicate;
1763 let DecoderNamespace = "SICI";
1764 let DisableDecoder = DisableSIDecoder;
1767 class VINTRP_Real_vi <bits <2> op, string opName, dag outs, dag ins,
1769 VINTRPCommon <outs, ins, asm, []>,
1771 SIMCInstr<opName, SIEncodingFamily.VI> {
1772 let AssemblerPredicate = VIAssemblerPredicate;
1773 let DecoderNamespace = "VI";
1774 let DisableDecoder = DisableVIDecoder;
1777 multiclass VINTRP_m <bits <2> op, dag outs, dag ins, string asm,
1778 list<dag> pattern = []> {
1779 def "" : VINTRP_Pseudo <NAME, outs, ins, pattern>;
1781 def _si : VINTRP_Real_si <op, NAME, outs, ins, asm>;
1783 def _vi : VINTRP_Real_vi <op, NAME, outs, ins, asm>;
1786 //===----------------------------------------------------------------------===//
1787 // Vector instruction mappings
1788 //===----------------------------------------------------------------------===//
1790 // Maps an opcode in e32 form to its e64 equivalent
1791 def getVOPe64 : InstrMapping {
1792 let FilterClass = "VOP";
1793 let RowFields = ["OpName"];
1794 let ColFields = ["Size", "VOP3"];
1795 let KeyCol = ["4", "0"];
1796 let ValueCols = [["8", "1"]];
1799 // Maps an opcode in e64 form to its e32 equivalent
1800 def getVOPe32 : InstrMapping {
1801 let FilterClass = "VOP";
1802 let RowFields = ["OpName"];
1803 let ColFields = ["Size", "VOP3"];
1804 let KeyCol = ["8", "1"];
1805 let ValueCols = [["4", "0"]];
1808 // Maps ordinary instructions to their SDWA counterparts
1809 def getSDWAOp : InstrMapping {
1810 let FilterClass = "VOP";
1811 let RowFields = ["OpName"];
1812 let ColFields = ["AsmVariantName"];
1813 let KeyCol = ["Default"];
1814 let ValueCols = [["SDWA"]];
1817 // Maps SDWA instructions to their ordinary counterparts
1818 def getBasicFromSDWAOp : InstrMapping {
1819 let FilterClass = "VOP";
1820 let RowFields = ["OpName"];
1821 let ColFields = ["AsmVariantName"];
1822 let KeyCol = ["SDWA"];
1823 let ValueCols = [["Default"]];
1826 def getMaskedMIMGOp1 : InstrMapping {
1827 let FilterClass = "MIMG_Mask";
1828 let RowFields = ["Op"];
1829 let ColFields = ["Channels"];
1831 let ValueCols = [["2"], ["3"], ["4"] ];
1834 def getMaskedMIMGOp2 : InstrMapping {
1835 let FilterClass = "MIMG_Mask";
1836 let RowFields = ["Op"];
1837 let ColFields = ["Channels"];
1839 let ValueCols = [["1"], ["3"], ["4"] ];
1842 def getMaskedMIMGOp3 : InstrMapping {
1843 let FilterClass = "MIMG_Mask";
1844 let RowFields = ["Op"];
1845 let ColFields = ["Channels"];
1847 let ValueCols = [["1"], ["2"], ["4"] ];
1850 def getMaskedMIMGOp4 : InstrMapping {
1851 let FilterClass = "MIMG_Mask";
1852 let RowFields = ["Op"];
1853 let ColFields = ["Channels"];
1855 let ValueCols = [["1"], ["2"], ["3"] ];
1858 // Maps an commuted opcode to its original version
1859 def getCommuteOrig : InstrMapping {
1860 let FilterClass = "Commutable_REV";
1861 let RowFields = ["RevOp"];
1862 let ColFields = ["IsOrig"];
1864 let ValueCols = [["1"]];
1867 // Maps an original opcode to its commuted version
1868 def getCommuteRev : InstrMapping {
1869 let FilterClass = "Commutable_REV";
1870 let RowFields = ["RevOp"];
1871 let ColFields = ["IsOrig"];
1873 let ValueCols = [["0"]];
1876 def getMCOpcodeGen : InstrMapping {
1877 let FilterClass = "SIMCInstr";
1878 let RowFields = ["PseudoInstr"];
1879 let ColFields = ["Subtarget"];
1880 let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
1881 let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
1882 [!cast<string>(SIEncodingFamily.VI)],
1883 [!cast<string>(SIEncodingFamily.SDWA)],
1884 [!cast<string>(SIEncodingFamily.SDWA9)],
1885 [!cast<string>(SIEncodingFamily.GFX9)]];
1888 // Get equivalent SOPK instruction.
1889 def getSOPKOp : InstrMapping {
1890 let FilterClass = "SOPKInstTable";
1891 let RowFields = ["BaseCmpOp"];
1892 let ColFields = ["IsSOPK"];
1894 let ValueCols = [["1"]];
1897 def getAddr64Inst : InstrMapping {
1898 let FilterClass = "MUBUFAddr64Table";
1899 let RowFields = ["OpName"];
1900 let ColFields = ["IsAddr64"];
1902 let ValueCols = [["1"]];
1905 // Maps an atomic opcode to its version with a return value.
1906 def getAtomicRetOp : InstrMapping {
1907 let FilterClass = "AtomicNoRet";
1908 let RowFields = ["NoRetOp"];
1909 let ColFields = ["IsRet"];
1911 let ValueCols = [["1"]];
1914 // Maps an atomic opcode to its returnless version.
1915 def getAtomicNoRetOp : InstrMapping {
1916 let FilterClass = "AtomicNoRet";
1917 let RowFields = ["NoRetOp"];
1918 let ColFields = ["IsRet"];
1920 let ValueCols = [["0"]];
1923 include "SIInstructions.td"
1925 include "DSInstructions.td"
1926 include "MIMGInstructions.td"