1 //===-- SILowerI1Copies.cpp - Lower I1 Copies -----------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 /// i1 values are usually inserted by the CFG Structurize pass and they are
9 /// unique in that they can be copied from VALU to SALU registers.
10 /// This is not possible for any other value type. Since there are no
11 /// MOV instructions for i1, we to use V_CMP_* and V_CNDMASK to move the i1.
13 //===----------------------------------------------------------------------===//
16 #define DEBUG_TYPE "si-i1-copies"
18 #include "AMDGPUSubtarget.h"
19 #include "SIInstrInfo.h"
20 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
21 #include "llvm/CodeGen/MachineFunctionPass.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/IR/Function.h"
25 #include "llvm/IR/LLVMContext.h"
26 #include "llvm/Support/Debug.h"
27 #include "llvm/Target/TargetMachine.h"
33 class SILowerI1Copies : public MachineFunctionPass {
38 SILowerI1Copies() : MachineFunctionPass(ID) {
39 initializeSILowerI1CopiesPass(*PassRegistry::getPassRegistry());
42 bool runOnMachineFunction(MachineFunction &MF) override;
44 StringRef getPassName() const override { return "SI Lower i1 Copies"; }
46 void getAnalysisUsage(AnalysisUsage &AU) const override {
48 MachineFunctionPass::getAnalysisUsage(AU);
52 } // End anonymous namespace.
54 INITIALIZE_PASS(SILowerI1Copies, DEBUG_TYPE,
55 "SI Lower i1 Copies", false, false)
57 char SILowerI1Copies::ID = 0;
59 char &llvm::SILowerI1CopiesID = SILowerI1Copies::ID;
61 FunctionPass *llvm::createSILowerI1CopiesPass() {
62 return new SILowerI1Copies();
65 bool SILowerI1Copies::runOnMachineFunction(MachineFunction &MF) {
66 MachineRegisterInfo &MRI = MF.getRegInfo();
67 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
68 const SIInstrInfo *TII = ST.getInstrInfo();
69 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
71 std::vector<unsigned> I1Defs;
73 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
76 MachineBasicBlock &MBB = *BI;
77 MachineBasicBlock::iterator I, Next;
78 for (I = MBB.begin(); I != MBB.end(); I = Next) {
80 MachineInstr &MI = *I;
82 if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) {
83 unsigned Reg = MI.getOperand(0).getReg();
84 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
85 if (RC == &AMDGPU::VReg_1RegClass)
86 MRI.setRegClass(Reg, &AMDGPU::SReg_64RegClass);
90 if (MI.getOpcode() != AMDGPU::COPY)
93 const MachineOperand &Dst = MI.getOperand(0);
94 const MachineOperand &Src = MI.getOperand(1);
96 if (!TargetRegisterInfo::isVirtualRegister(Src.getReg()) ||
97 !TargetRegisterInfo::isVirtualRegister(Dst.getReg()))
100 const TargetRegisterClass *DstRC = MRI.getRegClass(Dst.getReg());
101 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg());
103 DebugLoc DL = MI.getDebugLoc();
104 MachineInstr *DefInst = MRI.getUniqueVRegDef(Src.getReg());
105 if (DstRC == &AMDGPU::VReg_1RegClass &&
106 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
107 I1Defs.push_back(Dst.getReg());
109 if (DefInst->getOpcode() == AMDGPU::S_MOV_B64) {
110 if (DefInst->getOperand(1).isImm()) {
111 I1Defs.push_back(Dst.getReg());
113 int64_t Val = DefInst->getOperand(1).getImm();
114 assert(Val == 0 || Val == -1);
116 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_MOV_B32_e32))
119 MI.eraseFromParent();
124 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64))
129 MI.eraseFromParent();
130 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
131 SrcRC == &AMDGPU::VReg_1RegClass) {
132 if (DefInst->getOpcode() == AMDGPU::V_CNDMASK_B32_e64 &&
133 DefInst->getOperand(1).isImm() && DefInst->getOperand(2).isImm() &&
134 DefInst->getOperand(1).getImm() == 0 &&
135 DefInst->getOperand(2).getImm() != 0 &&
136 DefInst->getOperand(3).isReg() &&
137 TargetRegisterInfo::isVirtualRegister(
138 DefInst->getOperand(3).getReg()) &&
139 TRI->getCommonSubClass(
140 MRI.getRegClass(DefInst->getOperand(3).getReg()),
141 &AMDGPU::SGPR_64RegClass)) {
142 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_B64))
144 .addReg(AMDGPU::EXEC)
145 .add(DefInst->getOperand(3));
147 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMP_NE_U32_e64))
152 MI.eraseFromParent();
157 for (unsigned Reg : I1Defs)
158 MRI.setRegClass(Reg, &AMDGPU::VGPR_32RegClass);