1 //===- SIMachineFunctionInfo.cpp - SI Machine Function Info ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "SIMachineFunctionInfo.h"
11 #include "AMDGPUArgumentUsageInfo.h"
12 #include "AMDGPUSubtarget.h"
13 #include "SIRegisterInfo.h"
14 #include "Utils/AMDGPUBaseInfo.h"
15 #include "llvm/ADT/Optional.h"
16 #include "llvm/CodeGen/MachineBasicBlock.h"
17 #include "llvm/CodeGen/MachineFrameInfo.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #include "llvm/IR/CallingConv.h"
21 #include "llvm/IR/Function.h"
29 SIMachineFunctionInfo::SIMachineFunctionInfo(const MachineFunction &MF)
30 : AMDGPUMachineFunction(MF),
31 BufferPSV(*(MF.getSubtarget().getInstrInfo())),
32 ImagePSV(*(MF.getSubtarget().getInstrInfo())),
33 PrivateSegmentBuffer(false),
36 KernargSegmentPtr(false),
38 FlatScratchInit(false),
39 GridWorkgroupCountX(false),
40 GridWorkgroupCountY(false),
41 GridWorkgroupCountZ(false),
46 PrivateSegmentWaveByteOffset(false),
50 ImplicitBufferPtr(false),
51 ImplicitArgPtr(false),
52 GITPtrHigh(0xffffffff) {
53 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
54 const Function &F = MF.getFunction();
55 FlatWorkGroupSizes = ST.getFlatWorkGroupSizes(F);
56 WavesPerEU = ST.getWavesPerEU(F);
58 if (!isEntryFunction()) {
59 // Non-entry functions have no special inputs for now, other registers
60 // required for scratch access.
61 ScratchRSrcReg = AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3;
62 ScratchWaveOffsetReg = AMDGPU::SGPR4;
63 FrameOffsetReg = AMDGPU::SGPR5;
64 StackPtrOffsetReg = AMDGPU::SGPR32;
66 ArgInfo.PrivateSegmentBuffer =
67 ArgDescriptor::createRegister(ScratchRSrcReg);
68 ArgInfo.PrivateSegmentWaveByteOffset =
69 ArgDescriptor::createRegister(ScratchWaveOffsetReg);
71 if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
72 ImplicitArgPtr = true;
74 if (F.hasFnAttribute("amdgpu-implicitarg-ptr"))
75 KernargSegmentPtr = true;
78 CallingConv::ID CC = F.getCallingConv();
79 if (CC == CallingConv::AMDGPU_KERNEL || CC == CallingConv::SPIR_KERNEL) {
81 KernargSegmentPtr = true;
84 } else if (CC == CallingConv::AMDGPU_PS) {
85 PSInputAddr = AMDGPU::getInitialPSInputAddr(F);
88 if (ST.debuggerEmitPrologue()) {
97 if (F.hasFnAttribute("amdgpu-work-group-id-x"))
100 if (F.hasFnAttribute("amdgpu-work-group-id-y"))
103 if (F.hasFnAttribute("amdgpu-work-group-id-z"))
106 if (F.hasFnAttribute("amdgpu-work-item-id-x"))
109 if (F.hasFnAttribute("amdgpu-work-item-id-y"))
112 if (F.hasFnAttribute("amdgpu-work-item-id-z"))
116 const MachineFrameInfo &FrameInfo = MF.getFrameInfo();
117 bool MaySpill = ST.isVGPRSpillingEnabled(F);
118 bool HasStackObjects = FrameInfo.hasStackObjects();
120 if (isEntryFunction()) {
121 // X, XY, and XYZ are the only supported combinations, so make sure Y is
126 if (HasStackObjects || MaySpill) {
127 PrivateSegmentWaveByteOffset = true;
129 // HS and GS always have the scratch wave offset in SGPR5 on GFX9.
130 if (ST.getGeneration() >= AMDGPUSubtarget::GFX9 &&
131 (CC == CallingConv::AMDGPU_HS || CC == CallingConv::AMDGPU_GS))
132 ArgInfo.PrivateSegmentWaveByteOffset
133 = ArgDescriptor::createRegister(AMDGPU::SGPR5);
137 bool IsCOV2 = ST.isAmdCodeObjectV2(MF);
139 if (HasStackObjects || MaySpill)
140 PrivateSegmentBuffer = true;
142 if (F.hasFnAttribute("amdgpu-dispatch-ptr"))
145 if (F.hasFnAttribute("amdgpu-queue-ptr"))
148 if (F.hasFnAttribute("amdgpu-dispatch-id"))
150 } else if (ST.isMesaGfxShader(MF)) {
151 if (HasStackObjects || MaySpill)
152 ImplicitBufferPtr = true;
155 if (F.hasFnAttribute("amdgpu-kernarg-segment-ptr"))
156 KernargSegmentPtr = true;
158 if (ST.hasFlatAddressSpace() && isEntryFunction() && IsCOV2) {
159 // TODO: This could be refined a lot. The attribute is a poor way of
160 // detecting calls that may require it before argument lowering.
161 if (HasStackObjects || F.hasFnAttribute("amdgpu-flat-scratch"))
162 FlatScratchInit = true;
165 Attribute A = F.getFnAttribute("amdgpu-git-ptr-high");
166 StringRef S = A.getValueAsString();
168 S.consumeInteger(0, GITPtrHigh);
171 unsigned SIMachineFunctionInfo::addPrivateSegmentBuffer(
172 const SIRegisterInfo &TRI) {
173 ArgInfo.PrivateSegmentBuffer =
174 ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
175 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_128RegClass));
177 return ArgInfo.PrivateSegmentBuffer.getRegister();
180 unsigned SIMachineFunctionInfo::addDispatchPtr(const SIRegisterInfo &TRI) {
181 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
182 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
184 return ArgInfo.DispatchPtr.getRegister();
187 unsigned SIMachineFunctionInfo::addQueuePtr(const SIRegisterInfo &TRI) {
188 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
189 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
191 return ArgInfo.QueuePtr.getRegister();
194 unsigned SIMachineFunctionInfo::addKernargSegmentPtr(const SIRegisterInfo &TRI) {
195 ArgInfo.KernargSegmentPtr
196 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
197 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
199 return ArgInfo.KernargSegmentPtr.getRegister();
202 unsigned SIMachineFunctionInfo::addDispatchID(const SIRegisterInfo &TRI) {
203 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
204 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
206 return ArgInfo.DispatchID.getRegister();
209 unsigned SIMachineFunctionInfo::addFlatScratchInit(const SIRegisterInfo &TRI) {
210 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
211 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
213 return ArgInfo.FlatScratchInit.getRegister();
216 unsigned SIMachineFunctionInfo::addImplicitBufferPtr(const SIRegisterInfo &TRI) {
217 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg(
218 getNextUserSGPR(), AMDGPU::sub0, &AMDGPU::SReg_64RegClass));
220 return ArgInfo.ImplicitBufferPtr.getRegister();
223 static bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) {
224 for (unsigned I = 0; CSRegs[I]; ++I) {
225 if (CSRegs[I] == Reg)
232 /// Reserve a slice of a VGPR to support spilling for FrameIndex \p FI.
233 bool SIMachineFunctionInfo::allocateSGPRSpillToVGPR(MachineFunction &MF,
235 std::vector<SpilledReg> &SpillLanes = SGPRToVGPRSpills[FI];
237 // This has already been allocated.
238 if (!SpillLanes.empty())
241 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
242 const SIRegisterInfo *TRI = ST.getRegisterInfo();
243 MachineFrameInfo &FrameInfo = MF.getFrameInfo();
244 MachineRegisterInfo &MRI = MF.getRegInfo();
245 unsigned WaveSize = ST.getWavefrontSize();
247 unsigned Size = FrameInfo.getObjectSize(FI);
248 assert(Size >= 4 && Size <= 64 && "invalid sgpr spill size");
249 assert(TRI->spillSGPRToVGPR() && "not spilling SGPRs to VGPRs");
251 int NumLanes = Size / 4;
253 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
255 // Make sure to handle the case where a wide SGPR spill may span between two
257 for (int I = 0; I < NumLanes; ++I, ++NumVGPRSpillLanes) {
259 unsigned VGPRIndex = (NumVGPRSpillLanes % WaveSize);
261 if (VGPRIndex == 0) {
262 LaneVGPR = TRI->findUnusedRegister(MRI, &AMDGPU::VGPR_32RegClass, MF);
263 if (LaneVGPR == AMDGPU::NoRegister) {
264 // We have no VGPRs left for spilling SGPRs. Reset because we will not
265 // partially spill the SGPR to VGPRs.
266 SGPRToVGPRSpills.erase(FI);
267 NumVGPRSpillLanes -= I;
271 Optional<int> CSRSpillFI;
272 if (FrameInfo.hasCalls() && CSRegs && isCalleeSavedReg(CSRegs, LaneVGPR)) {
273 // TODO: Should this be a CreateSpillStackObject? This is technically a
275 CSRSpillFI = FrameInfo.CreateStackObject(4, 4, false);
278 SpillVGPRs.push_back(SGPRSpillVGPRCSR(LaneVGPR, CSRSpillFI));
280 // Add this register as live-in to all blocks to avoid machine verifer
281 // complaining about use of an undefined physical register.
282 for (MachineBasicBlock &BB : MF)
283 BB.addLiveIn(LaneVGPR);
285 LaneVGPR = SpillVGPRs.back().VGPR;
288 SpillLanes.push_back(SpilledReg(LaneVGPR, VGPRIndex));
294 void SIMachineFunctionInfo::removeSGPRToVGPRFrameIndices(MachineFrameInfo &MFI) {
295 for (auto &R : SGPRToVGPRSpills)
296 MFI.RemoveStackObject(R.first);