1 //===-- SIOptimizeExecMaskingPreRA.cpp ------------------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief This pass removes redundant S_OR_B64 instructions enabling lanes in
12 /// the exec. If two SI_END_CF (lowered as S_OR_B64) come together without any
13 /// vector instructions between them we can only keep outer SI_END_CF, given
14 /// that CFG is structured and exec bits of the outer end statement are always
15 /// not less than exec bit of the inner one.
17 /// This needs to be done before the RA to eliminate saved exec bits registers
18 /// but after register coalescer to have no vector registers copies in between
19 /// of different end cf statements.
21 //===----------------------------------------------------------------------===//
24 #include "AMDGPUSubtarget.h"
25 #include "SIInstrInfo.h"
26 #include "llvm/CodeGen/LiveIntervals.h"
27 #include "llvm/CodeGen/MachineFunctionPass.h"
31 #define DEBUG_TYPE "si-optimize-exec-masking-pre-ra"
35 class SIOptimizeExecMaskingPreRA : public MachineFunctionPass {
40 SIOptimizeExecMaskingPreRA() : MachineFunctionPass(ID) {
41 initializeSIOptimizeExecMaskingPreRAPass(*PassRegistry::getPassRegistry());
44 bool runOnMachineFunction(MachineFunction &MF) override;
46 StringRef getPassName() const override {
47 return "SI optimize exec mask operations pre-RA";
50 void getAnalysisUsage(AnalysisUsage &AU) const override {
51 AU.addRequired<LiveIntervals>();
53 MachineFunctionPass::getAnalysisUsage(AU);
57 } // End anonymous namespace.
59 INITIALIZE_PASS_BEGIN(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
60 "SI optimize exec mask operations pre-RA", false, false)
61 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
62 INITIALIZE_PASS_END(SIOptimizeExecMaskingPreRA, DEBUG_TYPE,
63 "SI optimize exec mask operations pre-RA", false, false)
65 char SIOptimizeExecMaskingPreRA::ID = 0;
67 char &llvm::SIOptimizeExecMaskingPreRAID = SIOptimizeExecMaskingPreRA::ID;
69 FunctionPass *llvm::createSIOptimizeExecMaskingPreRAPass() {
70 return new SIOptimizeExecMaskingPreRA();
73 static bool isEndCF(const MachineInstr& MI, const SIRegisterInfo* TRI) {
74 return MI.getOpcode() == AMDGPU::S_OR_B64 &&
75 MI.modifiesRegister(AMDGPU::EXEC, TRI);
78 static bool isFullExecCopy(const MachineInstr& MI) {
79 return MI.isFullCopy() && MI.getOperand(1).getReg() == AMDGPU::EXEC;
82 static unsigned getOrNonExecReg(const MachineInstr &MI,
83 const SIInstrInfo &TII) {
84 auto Op = TII.getNamedOperand(MI, AMDGPU::OpName::src1);
85 if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
87 Op = TII.getNamedOperand(MI, AMDGPU::OpName::src0);
88 if (Op->isReg() && Op->getReg() != AMDGPU::EXEC)
90 return AMDGPU::NoRegister;
93 static MachineInstr* getOrExecSource(const MachineInstr &MI,
94 const SIInstrInfo &TII,
95 const MachineRegisterInfo &MRI) {
96 auto SavedExec = getOrNonExecReg(MI, TII);
97 if (SavedExec == AMDGPU::NoRegister)
99 auto SaveExecInst = MRI.getUniqueVRegDef(SavedExec);
100 if (!SaveExecInst || !isFullExecCopy(*SaveExecInst))
105 bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) {
106 if (skipFunction(MF.getFunction()))
109 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
110 const SIRegisterInfo *TRI = ST.getRegisterInfo();
111 const SIInstrInfo *TII = ST.getInstrInfo();
112 MachineRegisterInfo &MRI = MF.getRegInfo();
113 LiveIntervals *LIS = &getAnalysis<LiveIntervals>();
114 DenseSet<unsigned> RecalcRegs({AMDGPU::EXEC_LO, AMDGPU::EXEC_HI});
115 bool Changed = false;
117 for (MachineBasicBlock &MBB : MF) {
119 // Try to remove unneeded instructions before s_endpgm.
120 if (MBB.succ_empty()) {
121 if (MBB.empty() || MBB.back().getOpcode() != AMDGPU::S_ENDPGM)
124 SmallVector<MachineBasicBlock*, 4> Blocks({&MBB});
126 while (!Blocks.empty()) {
127 auto CurBB = Blocks.pop_back_val();
128 auto I = CurBB->rbegin(), E = CurBB->rend();
130 if (I->isUnconditionalBranch() || I->getOpcode() == AMDGPU::S_ENDPGM)
132 else if (I->isBranch())
137 if (I->isDebugValue()) {
142 if (I->mayStore() || I->isBarrier() || I->isCall() ||
143 I->hasUnmodeledSideEffects() || I->hasOrderedMemoryRef())
146 DEBUG(dbgs() << "Removing no effect instruction: " << *I << '\n');
148 for (auto &Op : I->operands()) {
150 RecalcRegs.insert(Op.getReg());
153 auto Next = std::next(I);
154 LIS->RemoveMachineInstrFromMaps(*I);
155 I->eraseFromParent();
164 // Try to ascend predecessors.
165 for (auto *Pred : CurBB->predecessors()) {
166 if (Pred->succ_size() == 1)
167 Blocks.push_back(Pred);
173 // Try to collapse adjacent endifs.
174 auto Lead = MBB.begin(), E = MBB.end();
175 if (MBB.succ_size() != 1 || Lead == E || !isEndCF(*Lead, TRI))
178 const MachineBasicBlock* Succ = *MBB.succ_begin();
179 if (!MBB.isLayoutSuccessor(Succ))
182 auto I = std::next(Lead);
185 if (!TII->isSALU(*I) || I->readsRegister(AMDGPU::EXEC, TRI))
191 const auto NextLead = Succ->begin();
192 if (NextLead == Succ->end() || !isEndCF(*NextLead, TRI) ||
193 !getOrExecSource(*NextLead, *TII, MRI))
196 DEBUG(dbgs() << "Redundant EXEC = S_OR_B64 found: " << *Lead << '\n');
198 auto SaveExec = getOrExecSource(*Lead, *TII, MRI);
199 unsigned SaveExecReg = getOrNonExecReg(*Lead, *TII);
200 for (auto &Op : Lead->operands()) {
202 RecalcRegs.insert(Op.getReg());
205 LIS->RemoveMachineInstrFromMaps(*Lead);
206 Lead->eraseFromParent();
208 LIS->removeInterval(SaveExecReg);
209 LIS->createAndComputeVirtRegInterval(SaveExecReg);
214 // If the only use of saved exec in the removed instruction is S_AND_B64
215 // fold the copy now.
216 if (!SaveExec || !SaveExec->isFullCopy())
219 unsigned SavedExec = SaveExec->getOperand(0).getReg();
220 bool SafeToReplace = true;
221 for (auto& U : MRI.use_nodbg_instructions(SavedExec)) {
222 if (U.getParent() != SaveExec->getParent()) {
223 SafeToReplace = false;
227 DEBUG(dbgs() << "Redundant EXEC COPY: " << *SaveExec << '\n');
231 LIS->RemoveMachineInstrFromMaps(*SaveExec);
232 SaveExec->eraseFromParent();
233 MRI.replaceRegWith(SavedExec, AMDGPU::EXEC);
234 LIS->removeInterval(SavedExec);
239 for (auto Reg : RecalcRegs) {
240 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
241 LIS->removeInterval(Reg);
242 if (!MRI.reg_empty(Reg))
243 LIS->createAndComputeVirtRegInterval(Reg);
245 for (MCRegUnitIterator U(Reg, TRI); U.isValid(); ++U)
246 LIS->removeRegUnit(*U);