1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
18 #include "AMDGPURegisterInfo.h"
19 #include "SIDefines.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 class MachineRegisterInfo;
26 class SIMachineFunctionInfo;
28 class SIRegisterInfo final : public AMDGPURegisterInfo {
32 BitVector SGPRPressureSets;
33 BitVector VGPRPressureSets;
37 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
38 void classifyPressureSet(unsigned PSetID, unsigned Reg,
39 BitVector &PressureSets) const;
41 SIRegisterInfo(const SISubtarget &ST);
43 bool spillSGPRToVGPR() const {
44 return SpillSGPRToVGPR;
47 bool spillSGPRToSMEM() const {
48 return SpillSGPRToSMEM;
51 /// Return the end register initially reserved for the scratch buffer in case
52 /// spilling is needed.
53 unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
55 /// Return the end register initially reserved for the scratch wave offset in
56 /// case spilling is needed.
57 unsigned reservedPrivateSegmentWaveByteOffsetReg(
58 const MachineFunction &MF) const;
60 BitVector getReservedRegs(const MachineFunction &MF) const override;
62 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
64 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
65 bool requiresFrameIndexReplacementScavenging(
66 const MachineFunction &MF) const override;
67 bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
68 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
70 int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
72 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
73 int Idx) const override;
75 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
77 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
78 unsigned BaseReg, int FrameIdx,
79 int64_t Offset) const override;
81 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
82 int64_t Offset) const override;
84 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
85 int64_t Offset) const override;
87 const TargetRegisterClass *getPointerRegClass(
88 const MachineFunction &MF, unsigned Kind = 0) const override;
90 /// If \p OnlyToVGPR is true, this will only succeed if this
91 bool spillSGPR(MachineBasicBlock::iterator MI,
92 int FI, RegScavenger *RS,
93 bool OnlyToVGPR = false) const;
95 bool restoreSGPR(MachineBasicBlock::iterator MI,
96 int FI, RegScavenger *RS,
97 bool OnlyToVGPR = false) const;
99 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
100 unsigned FIOperandNum,
101 RegScavenger *RS) const override;
103 bool eliminateSGPRToVGPRSpillFrameIndex(MachineBasicBlock::iterator MI,
104 int FI, RegScavenger *RS) const;
106 unsigned getHWRegIndex(unsigned Reg) const {
107 return getEncodingValue(Reg) & 0xff;
110 /// \brief Return the 'base' register class for this register.
111 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
112 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
114 /// \returns true if this class contains only SGPR registers
115 bool isSGPRClass(const TargetRegisterClass *RC) const {
116 return !hasVGPRs(RC);
119 /// \returns true if this class ID contains only SGPR registers
120 bool isSGPRClassID(unsigned RCID) const {
121 return isSGPRClass(getRegClass(RCID));
124 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
125 const TargetRegisterClass *RC;
126 if (TargetRegisterInfo::isVirtualRegister(Reg))
127 RC = MRI.getRegClass(Reg);
129 RC = getPhysRegClass(Reg);
130 return isSGPRClass(RC);
133 /// \returns true if this class contains VGPR registers.
134 bool hasVGPRs(const TargetRegisterClass *RC) const;
136 /// \returns A VGPR reg class with the same width as \p SRC
137 const TargetRegisterClass *getEquivalentVGPRClass(
138 const TargetRegisterClass *SRC) const;
140 /// \returns A SGPR reg class with the same width as \p SRC
141 const TargetRegisterClass *getEquivalentSGPRClass(
142 const TargetRegisterClass *VRC) const;
144 /// \returns The register class that is used for a sub-register of \p RC for
145 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
147 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
148 unsigned SubIdx) const;
150 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
152 const TargetRegisterClass *SrcRC,
153 unsigned SrcSubReg) const override;
155 /// \returns True if operands defined with this operand type can accept
156 /// a literal constant (i.e. any 32-bit immediate).
157 bool opCanUseLiteralConstant(unsigned OpType) const {
158 // TODO: 64-bit operands have extending behavior from 32-bit literal.
159 return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
160 OpType <= AMDGPU::OPERAND_REG_IMM_LAST;
163 /// \returns True if operands defined with this operand type can accept
164 /// an inline constant. i.e. An integer value in the range (-16, 64) or
165 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
166 bool opCanUseInlineConstant(unsigned OpType) const {
167 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
168 OpType <= AMDGPU::OPERAND_SRC_LAST;
171 enum PreloadedValue {
173 PRIVATE_SEGMENT_BUFFER = 0,
176 KERNARG_SEGMENT_PTR = 3,
178 FLAT_SCRATCH_INIT = 5,
182 PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
185 FIRST_VGPR_VALUE = 15,
186 WORKITEM_ID_X = FIRST_VGPR_VALUE,
191 /// \brief Returns the physical register that \p Value is stored in.
192 unsigned getPreloadedValue(const MachineFunction &MF,
193 enum PreloadedValue Value) const;
195 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
196 const TargetRegisterClass *RC,
197 const MachineFunction &MF) const;
199 unsigned getSGPRPressureSet() const { return SGPRSetID; };
200 unsigned getVGPRPressureSet() const { return VGPRSetID; };
202 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
204 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
206 bool isSGPRPressureSet(unsigned SetID) const {
207 return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
209 bool isVGPRPressureSet(unsigned SetID) const {
210 return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
213 ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
214 unsigned EltSize) const;
216 bool shouldCoalesce(MachineInstr *MI,
217 const TargetRegisterClass *SrcRC,
219 const TargetRegisterClass *DstRC,
221 const TargetRegisterClass *NewRC) const override;
223 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
224 MachineFunction &MF) const override;
226 unsigned getRegPressureSetLimit(const MachineFunction &MF,
227 unsigned Idx) const override;
229 const int *getRegUnitPressureSets(unsigned RegUnit) const override;
232 void buildSpillLoadStore(MachineBasicBlock::iterator MI,
233 unsigned LoadStoreOp,
237 unsigned ScratchRsrcReg,
238 unsigned ScratchOffsetReg,
240 MachineMemOperand *MMO,
241 RegScavenger *RS) const;
244 } // End namespace llvm