1 //===-- SIRegisterInfo.h - SI Register Info Interface ----------*- C++ -*--===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 /// \brief Interface definition for SIRegisterInfo
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
16 #define LLVM_LIB_TARGET_AMDGPU_SIREGISTERINFO_H
18 #include "AMDGPURegisterInfo.h"
19 #include "SIDefines.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 class MachineRegisterInfo;
26 class SIMachineFunctionInfo;
28 class SIRegisterInfo final : public AMDGPURegisterInfo {
32 BitVector SGPRPressureSets;
33 BitVector VGPRPressureSets;
35 void reserveRegisterTuples(BitVector &, unsigned Reg) const;
36 void classifyPressureSet(unsigned PSetID, unsigned Reg,
37 BitVector &PressureSets) const;
42 /// Return the end register initially reserved for the scratch buffer in case
43 /// spilling is needed.
44 unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
46 /// Return the end register initially reserved for the scratch wave offset in
47 /// case spilling is needed.
48 unsigned reservedPrivateSegmentWaveByteOffsetReg(
49 const MachineFunction &MF) const;
51 BitVector getReservedRegs(const MachineFunction &MF) const override;
53 bool requiresRegisterScavenging(const MachineFunction &Fn) const override;
55 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
56 bool requiresFrameIndexReplacementScavenging(
57 const MachineFunction &MF) const override;
58 bool requiresVirtualBaseRegisters(const MachineFunction &Fn) const override;
59 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
61 int64_t getMUBUFInstrOffset(const MachineInstr *MI) const;
63 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
64 int Idx) const override;
66 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
68 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
69 unsigned BaseReg, int FrameIdx,
70 int64_t Offset) const override;
72 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
73 int64_t Offset) const override;
75 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
76 int64_t Offset) const override;
78 const TargetRegisterClass *getPointerRegClass(
79 const MachineFunction &MF, unsigned Kind = 0) const override;
81 void spillSGPR(MachineBasicBlock::iterator MI,
82 int FI, RegScavenger *RS) const;
84 void restoreSGPR(MachineBasicBlock::iterator MI,
85 int FI, RegScavenger *RS) const;
87 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
88 unsigned FIOperandNum,
89 RegScavenger *RS) const override;
91 unsigned getHWRegIndex(unsigned Reg) const {
92 return getEncodingValue(Reg) & 0xff;
95 /// \brief Return the 'base' register class for this register.
96 /// e.g. SGPR0 => SReg_32, VGPR => VGPR_32 SGPR0_SGPR1 -> SReg_32, etc.
97 const TargetRegisterClass *getPhysRegClass(unsigned Reg) const;
99 /// \returns true if this class contains only SGPR registers
100 bool isSGPRClass(const TargetRegisterClass *RC) const {
101 return !hasVGPRs(RC);
104 /// \returns true if this class ID contains only SGPR registers
105 bool isSGPRClassID(unsigned RCID) const {
106 return isSGPRClass(getRegClass(RCID));
109 bool isSGPRReg(const MachineRegisterInfo &MRI, unsigned Reg) const {
110 const TargetRegisterClass *RC;
111 if (TargetRegisterInfo::isVirtualRegister(Reg))
112 RC = MRI.getRegClass(Reg);
114 RC = getPhysRegClass(Reg);
115 return isSGPRClass(RC);
118 /// \returns true if this class contains VGPR registers.
119 bool hasVGPRs(const TargetRegisterClass *RC) const;
121 /// \returns A VGPR reg class with the same width as \p SRC
122 const TargetRegisterClass *getEquivalentVGPRClass(
123 const TargetRegisterClass *SRC) const;
125 /// \returns A SGPR reg class with the same width as \p SRC
126 const TargetRegisterClass *getEquivalentSGPRClass(
127 const TargetRegisterClass *VRC) const;
129 /// \returns The register class that is used for a sub-register of \p RC for
130 /// the given \p SubIdx. If \p SubIdx equals NoSubRegister, \p RC will
132 const TargetRegisterClass *getSubRegClass(const TargetRegisterClass *RC,
133 unsigned SubIdx) const;
135 bool shouldRewriteCopySrc(const TargetRegisterClass *DefRC,
137 const TargetRegisterClass *SrcRC,
138 unsigned SrcSubReg) const override;
140 /// \returns True if operands defined with this operand type can accept
141 /// a literal constant (i.e. any 32-bit immediate).
142 bool opCanUseLiteralConstant(unsigned OpType) const {
143 // TODO: 64-bit operands have extending behavior from 32-bit literal.
144 return OpType >= AMDGPU::OPERAND_REG_IMM_FIRST &&
145 OpType <= AMDGPU::OPERAND_REG_IMM_LAST;
148 /// \returns True if operands defined with this operand type can accept
149 /// an inline constant. i.e. An integer value in the range (-16, 64) or
150 /// -4.0f, -2.0f, -1.0f, -0.5f, 0.0f, 0.5f, 1.0f, 2.0f, 4.0f.
151 bool opCanUseInlineConstant(unsigned OpType) const {
152 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
153 OpType <= AMDGPU::OPERAND_SRC_LAST;
156 enum PreloadedValue {
158 PRIVATE_SEGMENT_BUFFER = 0,
161 KERNARG_SEGMENT_PTR = 3,
163 FLAT_SCRATCH_INIT = 5,
167 PRIVATE_SEGMENT_WAVE_BYTE_OFFSET = 14,
170 FIRST_VGPR_VALUE = 15,
171 WORKITEM_ID_X = FIRST_VGPR_VALUE,
176 /// \brief Returns the physical register that \p Value is stored in.
177 unsigned getPreloadedValue(const MachineFunction &MF,
178 enum PreloadedValue Value) const;
180 unsigned findUnusedRegister(const MachineRegisterInfo &MRI,
181 const TargetRegisterClass *RC,
182 const MachineFunction &MF) const;
184 unsigned getSGPRPressureSet() const { return SGPRSetID; };
185 unsigned getVGPRPressureSet() const { return VGPRSetID; };
187 const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
189 bool isVGPR(const MachineRegisterInfo &MRI, unsigned Reg) const;
191 bool isSGPRPressureSet(unsigned SetID) const {
192 return SGPRPressureSets.test(SetID) && !VGPRPressureSets.test(SetID);
194 bool isVGPRPressureSet(unsigned SetID) const {
195 return VGPRPressureSets.test(SetID) && !SGPRPressureSets.test(SetID);
198 /// \returns SGPR allocation granularity supported by the subtarget.
199 unsigned getSGPRAllocGranule() const {
203 /// \returns Total number of SGPRs supported by the subtarget.
204 unsigned getTotalNumSGPRs(const SISubtarget &ST) const;
206 /// \returns Number of addressable SGPRs supported by the subtarget.
207 unsigned getNumAddressableSGPRs(const SISubtarget &ST) const;
209 /// \returns Number of reserved SGPRs supported by the subtarget.
210 unsigned getNumReservedSGPRs(const SISubtarget &ST,
211 const SIMachineFunctionInfo &MFI) const;
213 /// \returns Minimum number of SGPRs that meets given number of waves per
214 /// execution unit requirement for given subtarget.
215 unsigned getMinNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU) const;
217 /// \returns Maximum number of SGPRs that meets given number of waves per
218 /// execution unit requirement for given subtarget.
219 unsigned getMaxNumSGPRs(const SISubtarget &ST, unsigned WavesPerEU,
220 bool Addressable) const;
222 /// \returns Maximum number of SGPRs that meets number of waves per execution
223 /// unit requirement for function \p MF, or number of SGPRs explicitly
224 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
226 /// \returns Value that meets number of waves per execution unit requirement
227 /// if explicitly requested value cannot be converted to integer, violates
228 /// subtarget's specifications, or does not meet number of waves per execution
229 /// unit requirement.
230 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
232 /// \returns VGPR allocation granularity supported by the subtarget.
233 unsigned getVGPRAllocGranule() const {
237 /// \returns Total number of VGPRs supported by the subtarget.
238 unsigned getTotalNumVGPRs() const {
242 /// \returns Number of reserved VGPRs for debugger use supported by the
244 unsigned getNumDebuggerReservedVGPRs(const SISubtarget &ST) const;
246 /// \returns Minimum number of SGPRs that meets given number of waves per
247 /// execution unit requirement.
248 unsigned getMinNumVGPRs(unsigned WavesPerEU) const;
250 /// \returns Maximum number of VGPRs that meets given number of waves per
251 /// execution unit requirement.
252 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const;
254 /// \returns Maximum number of VGPRs that meets number of waves per execution
255 /// unit requirement for function \p MF, or number of VGPRs explicitly
256 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
258 /// \returns Value that meets number of waves per execution unit requirement
259 /// if explicitly requested value cannot be converted to integer, violates
260 /// subtarget's specifications, or does not meet number of waves per execution
261 /// unit requirement.
262 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
264 ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
265 unsigned EltSize) const;
268 void buildSpillLoadStore(MachineBasicBlock::iterator MI,
269 unsigned LoadStoreOp,
273 unsigned ScratchRsrcReg,
274 unsigned ScratchOffsetReg,
276 MachineMemOperand *MMO,
277 RegScavenger *RS) const;
280 } // End namespace llvm