1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the SI registers
12 //===----------------------------------------------------------------------===//
13 class SIReg <string n, bits<16> regIdx = 0> : Register<n>,
14 DwarfRegNum<[!cast<int>(HWEncoding)]> {
15 let Namespace = "AMDGPU";
17 // This is the not yet the complete register encoding. An additional
18 // bit is set for VGPRs.
19 let HWEncoding = regIdx;
23 def VCC_LO : SIReg<"vcc_lo", 106>;
24 def VCC_HI : SIReg<"vcc_hi", 107>;
26 // VCC for 64-bit instructions
27 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
28 DwarfRegAlias<VCC_LO> {
29 let Namespace = "AMDGPU";
30 let SubRegIndices = [sub0, sub1];
34 def EXEC_LO : SIReg<"exec_lo", 126>;
35 def EXEC_HI : SIReg<"exec_hi", 127>;
37 def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>,
38 DwarfRegAlias<EXEC_LO> {
39 let Namespace = "AMDGPU";
40 let SubRegIndices = [sub0, sub1];
44 def SCC : SIReg<"scc", 253>;
45 def M0 : SIReg <"m0", 124>;
47 // Trap handler registers
48 def TBA_LO : SIReg<"tba_lo", 108>;
49 def TBA_HI : SIReg<"tba_hi", 109>;
51 def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>,
52 DwarfRegAlias<TBA_LO> {
53 let Namespace = "AMDGPU";
54 let SubRegIndices = [sub0, sub1];
58 def TMA_LO : SIReg<"tma_lo", 110>;
59 def TMA_HI : SIReg<"tma_hi", 111>;
61 def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>,
62 DwarfRegAlias<TMA_LO> {
63 let Namespace = "AMDGPU";
64 let SubRegIndices = [sub0, sub1];
68 def TTMP0 : SIReg <"ttmp0", 112>;
69 def TTMP1 : SIReg <"ttmp1", 113>;
70 def TTMP2 : SIReg <"ttmp2", 114>;
71 def TTMP3 : SIReg <"ttmp3", 115>;
72 def TTMP4 : SIReg <"ttmp4", 116>;
73 def TTMP5 : SIReg <"ttmp5", 117>;
74 def TTMP6 : SIReg <"ttmp6", 118>;
75 def TTMP7 : SIReg <"ttmp7", 119>;
76 def TTMP8 : SIReg <"ttmp8", 120>;
77 def TTMP9 : SIReg <"ttmp9", 121>;
78 def TTMP10 : SIReg <"ttmp10", 122>;
79 def TTMP11 : SIReg <"ttmp11", 123>;
81 multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
82 def _ci : SIReg<n, ci_e>;
83 def _vi : SIReg<n, vi_e>;
84 def "" : SIReg<"", 0>;
87 class FlatReg <Register lo, Register hi, bits<16> encoding> :
88 RegisterWithSubRegs<"flat_scratch", [lo, hi]>,
90 let Namespace = "AMDGPU";
91 let SubRegIndices = [sub0, sub1];
92 let HWEncoding = encoding;
95 defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes.
96 defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.
98 def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;
99 def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;
100 def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
103 foreach Index = 0-103 in {
104 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
108 foreach Index = 0-255 in {
109 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
110 let HWEncoding{8} = 1;
114 //===----------------------------------------------------------------------===//
115 // Groupings using register classes and tuples
116 //===----------------------------------------------------------------------===//
118 def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
120 let isAllocatable = 0;
123 def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> {
125 let isAllocatable = 0;
128 // TODO: Do we need to set DwarfRegAlias on register tuples?
130 // SGPR 32-bit registers
131 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
132 (add (sequence "SGPR%u", 0, 103))> {
133 // Give all SGPR classes higher priority than VGPR classes, because
134 // we want to spill SGPRs to VGPRs.
135 let AllocationPriority = 7;
138 // SGPR 64-bit registers
139 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
140 [(add (decimate SGPR_32, 2)),
141 (add (decimate (shl SGPR_32, 1), 2))]>;
143 // SGPR 128-bit registers
144 def SGPR_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
145 [(add (decimate SGPR_32, 4)),
146 (add (decimate (shl SGPR_32, 1), 4)),
147 (add (decimate (shl SGPR_32, 2), 4)),
148 (add (decimate (shl SGPR_32, 3), 4))]>;
150 // SGPR 256-bit registers
151 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
152 [(add (decimate SGPR_32, 4)),
153 (add (decimate (shl SGPR_32, 1), 4)),
154 (add (decimate (shl SGPR_32, 2), 4)),
155 (add (decimate (shl SGPR_32, 3), 4)),
156 (add (decimate (shl SGPR_32, 4), 4)),
157 (add (decimate (shl SGPR_32, 5), 4)),
158 (add (decimate (shl SGPR_32, 6), 4)),
159 (add (decimate (shl SGPR_32, 7), 4))]>;
161 // SGPR 512-bit registers
162 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
163 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
164 [(add (decimate SGPR_32, 4)),
165 (add (decimate (shl SGPR_32, 1), 4)),
166 (add (decimate (shl SGPR_32, 2), 4)),
167 (add (decimate (shl SGPR_32, 3), 4)),
168 (add (decimate (shl SGPR_32, 4), 4)),
169 (add (decimate (shl SGPR_32, 5), 4)),
170 (add (decimate (shl SGPR_32, 6), 4)),
171 (add (decimate (shl SGPR_32, 7), 4)),
172 (add (decimate (shl SGPR_32, 8), 4)),
173 (add (decimate (shl SGPR_32, 9), 4)),
174 (add (decimate (shl SGPR_32, 10), 4)),
175 (add (decimate (shl SGPR_32, 11), 4)),
176 (add (decimate (shl SGPR_32, 12), 4)),
177 (add (decimate (shl SGPR_32, 13), 4)),
178 (add (decimate (shl SGPR_32, 14), 4)),
179 (add (decimate (shl SGPR_32, 15), 4))]>;
181 // Trap handler TMP 32-bit registers
182 def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
183 (add (sequence "TTMP%u", 0, 11))> {
184 let isAllocatable = 0;
187 // Trap handler TMP 64-bit registers
188 def TTMP_64Regs : RegisterTuples<[sub0, sub1],
189 [(add (decimate TTMP_32, 2)),
190 (add (decimate (shl TTMP_32, 1), 2))]>;
192 // Trap handler TMP 128-bit registers
193 def TTMP_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
194 [(add (decimate TTMP_32, 4)),
195 (add (decimate (shl TTMP_32, 1), 4)),
196 (add (decimate (shl TTMP_32, 2), 4)),
197 (add (decimate (shl TTMP_32, 3), 4))]>;
199 // VGPR 32-bit registers
200 def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
201 (add (sequence "VGPR%u", 0, 255))> {
202 let AllocationPriority = 1;
206 // VGPR 64-bit registers
207 def VGPR_64 : RegisterTuples<[sub0, sub1],
208 [(add (trunc VGPR_32, 255)),
209 (add (shl VGPR_32, 1))]>;
211 // VGPR 96-bit registers
212 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
213 [(add (trunc VGPR_32, 254)),
214 (add (shl VGPR_32, 1)),
215 (add (shl VGPR_32, 2))]>;
217 // VGPR 128-bit registers
218 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
219 [(add (trunc VGPR_32, 253)),
220 (add (shl VGPR_32, 1)),
221 (add (shl VGPR_32, 2)),
222 (add (shl VGPR_32, 3))]>;
224 // VGPR 256-bit registers
225 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
226 [(add (trunc VGPR_32, 249)),
227 (add (shl VGPR_32, 1)),
228 (add (shl VGPR_32, 2)),
229 (add (shl VGPR_32, 3)),
230 (add (shl VGPR_32, 4)),
231 (add (shl VGPR_32, 5)),
232 (add (shl VGPR_32, 6)),
233 (add (shl VGPR_32, 7))]>;
235 // VGPR 512-bit registers
236 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
237 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
238 [(add (trunc VGPR_32, 241)),
239 (add (shl VGPR_32, 1)),
240 (add (shl VGPR_32, 2)),
241 (add (shl VGPR_32, 3)),
242 (add (shl VGPR_32, 4)),
243 (add (shl VGPR_32, 5)),
244 (add (shl VGPR_32, 6)),
245 (add (shl VGPR_32, 7)),
246 (add (shl VGPR_32, 8)),
247 (add (shl VGPR_32, 9)),
248 (add (shl VGPR_32, 10)),
249 (add (shl VGPR_32, 11)),
250 (add (shl VGPR_32, 12)),
251 (add (shl VGPR_32, 13)),
252 (add (shl VGPR_32, 14)),
253 (add (shl VGPR_32, 15))]>;
255 //===----------------------------------------------------------------------===//
256 // Register classes used as source and destination
257 //===----------------------------------------------------------------------===//
259 // Subset of SReg_32 without M0 for SMRD instructions and alike.
260 // See comments in SIInstructions.td for more info.
261 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
262 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
263 TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI)> {
264 let AllocationPriority = 7;
267 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
268 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
269 let AllocationPriority = 7;
272 // Register class for all scalar registers (SGPRs + Special Registers)
273 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
274 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI)> {
275 let AllocationPriority = 7;
278 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)> {
280 let AllocationPriority = 8;
283 def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
284 let isAllocatable = 0;
287 def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
288 (add SGPR_64, VCC, FLAT_SCR, TTMP_64, TBA, TMA)> {
290 let AllocationPriority = 8;
293 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
294 (add SReg_64_XEXEC, EXEC)> {
296 let AllocationPriority = 8;
299 // Requires 2 s_mov_b64 to copy
300 let CopyCost = 2 in {
302 def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)> {
303 let AllocationPriority = 10;
306 def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> {
307 let isAllocatable = 0;
310 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128, TTMP_128)> {
311 let AllocationPriority = 10;
314 } // End CopyCost = 2
316 def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {
317 // Requires 4 s_mov_b64 to copy
319 let AllocationPriority = 11;
322 def SReg_512 : RegisterClass<"AMDGPU", [v64i8, v16i32], 32, (add SGPR_512)> {
323 // Requires 8 s_mov_b64 to copy
325 let AllocationPriority = 12;
328 // Register class for all vector registers (VGPRs + Interploation Registers)
329 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 32, (add VGPR_64)> {
332 // Requires 2 v_mov_b32 to copy
334 let AllocationPriority = 2;
337 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 32, (add VGPR_96)> {
340 // Requires 3 v_mov_b32 to copy
342 let AllocationPriority = 3;
345 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, (add VGPR_128)> {
348 // Requires 4 v_mov_b32 to copy
350 let AllocationPriority = 4;
353 def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add VGPR_256)> {
356 let AllocationPriority = 5;
359 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
362 let AllocationPriority = 6;
365 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
369 def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16], 32,
370 (add VGPR_32, SReg_32)> {
371 let isAllocatable = 0;
374 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
375 let isAllocatable = 0;
378 //===----------------------------------------------------------------------===//
380 //===----------------------------------------------------------------------===//
382 class RegImmMatcher<string name> : AsmOperandClass {
384 let RenderMethod = "addRegOrImmOperands";
387 multiclass SIRegOperand <string rc, string MatchName, string opType> {
388 let OperandNamespace = "AMDGPU" in {
389 def _b16 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
390 let OperandType = opType#"_INT16";
391 let ParserMatchClass = RegImmMatcher<MatchName#"B16">;
392 let DecoderMethod = "decodeOperand_VSrc16";
395 def _f16 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
396 let OperandType = opType#"_FP16";
397 let ParserMatchClass = RegImmMatcher<MatchName#"F16">;
398 let DecoderMethod = "decodeOperand_VSrc16";
401 def _b32 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
402 let OperandType = opType#"_INT32";
403 let ParserMatchClass = RegImmMatcher<MatchName#"B32">;
406 def _f32 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
407 let OperandType = opType#"_FP32";
408 let ParserMatchClass = RegImmMatcher<MatchName#"F32">;
411 def _b64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> {
412 let OperandType = opType#"_INT64";
413 let ParserMatchClass = RegImmMatcher<MatchName#"B64">;
416 def _f64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> {
417 let OperandType = opType#"_FP64";
418 let ParserMatchClass = RegImmMatcher<MatchName#"F64">;
423 // FIXME: 64-bit sources can sometimes use 32-bit constants.
424 multiclass RegImmOperand <string rc, string MatchName>
425 : SIRegOperand<rc, MatchName, "OPERAND_REG_IMM">;
427 multiclass RegInlineOperand <string rc, string MatchName>
428 : SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">;
430 //===----------------------------------------------------------------------===//
431 // SSrc_* Operands with an SGPR or a 32-bit immediate
432 //===----------------------------------------------------------------------===//
434 defm SSrc : RegImmOperand<"SReg", "SSrc">;
436 //===----------------------------------------------------------------------===//
437 // SCSrc_* Operands with an SGPR or a inline constant
438 //===----------------------------------------------------------------------===//
440 defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ;
442 //===----------------------------------------------------------------------===//
443 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
444 //===----------------------------------------------------------------------===//
446 defm VSrc : RegImmOperand<"VS", "VSrc">;
448 def VSrc_128 : RegisterOperand<VReg_128>;
450 //===----------------------------------------------------------------------===//
451 // VSrc_* Operands with an VGPR
452 //===----------------------------------------------------------------------===//
454 // This is for operands with the enum(9), VSrc encoding restriction,
455 // but only allows VGPRs.
456 def VRegSrc_32 : RegisterOperand<VGPR_32> {
457 //let ParserMatchClass = RegImmMatcher<"VRegSrc32">;
458 let DecoderMethod = "DecodeVS_32RegisterClass";
461 //===----------------------------------------------------------------------===//
462 // VCSrc_* Operands with an SGPR, VGPR or an inline constant
463 //===----------------------------------------------------------------------===//
465 defm VCSrc : RegInlineOperand<"VS", "VCSrc">;