1 //===-- SIRegisterInfo.td - SI Register defs ---------------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Declarations that describe the SI registers
12 //===----------------------------------------------------------------------===//
13 class SIReg <string n, bits<16> regIdx = 0> : Register<n>,
14 DwarfRegNum<[!cast<int>(HWEncoding)]> {
15 let Namespace = "AMDGPU";
17 // This is the not yet the complete register encoding. An additional
18 // bit is set for VGPRs.
19 let HWEncoding = regIdx;
23 def VCC_LO : SIReg<"vcc_lo", 106>;
24 def VCC_HI : SIReg<"vcc_hi", 107>;
26 // VCC for 64-bit instructions
27 def VCC : RegisterWithSubRegs<"vcc", [VCC_LO, VCC_HI]>,
28 DwarfRegAlias<VCC_LO> {
29 let Namespace = "AMDGPU";
30 let SubRegIndices = [sub0, sub1];
34 def EXEC_LO : SIReg<"exec_lo", 126>;
35 def EXEC_HI : SIReg<"exec_hi", 127>;
37 def EXEC : RegisterWithSubRegs<"EXEC", [EXEC_LO, EXEC_HI]>,
38 DwarfRegAlias<EXEC_LO> {
39 let Namespace = "AMDGPU";
40 let SubRegIndices = [sub0, sub1];
44 def SCC : SIReg<"scc", 253>;
45 def M0 : SIReg <"m0", 124>;
47 def SRC_SHARED_BASE : SIReg<"src_shared_base", 235>;
48 def SRC_SHARED_LIMIT : SIReg<"src_shared_limit", 236>;
49 def SRC_PRIVATE_BASE : SIReg<"src_private_base", 237>;
50 def SRC_PRIVATE_LIMIT : SIReg<"src_private_limit", 238>;
52 // Trap handler registers
53 def TBA_LO : SIReg<"tba_lo", 108>;
54 def TBA_HI : SIReg<"tba_hi", 109>;
56 def TBA : RegisterWithSubRegs<"tba", [TBA_LO, TBA_HI]>,
57 DwarfRegAlias<TBA_LO> {
58 let Namespace = "AMDGPU";
59 let SubRegIndices = [sub0, sub1];
63 def TMA_LO : SIReg<"tma_lo", 110>;
64 def TMA_HI : SIReg<"tma_hi", 111>;
66 def TMA : RegisterWithSubRegs<"tma", [TMA_LO, TMA_HI]>,
67 DwarfRegAlias<TMA_LO> {
68 let Namespace = "AMDGPU";
69 let SubRegIndices = [sub0, sub1];
73 def TTMP0 : SIReg <"ttmp0", 112>;
74 def TTMP1 : SIReg <"ttmp1", 113>;
75 def TTMP2 : SIReg <"ttmp2", 114>;
76 def TTMP3 : SIReg <"ttmp3", 115>;
77 def TTMP4 : SIReg <"ttmp4", 116>;
78 def TTMP5 : SIReg <"ttmp5", 117>;
79 def TTMP6 : SIReg <"ttmp6", 118>;
80 def TTMP7 : SIReg <"ttmp7", 119>;
81 def TTMP8 : SIReg <"ttmp8", 120>;
82 def TTMP9 : SIReg <"ttmp9", 121>;
83 def TTMP10 : SIReg <"ttmp10", 122>;
84 def TTMP11 : SIReg <"ttmp11", 123>;
86 multiclass FLAT_SCR_LOHI_m <string n, bits<16> ci_e, bits<16> vi_e> {
87 def _ci : SIReg<n, ci_e>;
88 def _vi : SIReg<n, vi_e>;
89 def "" : SIReg<"", 0>;
92 class FlatReg <Register lo, Register hi, bits<16> encoding> :
93 RegisterWithSubRegs<"flat_scratch", [lo, hi]>,
95 let Namespace = "AMDGPU";
96 let SubRegIndices = [sub0, sub1];
97 let HWEncoding = encoding;
100 defm FLAT_SCR_LO : FLAT_SCR_LOHI_m<"flat_scratch_lo", 104, 102>; // Offset in units of 256-bytes.
101 defm FLAT_SCR_HI : FLAT_SCR_LOHI_m<"flat_scratch_hi", 105, 103>; // Size is the per-thread scratch size, in bytes.
103 def FLAT_SCR_ci : FlatReg<FLAT_SCR_LO_ci, FLAT_SCR_HI_ci, 104>;
104 def FLAT_SCR_vi : FlatReg<FLAT_SCR_LO_vi, FLAT_SCR_HI_vi, 102>;
105 def FLAT_SCR : FlatReg<FLAT_SCR_LO, FLAT_SCR_HI, 0>;
108 foreach Index = 0-103 in {
109 def SGPR#Index : SIReg <"SGPR"#Index, Index>;
113 foreach Index = 0-255 in {
114 def VGPR#Index : SIReg <"VGPR"#Index, Index> {
115 let HWEncoding{8} = 1;
119 //===----------------------------------------------------------------------===//
120 // Groupings using register classes and tuples
121 //===----------------------------------------------------------------------===//
123 def SCC_CLASS : RegisterClass<"AMDGPU", [i1], 1, (add SCC)> {
125 let isAllocatable = 0;
128 def M0_CLASS : RegisterClass<"AMDGPU", [i32], 32, (add M0)> {
130 let isAllocatable = 0;
133 // TODO: Do we need to set DwarfRegAlias on register tuples?
135 // SGPR 32-bit registers
136 def SGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
137 (add (sequence "SGPR%u", 0, 103))> {
138 // Give all SGPR classes higher priority than VGPR classes, because
139 // we want to spill SGPRs to VGPRs.
140 let AllocationPriority = 7;
143 // SGPR 64-bit registers
144 def SGPR_64Regs : RegisterTuples<[sub0, sub1],
145 [(add (decimate SGPR_32, 2)),
146 (add (decimate (shl SGPR_32, 1), 2))]>;
148 // SGPR 128-bit registers
149 def SGPR_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
150 [(add (decimate SGPR_32, 4)),
151 (add (decimate (shl SGPR_32, 1), 4)),
152 (add (decimate (shl SGPR_32, 2), 4)),
153 (add (decimate (shl SGPR_32, 3), 4))]>;
155 // SGPR 256-bit registers
156 def SGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
157 [(add (decimate SGPR_32, 4)),
158 (add (decimate (shl SGPR_32, 1), 4)),
159 (add (decimate (shl SGPR_32, 2), 4)),
160 (add (decimate (shl SGPR_32, 3), 4)),
161 (add (decimate (shl SGPR_32, 4), 4)),
162 (add (decimate (shl SGPR_32, 5), 4)),
163 (add (decimate (shl SGPR_32, 6), 4)),
164 (add (decimate (shl SGPR_32, 7), 4))]>;
166 // SGPR 512-bit registers
167 def SGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
168 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
169 [(add (decimate SGPR_32, 4)),
170 (add (decimate (shl SGPR_32, 1), 4)),
171 (add (decimate (shl SGPR_32, 2), 4)),
172 (add (decimate (shl SGPR_32, 3), 4)),
173 (add (decimate (shl SGPR_32, 4), 4)),
174 (add (decimate (shl SGPR_32, 5), 4)),
175 (add (decimate (shl SGPR_32, 6), 4)),
176 (add (decimate (shl SGPR_32, 7), 4)),
177 (add (decimate (shl SGPR_32, 8), 4)),
178 (add (decimate (shl SGPR_32, 9), 4)),
179 (add (decimate (shl SGPR_32, 10), 4)),
180 (add (decimate (shl SGPR_32, 11), 4)),
181 (add (decimate (shl SGPR_32, 12), 4)),
182 (add (decimate (shl SGPR_32, 13), 4)),
183 (add (decimate (shl SGPR_32, 14), 4)),
184 (add (decimate (shl SGPR_32, 15), 4))]>;
186 // Trap handler TMP 32-bit registers
187 def TTMP_32 : RegisterClass<"AMDGPU", [i32, f32, v2i16, v2f16], 32,
188 (add (sequence "TTMP%u", 0, 11))> {
189 let isAllocatable = 0;
192 // Trap handler TMP 64-bit registers
193 def TTMP_64Regs : RegisterTuples<[sub0, sub1],
194 [(add (decimate TTMP_32, 2)),
195 (add (decimate (shl TTMP_32, 1), 2))]>;
197 // Trap handler TMP 128-bit registers
198 def TTMP_128Regs : RegisterTuples<[sub0, sub1, sub2, sub3],
199 [(add (decimate TTMP_32, 4)),
200 (add (decimate (shl TTMP_32, 1), 4)),
201 (add (decimate (shl TTMP_32, 2), 4)),
202 (add (decimate (shl TTMP_32, 3), 4))]>;
204 // VGPR 32-bit registers
205 // i16/f16 only on VI+
206 def VGPR_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
207 (add (sequence "VGPR%u", 0, 255))> {
208 let AllocationPriority = 1;
212 // VGPR 64-bit registers
213 def VGPR_64 : RegisterTuples<[sub0, sub1],
214 [(add (trunc VGPR_32, 255)),
215 (add (shl VGPR_32, 1))]>;
217 // VGPR 96-bit registers
218 def VGPR_96 : RegisterTuples<[sub0, sub1, sub2],
219 [(add (trunc VGPR_32, 254)),
220 (add (shl VGPR_32, 1)),
221 (add (shl VGPR_32, 2))]>;
223 // VGPR 128-bit registers
224 def VGPR_128 : RegisterTuples<[sub0, sub1, sub2, sub3],
225 [(add (trunc VGPR_32, 253)),
226 (add (shl VGPR_32, 1)),
227 (add (shl VGPR_32, 2)),
228 (add (shl VGPR_32, 3))]>;
230 // VGPR 256-bit registers
231 def VGPR_256 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7],
232 [(add (trunc VGPR_32, 249)),
233 (add (shl VGPR_32, 1)),
234 (add (shl VGPR_32, 2)),
235 (add (shl VGPR_32, 3)),
236 (add (shl VGPR_32, 4)),
237 (add (shl VGPR_32, 5)),
238 (add (shl VGPR_32, 6)),
239 (add (shl VGPR_32, 7))]>;
241 // VGPR 512-bit registers
242 def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
243 sub8, sub9, sub10, sub11, sub12, sub13, sub14, sub15],
244 [(add (trunc VGPR_32, 241)),
245 (add (shl VGPR_32, 1)),
246 (add (shl VGPR_32, 2)),
247 (add (shl VGPR_32, 3)),
248 (add (shl VGPR_32, 4)),
249 (add (shl VGPR_32, 5)),
250 (add (shl VGPR_32, 6)),
251 (add (shl VGPR_32, 7)),
252 (add (shl VGPR_32, 8)),
253 (add (shl VGPR_32, 9)),
254 (add (shl VGPR_32, 10)),
255 (add (shl VGPR_32, 11)),
256 (add (shl VGPR_32, 12)),
257 (add (shl VGPR_32, 13)),
258 (add (shl VGPR_32, 14)),
259 (add (shl VGPR_32, 15))]>;
261 //===----------------------------------------------------------------------===//
262 // Register classes used as source and destination
263 //===----------------------------------------------------------------------===//
265 // Subset of SReg_32 without M0 for SMRD instructions and alike.
266 // See comments in SIInstructions.td for more info.
267 def SReg_32_XM0_XEXEC : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
268 (add SGPR_32, VCC_LO, VCC_HI, FLAT_SCR_LO, FLAT_SCR_HI,
269 TTMP_32, TMA_LO, TMA_HI, TBA_LO, TBA_HI, SRC_SHARED_BASE, SRC_SHARED_LIMIT,
270 SRC_PRIVATE_BASE, SRC_PRIVATE_LIMIT)> {
271 let AllocationPriority = 7;
274 def SReg_32_XM0 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
275 (add SReg_32_XM0_XEXEC, EXEC_LO, EXEC_HI)> {
276 let AllocationPriority = 7;
279 // Register class for all scalar registers (SGPRs + Special Registers)
280 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
281 (add SReg_32_XM0, M0_CLASS, EXEC_LO, EXEC_HI)> {
282 let AllocationPriority = 7;
285 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add SGPR_64Regs)> {
287 let AllocationPriority = 8;
290 def TTMP_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 32, (add TTMP_64Regs)> {
291 let isAllocatable = 0;
294 def SReg_64_XEXEC : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
295 (add SGPR_64, VCC, FLAT_SCR, TTMP_64, TBA, TMA)> {
297 let AllocationPriority = 8;
300 def SReg_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64, i1], 32,
301 (add SReg_64_XEXEC, EXEC)> {
303 let AllocationPriority = 8;
306 // Requires 2 s_mov_b64 to copy
307 let CopyCost = 2 in {
309 def SGPR_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128Regs)> {
310 let AllocationPriority = 10;
313 def TTMP_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add TTMP_128Regs)> {
314 let isAllocatable = 0;
317 def SReg_128 : RegisterClass<"AMDGPU", [v4i32, v16i8, v2i64], 32, (add SGPR_128, TTMP_128)> {
318 let AllocationPriority = 10;
321 } // End CopyCost = 2
323 def SReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add SGPR_256)> {
324 // Requires 4 s_mov_b64 to copy
326 let AllocationPriority = 11;
329 def SReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add SGPR_512)> {
330 // Requires 8 s_mov_b64 to copy
332 let AllocationPriority = 12;
335 // Register class for all vector registers (VGPRs + Interploation Registers)
336 def VReg_64 : RegisterClass<"AMDGPU", [i64, f64, v2i32, v2f32], 32, (add VGPR_64)> {
339 // Requires 2 v_mov_b32 to copy
341 let AllocationPriority = 2;
344 def VReg_96 : RegisterClass<"AMDGPU", [untyped], 32, (add VGPR_96)> {
347 // Requires 3 v_mov_b32 to copy
349 let AllocationPriority = 3;
352 def VReg_128 : RegisterClass<"AMDGPU", [v4i32, v4f32, v2i64, v2f64], 32, (add VGPR_128)> {
355 // Requires 4 v_mov_b32 to copy
357 let AllocationPriority = 4;
360 def VReg_256 : RegisterClass<"AMDGPU", [v8i32, v8f32], 32, (add VGPR_256)> {
363 let AllocationPriority = 5;
366 def VReg_512 : RegisterClass<"AMDGPU", [v16i32, v16f32], 32, (add VGPR_512)> {
369 let AllocationPriority = 6;
372 def VReg_1 : RegisterClass<"AMDGPU", [i1], 32, (add VGPR_32)> {
376 def VS_32 : RegisterClass<"AMDGPU", [i32, f32, i16, f16, v2i16, v2f16], 32,
377 (add VGPR_32, SReg_32)> {
378 let isAllocatable = 0;
381 def VS_64 : RegisterClass<"AMDGPU", [i64, f64], 32, (add VReg_64, SReg_64)> {
382 let isAllocatable = 0;
385 //===----------------------------------------------------------------------===//
387 //===----------------------------------------------------------------------===//
389 class RegImmMatcher<string name> : AsmOperandClass {
391 let RenderMethod = "addRegOrImmOperands";
394 multiclass SIRegOperand <string rc, string MatchName, string opType> {
395 let OperandNamespace = "AMDGPU" in {
396 def _b16 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
397 let OperandType = opType#"_INT16";
398 let ParserMatchClass = RegImmMatcher<MatchName#"B16">;
399 let DecoderMethod = "decodeOperand_VSrc16";
402 def _f16 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
403 let OperandType = opType#"_FP16";
404 let ParserMatchClass = RegImmMatcher<MatchName#"F16">;
405 let DecoderMethod = "decodeOperand_VSrc16";
408 def _b32 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
409 let OperandType = opType#"_INT32";
410 let ParserMatchClass = RegImmMatcher<MatchName#"B32">;
413 def _f32 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
414 let OperandType = opType#"_FP32";
415 let ParserMatchClass = RegImmMatcher<MatchName#"F32">;
418 def _b64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> {
419 let OperandType = opType#"_INT64";
420 let ParserMatchClass = RegImmMatcher<MatchName#"B64">;
423 def _f64 : RegisterOperand<!cast<RegisterClass>(rc#"_64")> {
424 let OperandType = opType#"_FP64";
425 let ParserMatchClass = RegImmMatcher<MatchName#"F64">;
428 def _v2b16 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
429 let OperandType = opType#"_V2INT16";
430 let ParserMatchClass = RegImmMatcher<MatchName#"V2B16">;
431 let DecoderMethod = "decodeOperand_VSrcV216";
434 def _v2f16 : RegisterOperand<!cast<RegisterClass>(rc#"_32")> {
435 let OperandType = opType#"_V2FP16";
436 let ParserMatchClass = RegImmMatcher<MatchName#"V2F16">;
437 let DecoderMethod = "decodeOperand_VSrcV216";
442 // FIXME: 64-bit sources can sometimes use 32-bit constants.
443 multiclass RegImmOperand <string rc, string MatchName>
444 : SIRegOperand<rc, MatchName, "OPERAND_REG_IMM">;
446 multiclass RegInlineOperand <string rc, string MatchName>
447 : SIRegOperand<rc, MatchName, "OPERAND_REG_INLINE_C">;
449 //===----------------------------------------------------------------------===//
450 // SSrc_* Operands with an SGPR or a 32-bit immediate
451 //===----------------------------------------------------------------------===//
453 defm SSrc : RegImmOperand<"SReg", "SSrc">;
455 //===----------------------------------------------------------------------===//
456 // SCSrc_* Operands with an SGPR or a inline constant
457 //===----------------------------------------------------------------------===//
459 defm SCSrc : RegInlineOperand<"SReg", "SCSrc"> ;
461 //===----------------------------------------------------------------------===//
462 // VSrc_* Operands with an SGPR, VGPR or a 32-bit immediate
463 //===----------------------------------------------------------------------===//
465 defm VSrc : RegImmOperand<"VS", "VSrc">;
467 def VSrc_128 : RegisterOperand<VReg_128>;
469 //===----------------------------------------------------------------------===//
470 // VSrc_* Operands with an VGPR
471 //===----------------------------------------------------------------------===//
473 // This is for operands with the enum(9), VSrc encoding restriction,
474 // but only allows VGPRs.
475 def VRegSrc_32 : RegisterOperand<VGPR_32> {
476 //let ParserMatchClass = RegImmMatcher<"VRegSrc32">;
477 let DecoderMethod = "DecodeVS_32RegisterClass";
480 //===----------------------------------------------------------------------===//
481 // VCSrc_* Operands with an SGPR, VGPR or an inline constant
482 //===----------------------------------------------------------------------===//
484 defm VCSrc : RegInlineOperand<"VS", "VCSrc">;