1 //===-- SISchedule.td - SI Scheduling definitons -------------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // MachineModel definitions for Southern Islands (SI)
12 //===----------------------------------------------------------------------===//
14 def : PredicateProlog<[{
15 const SIInstrInfo *TII =
16 static_cast<const SIInstrInfo*>(SchedModel->getInstrInfo());
20 def WriteBranch : SchedWrite;
21 def WriteExport : SchedWrite;
22 def WriteLDS : SchedWrite;
23 def WriteSALU : SchedWrite;
24 def WriteSMEM : SchedWrite;
25 def WriteVMEM : SchedWrite;
26 def WriteBarrier : SchedWrite;
28 // Vector ALU instructions
29 def Write32Bit : SchedWrite;
30 def WriteQuarterRate32 : SchedWrite;
31 def WriteFullOrQuarterRate32 : SchedWrite;
33 def WriteFloatFMA : SchedWrite;
35 // Slow quarter rate f64 instruction.
36 def WriteDouble : SchedWrite;
38 // half rate f64 instruction (same as v_add_f64)
39 def WriteDoubleAdd : SchedWrite;
41 // Half rate 64-bit instructions.
42 def Write64Bit : SchedWrite;
44 // FIXME: Should there be a class for instructions which are VALU
45 // instructions and have VALU rates, but write to the SALU (i.e. VOPC
48 class SISchedMachineModel : SchedMachineModel {
49 let CompleteModel = 0;
51 let PostRAScheduler = 1;
54 def SIFullSpeedModel : SISchedMachineModel;
55 def SIQuarterSpeedModel : SISchedMachineModel;
57 // XXX: Are the resource counts correct?
58 def HWBranch : ProcResource<1> {
61 def HWExport : ProcResource<1> {
62 let BufferSize = 7; // Taken from S_WAITCNT
64 def HWLGKM : ProcResource<1> {
65 let BufferSize = 31; // Taken from S_WAITCNT
67 def HWSALU : ProcResource<1> {
70 def HWVMEM : ProcResource<1> {
71 let BufferSize = 15; // Taken from S_WAITCNT
73 def HWVALU : ProcResource<1> {
77 class HWWriteRes<SchedWrite write, list<ProcResourceKind> resources,
78 int latency> : WriteRes<write, resources> {
79 let Latency = latency;
82 class HWVALUWriteRes<SchedWrite write, int latency> :
83 HWWriteRes<write, [HWVALU], latency>;
86 // The latency numbers are taken from AMD Accelerated Parallel Processing
87 // guide. They may not be accurate.
89 // The latency values are 1 / (operations / cycle) / 4.
90 multiclass SICommonWriteRes {
92 def : HWWriteRes<WriteBranch, [HWBranch], 8>;
93 def : HWWriteRes<WriteExport, [HWExport], 4>;
94 def : HWWriteRes<WriteLDS, [HWLGKM], 5>; // Can be between 2 and 64
95 def : HWWriteRes<WriteSALU, [HWSALU], 1>;
96 def : HWWriteRes<WriteSMEM, [HWLGKM], 5>;
97 def : HWWriteRes<WriteVMEM, [HWVMEM], 80>;
98 def : HWWriteRes<WriteBarrier, [HWBranch], 500>; // XXX: Guessed ???
100 def : HWVALUWriteRes<Write32Bit, 1>;
101 def : HWVALUWriteRes<Write64Bit, 2>;
102 def : HWVALUWriteRes<WriteQuarterRate32, 4>;
105 def PredIsVGPR32Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) <= 32}]>;
106 def PredIsVGPR64Copy : SchedPredicate<[{TII->isVGPRCopy(*MI) && TII->getOpSize(*MI, 0) > 32}]>;
107 def WriteCopy : SchedWriteVariant<[
108 SchedVar<PredIsVGPR32Copy, [Write32Bit]>,
109 SchedVar<PredIsVGPR64Copy, [Write64Bit]>,
110 SchedVar<NoSchedPred, [WriteSALU]>]>;
112 let SchedModel = SIFullSpeedModel in {
114 defm : SICommonWriteRes;
116 def : HWVALUWriteRes<WriteFloatFMA, 1>;
117 def : HWVALUWriteRes<WriteDouble, 4>;
118 def : HWVALUWriteRes<WriteDoubleAdd, 2>;
120 def : InstRW<[WriteCopy], (instrs COPY)>;
122 } // End SchedModel = SIFullSpeedModel
124 let SchedModel = SIQuarterSpeedModel in {
126 defm : SICommonWriteRes;
128 def : HWVALUWriteRes<WriteFloatFMA, 16>;
129 def : HWVALUWriteRes<WriteDouble, 16>;
130 def : HWVALUWriteRes<WriteDoubleAdd, 8>;
132 def : InstRW<[WriteCopy], (instrs COPY)>;
134 } // End SchedModel = SIQuarterSpeedModel