1 //===-- SIWholeQuadMode.cpp - enter and suspend whole quad mode -----------===//
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
7 //===----------------------------------------------------------------------===//
10 /// This pass adds instructions to enable whole quad mode for pixel
11 /// shaders, and whole wavefront mode for all programs.
13 /// Whole quad mode is required for derivative computations, but it interferes
14 /// with shader side effects (stores and atomics). This pass is run on the
15 /// scheduled machine IR but before register coalescing, so that machine SSA is
16 /// available for analysis. It ensures that WQM is enabled when necessary, but
17 /// disabled around stores and atomics.
19 /// When necessary, this pass creates a function prolog
21 /// S_MOV_B64 LiveMask, EXEC
22 /// S_WQM_B64 EXEC, EXEC
24 /// to enter WQM at the top of the function and surrounds blocks of Exact
27 /// S_AND_SAVEEXEC_B64 Tmp, LiveMask
29 /// S_MOV_B64 EXEC, Tmp
31 /// We also compute when a sequence of instructions requires Whole Wavefront
32 /// Mode (WWM) and insert instructions to save and restore it:
34 /// S_OR_SAVEEXEC_B64 Tmp, -1
36 /// S_MOV_B64 EXEC, Tmp
38 /// In order to avoid excessive switching during sequences of Exact
39 /// instructions, the pass first analyzes which instructions must be run in WQM
40 /// (aka which instructions produce values that lead to derivative
43 /// Basic blocks are always exited in WQM as long as some successor needs WQM.
45 /// There is room for improvement given better control flow analysis:
47 /// (1) at the top level (outside of control flow statements, and as long as
48 /// kill hasn't been used), one SGPR can be saved by recovering WQM from
49 /// the LiveMask (this is implemented for the entry block).
51 /// (2) when entire regions (e.g. if-else blocks or entire loops) only
52 /// consist of exact and don't-care instructions, the switch only has to
53 /// be done at the entry and exit points rather than potentially in each
54 /// block of the region.
56 //===----------------------------------------------------------------------===//
59 #include "AMDGPUSubtarget.h"
60 #include "SIInstrInfo.h"
61 #include "SIMachineFunctionInfo.h"
62 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
63 #include "llvm/ADT/DenseMap.h"
64 #include "llvm/ADT/PostOrderIterator.h"
65 #include "llvm/ADT/SmallVector.h"
66 #include "llvm/ADT/StringRef.h"
67 #include "llvm/CodeGen/LiveInterval.h"
68 #include "llvm/CodeGen/LiveIntervals.h"
69 #include "llvm/CodeGen/MachineBasicBlock.h"
70 #include "llvm/CodeGen/MachineFunction.h"
71 #include "llvm/CodeGen/MachineFunctionPass.h"
72 #include "llvm/CodeGen/MachineInstr.h"
73 #include "llvm/CodeGen/MachineInstrBuilder.h"
74 #include "llvm/CodeGen/MachineOperand.h"
75 #include "llvm/CodeGen/MachineRegisterInfo.h"
76 #include "llvm/CodeGen/SlotIndexes.h"
77 #include "llvm/CodeGen/TargetRegisterInfo.h"
78 #include "llvm/IR/CallingConv.h"
79 #include "llvm/IR/DebugLoc.h"
80 #include "llvm/MC/MCRegisterInfo.h"
81 #include "llvm/Pass.h"
82 #include "llvm/Support/Debug.h"
83 #include "llvm/Support/raw_ostream.h"
89 #define DEBUG_TYPE "si-wqm"
103 explicit PrintState(int State) : State(State) {}
107 static raw_ostream &operator<<(raw_ostream &OS, const PrintState &PS) {
108 if (PS.State & StateWQM)
110 if (PS.State & StateWWM) {
111 if (PS.State & StateWQM)
115 if (PS.State & StateExact) {
116 if (PS.State & (StateWQM | StateWWM))
138 MachineBasicBlock *MBB = nullptr;
139 MachineInstr *MI = nullptr;
141 WorkItem() = default;
142 WorkItem(MachineBasicBlock *MBB) : MBB(MBB) {}
143 WorkItem(MachineInstr *MI) : MI(MI) {}
146 class SIWholeQuadMode : public MachineFunctionPass {
148 CallingConv::ID CallingConv;
149 const SIInstrInfo *TII;
150 const SIRegisterInfo *TRI;
151 const GCNSubtarget *ST;
152 MachineRegisterInfo *MRI;
155 DenseMap<const MachineInstr *, InstrInfo> Instructions;
156 DenseMap<MachineBasicBlock *, BlockInfo> Blocks;
157 SmallVector<MachineInstr *, 1> LiveMaskQueries;
158 SmallVector<MachineInstr *, 4> LowerToCopyInstrs;
162 void markInstruction(MachineInstr &MI, char Flag,
163 std::vector<WorkItem> &Worklist);
164 void markInstructionUses(const MachineInstr &MI, char Flag,
165 std::vector<WorkItem> &Worklist);
166 char scanInstructions(MachineFunction &MF, std::vector<WorkItem> &Worklist);
167 void propagateInstruction(MachineInstr &MI, std::vector<WorkItem> &Worklist);
168 void propagateBlock(MachineBasicBlock &MBB, std::vector<WorkItem> &Worklist);
169 char analyzeFunction(MachineFunction &MF);
171 bool requiresCorrectState(const MachineInstr &MI) const;
173 MachineBasicBlock::iterator saveSCC(MachineBasicBlock &MBB,
174 MachineBasicBlock::iterator Before);
175 MachineBasicBlock::iterator
176 prepareInsertion(MachineBasicBlock &MBB, MachineBasicBlock::iterator First,
177 MachineBasicBlock::iterator Last, bool PreferLast,
179 void toExact(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
180 unsigned SaveWQM, unsigned LiveMaskReg);
181 void toWQM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
183 void toWWM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
185 void fromWWM(MachineBasicBlock &MBB, MachineBasicBlock::iterator Before,
187 void processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg, bool isEntry);
189 void lowerLiveMaskQueries(unsigned LiveMaskReg);
190 void lowerCopyInstrs();
196 MachineFunctionPass(ID) { }
198 bool runOnMachineFunction(MachineFunction &MF) override;
200 StringRef getPassName() const override { return "SI Whole Quad Mode"; }
202 void getAnalysisUsage(AnalysisUsage &AU) const override {
203 AU.addRequired<LiveIntervals>();
204 AU.addPreserved<SlotIndexes>();
205 AU.addPreserved<LiveIntervals>();
206 AU.setPreservesCFG();
207 MachineFunctionPass::getAnalysisUsage(AU);
211 } // end anonymous namespace
213 char SIWholeQuadMode::ID = 0;
215 INITIALIZE_PASS_BEGIN(SIWholeQuadMode, DEBUG_TYPE, "SI Whole Quad Mode", false,
217 INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
218 INITIALIZE_PASS_END(SIWholeQuadMode, DEBUG_TYPE, "SI Whole Quad Mode", false,
221 char &llvm::SIWholeQuadModeID = SIWholeQuadMode::ID;
223 FunctionPass *llvm::createSIWholeQuadModePass() {
224 return new SIWholeQuadMode;
228 LLVM_DUMP_METHOD void SIWholeQuadMode::printInfo() {
229 for (const auto &BII : Blocks) {
231 << printMBBReference(*BII.first) << ":\n"
232 << " InNeeds = " << PrintState(BII.second.InNeeds)
233 << ", Needs = " << PrintState(BII.second.Needs)
234 << ", OutNeeds = " << PrintState(BII.second.OutNeeds) << "\n\n";
236 for (const MachineInstr &MI : *BII.first) {
237 auto III = Instructions.find(&MI);
238 if (III == Instructions.end())
241 dbgs() << " " << MI << " Needs = " << PrintState(III->second.Needs)
242 << ", OutNeeds = " << PrintState(III->second.OutNeeds) << '\n';
248 void SIWholeQuadMode::markInstruction(MachineInstr &MI, char Flag,
249 std::vector<WorkItem> &Worklist) {
250 InstrInfo &II = Instructions[&MI];
252 assert(!(Flag & StateExact) && Flag != 0);
254 // Remove any disabled states from the flag. The user that required it gets
255 // an undefined value in the helper lanes. For example, this can happen if
256 // the result of an atomic is used by instruction that requires WQM, where
257 // ignoring the request for WQM is correct as per the relevant specs.
258 Flag &= ~II.Disabled;
260 // Ignore if the flag is already encompassed by the existing needs, or we
261 // just disabled everything.
262 if ((II.Needs & Flag) == Flag)
266 Worklist.push_back(&MI);
269 /// Mark all instructions defining the uses in \p MI with \p Flag.
270 void SIWholeQuadMode::markInstructionUses(const MachineInstr &MI, char Flag,
271 std::vector<WorkItem> &Worklist) {
272 for (const MachineOperand &Use : MI.uses()) {
273 if (!Use.isReg() || !Use.isUse())
276 unsigned Reg = Use.getReg();
278 // Handle physical registers that we need to track; this is mostly relevant
279 // for VCC, which can appear as the (implicit) input of a uniform branch,
280 // e.g. when a loop counter is stored in a VGPR.
281 if (!TargetRegisterInfo::isVirtualRegister(Reg)) {
282 if (Reg == AMDGPU::EXEC || Reg == AMDGPU::EXEC_LO)
285 for (MCRegUnitIterator RegUnit(Reg, TRI); RegUnit.isValid(); ++RegUnit) {
286 LiveRange &LR = LIS->getRegUnit(*RegUnit);
287 const VNInfo *Value = LR.Query(LIS->getInstructionIndex(MI)).valueIn();
291 // Since we're in machine SSA, we do not need to track physical
292 // registers across basic blocks.
293 if (Value->isPHIDef())
296 markInstruction(*LIS->getInstructionFromIndex(Value->def), Flag,
303 for (MachineInstr &DefMI : MRI->def_instructions(Use.getReg()))
304 markInstruction(DefMI, Flag, Worklist);
308 // Scan instructions to determine which ones require an Exact execmask and
309 // which ones seed WQM requirements.
310 char SIWholeQuadMode::scanInstructions(MachineFunction &MF,
311 std::vector<WorkItem> &Worklist) {
312 char GlobalFlags = 0;
313 bool WQMOutputs = MF.getFunction().hasFnAttribute("amdgpu-ps-wqm-outputs");
314 SmallVector<MachineInstr *, 4> SetInactiveInstrs;
316 // We need to visit the basic blocks in reverse post-order so that we visit
317 // defs before uses, in particular so that we don't accidentally mark an
318 // instruction as needing e.g. WQM before visiting it and realizing it needs
320 ReversePostOrderTraversal<MachineFunction *> RPOT(&MF);
321 for (auto BI = RPOT.begin(), BE = RPOT.end(); BI != BE; ++BI) {
322 MachineBasicBlock &MBB = **BI;
323 BlockInfo &BBI = Blocks[&MBB];
325 for (auto II = MBB.begin(), IE = MBB.end(); II != IE; ++II) {
326 MachineInstr &MI = *II;
327 InstrInfo &III = Instructions[&MI];
328 unsigned Opcode = MI.getOpcode();
331 if (TII->isWQM(Opcode)) {
332 // Sampling instructions don't need to produce results for all pixels
333 // in a quad, they just require all inputs of a quad to have been
334 // computed for derivatives.
335 markInstructionUses(MI, StateWQM, Worklist);
336 GlobalFlags |= StateWQM;
338 } else if (Opcode == AMDGPU::WQM) {
339 // The WQM intrinsic requires its output to have all the helper lanes
340 // correct, so we need it to be in WQM.
342 LowerToCopyInstrs.push_back(&MI);
343 } else if (Opcode == AMDGPU::WWM) {
344 // The WWM intrinsic doesn't make the same guarantee, and plus it needs
345 // to be executed in WQM or Exact so that its copy doesn't clobber
347 markInstructionUses(MI, StateWWM, Worklist);
348 GlobalFlags |= StateWWM;
349 LowerToCopyInstrs.push_back(&MI);
351 } else if (Opcode == AMDGPU::V_SET_INACTIVE_B32 ||
352 Opcode == AMDGPU::V_SET_INACTIVE_B64) {
353 III.Disabled = StateWWM;
354 MachineOperand &Inactive = MI.getOperand(2);
355 if (Inactive.isReg()) {
356 if (Inactive.isUndef()) {
357 LowerToCopyInstrs.push_back(&MI);
359 unsigned Reg = Inactive.getReg();
360 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
361 for (MachineInstr &DefMI : MRI->def_instructions(Reg))
362 markInstruction(DefMI, StateWWM, Worklist);
366 SetInactiveInstrs.push_back(&MI);
368 } else if (TII->isDisableWQM(MI)) {
369 BBI.Needs |= StateExact;
370 if (!(BBI.InNeeds & StateExact)) {
371 BBI.InNeeds |= StateExact;
372 Worklist.push_back(&MBB);
374 GlobalFlags |= StateExact;
375 III.Disabled = StateWQM | StateWWM;
378 if (Opcode == AMDGPU::SI_PS_LIVE) {
379 LiveMaskQueries.push_back(&MI);
380 } else if (WQMOutputs) {
381 // The function is in machine SSA form, which means that physical
382 // VGPRs correspond to shader inputs and outputs. Inputs are
383 // only used, outputs are only defined.
384 for (const MachineOperand &MO : MI.defs()) {
388 unsigned Reg = MO.getReg();
390 if (!TRI->isVirtualRegister(Reg) &&
391 TRI->hasVectorRegisters(TRI->getPhysRegClass(Reg))) {
402 markInstruction(MI, Flags, Worklist);
403 GlobalFlags |= Flags;
407 // Mark sure that any SET_INACTIVE instructions are computed in WQM if WQM is
408 // ever used anywhere in the function. This implements the corresponding
409 // semantics of @llvm.amdgcn.set.inactive.
410 if (GlobalFlags & StateWQM) {
411 for (MachineInstr *MI : SetInactiveInstrs)
412 markInstruction(*MI, StateWQM, Worklist);
418 void SIWholeQuadMode::propagateInstruction(MachineInstr &MI,
419 std::vector<WorkItem>& Worklist) {
420 MachineBasicBlock *MBB = MI.getParent();
421 InstrInfo II = Instructions[&MI]; // take a copy to prevent dangling references
422 BlockInfo &BI = Blocks[MBB];
424 // Control flow-type instructions and stores to temporary memory that are
425 // followed by WQM computations must themselves be in WQM.
426 if ((II.OutNeeds & StateWQM) && !(II.Disabled & StateWQM) &&
427 (MI.isTerminator() || (TII->usesVM_CNT(MI) && MI.mayStore()))) {
428 Instructions[&MI].Needs = StateWQM;
432 // Propagate to block level
433 if (II.Needs & StateWQM) {
434 BI.Needs |= StateWQM;
435 if (!(BI.InNeeds & StateWQM)) {
436 BI.InNeeds |= StateWQM;
437 Worklist.push_back(MBB);
441 // Propagate backwards within block
442 if (MachineInstr *PrevMI = MI.getPrevNode()) {
443 char InNeeds = (II.Needs & ~StateWWM) | II.OutNeeds;
444 if (!PrevMI->isPHI()) {
445 InstrInfo &PrevII = Instructions[PrevMI];
446 if ((PrevII.OutNeeds | InNeeds) != PrevII.OutNeeds) {
447 PrevII.OutNeeds |= InNeeds;
448 Worklist.push_back(PrevMI);
453 // Propagate WQM flag to instruction inputs
454 assert(!(II.Needs & StateExact));
457 markInstructionUses(MI, II.Needs, Worklist);
459 // Ensure we process a block containing WWM, even if it does not require any
461 if (II.Needs & StateWWM)
462 BI.Needs |= StateWWM;
465 void SIWholeQuadMode::propagateBlock(MachineBasicBlock &MBB,
466 std::vector<WorkItem>& Worklist) {
467 BlockInfo BI = Blocks[&MBB]; // Make a copy to prevent dangling references.
469 // Propagate through instructions
471 MachineInstr *LastMI = &*MBB.rbegin();
472 InstrInfo &LastII = Instructions[LastMI];
473 if ((LastII.OutNeeds | BI.OutNeeds) != LastII.OutNeeds) {
474 LastII.OutNeeds |= BI.OutNeeds;
475 Worklist.push_back(LastMI);
479 // Predecessor blocks must provide for our WQM/Exact needs.
480 for (MachineBasicBlock *Pred : MBB.predecessors()) {
481 BlockInfo &PredBI = Blocks[Pred];
482 if ((PredBI.OutNeeds | BI.InNeeds) == PredBI.OutNeeds)
485 PredBI.OutNeeds |= BI.InNeeds;
486 PredBI.InNeeds |= BI.InNeeds;
487 Worklist.push_back(Pred);
490 // All successors must be prepared to accept the same set of WQM/Exact data.
491 for (MachineBasicBlock *Succ : MBB.successors()) {
492 BlockInfo &SuccBI = Blocks[Succ];
493 if ((SuccBI.InNeeds | BI.OutNeeds) == SuccBI.InNeeds)
496 SuccBI.InNeeds |= BI.OutNeeds;
497 Worklist.push_back(Succ);
501 char SIWholeQuadMode::analyzeFunction(MachineFunction &MF) {
502 std::vector<WorkItem> Worklist;
503 char GlobalFlags = scanInstructions(MF, Worklist);
505 while (!Worklist.empty()) {
506 WorkItem WI = Worklist.back();
510 propagateInstruction(*WI.MI, Worklist);
512 propagateBlock(*WI.MBB, Worklist);
518 /// Whether \p MI really requires the exec state computed during analysis.
520 /// Scalar instructions must occasionally be marked WQM for correct propagation
521 /// (e.g. thread masks leading up to branches), but when it comes to actual
522 /// execution, they don't care about EXEC.
523 bool SIWholeQuadMode::requiresCorrectState(const MachineInstr &MI) const {
524 if (MI.isTerminator())
527 // Skip instructions that are not affected by EXEC
528 if (TII->isScalarUnit(MI))
531 // Generic instructions such as COPY will either disappear by register
532 // coalescing or be lowered to SALU or VALU instructions.
533 if (MI.isTransient()) {
534 if (MI.getNumExplicitOperands() >= 1) {
535 const MachineOperand &Op = MI.getOperand(0);
537 if (TRI->isSGPRReg(*MRI, Op.getReg())) {
538 // SGPR instructions are not affected by EXEC
548 MachineBasicBlock::iterator
549 SIWholeQuadMode::saveSCC(MachineBasicBlock &MBB,
550 MachineBasicBlock::iterator Before) {
551 unsigned SaveReg = MRI->createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
554 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), SaveReg)
555 .addReg(AMDGPU::SCC);
556 MachineInstr *Restore =
557 BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), AMDGPU::SCC)
560 LIS->InsertMachineInstrInMaps(*Save);
561 LIS->InsertMachineInstrInMaps(*Restore);
562 LIS->createAndComputeVirtRegInterval(SaveReg);
567 // Return an iterator in the (inclusive) range [First, Last] at which
568 // instructions can be safely inserted, keeping in mind that some of the
569 // instructions we want to add necessarily clobber SCC.
570 MachineBasicBlock::iterator SIWholeQuadMode::prepareInsertion(
571 MachineBasicBlock &MBB, MachineBasicBlock::iterator First,
572 MachineBasicBlock::iterator Last, bool PreferLast, bool SaveSCC) {
574 return PreferLast ? Last : First;
576 LiveRange &LR = LIS->getRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));
577 auto MBBE = MBB.end();
578 SlotIndex FirstIdx = First != MBBE ? LIS->getInstructionIndex(*First)
579 : LIS->getMBBEndIdx(&MBB);
581 Last != MBBE ? LIS->getInstructionIndex(*Last) : LIS->getMBBEndIdx(&MBB);
582 SlotIndex Idx = PreferLast ? LastIdx : FirstIdx;
583 const LiveRange::Segment *S;
586 S = LR.getSegmentContaining(Idx);
591 SlotIndex Next = S->start.getBaseIndex();
596 SlotIndex Next = S->end.getNextIndex().getBaseIndex();
603 MachineBasicBlock::iterator MBBI;
605 if (MachineInstr *MI = LIS->getInstructionFromIndex(Idx))
608 assert(Idx == LIS->getMBBEndIdx(&MBB));
613 MBBI = saveSCC(MBB, MBBI);
618 void SIWholeQuadMode::toExact(MachineBasicBlock &MBB,
619 MachineBasicBlock::iterator Before,
620 unsigned SaveWQM, unsigned LiveMaskReg) {
624 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
625 AMDGPU::S_AND_SAVEEXEC_B32 : AMDGPU::S_AND_SAVEEXEC_B64),
627 .addReg(LiveMaskReg);
629 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
630 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
631 AMDGPU::S_AND_B32 : AMDGPU::S_AND_B64),
634 .addReg(LiveMaskReg);
637 LIS->InsertMachineInstrInMaps(*MI);
640 void SIWholeQuadMode::toWQM(MachineBasicBlock &MBB,
641 MachineBasicBlock::iterator Before,
645 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
647 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::COPY), Exec)
650 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(ST->isWave32() ?
651 AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64),
656 LIS->InsertMachineInstrInMaps(*MI);
659 void SIWholeQuadMode::toWWM(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator Before,
665 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::ENTER_WWM), SaveOrig)
667 LIS->InsertMachineInstrInMaps(*MI);
670 void SIWholeQuadMode::fromWWM(MachineBasicBlock &MBB,
671 MachineBasicBlock::iterator Before,
672 unsigned SavedOrig) {
676 MI = BuildMI(MBB, Before, DebugLoc(), TII->get(AMDGPU::EXIT_WWM),
677 ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC)
679 LIS->InsertMachineInstrInMaps(*MI);
682 void SIWholeQuadMode::processBlock(MachineBasicBlock &MBB, unsigned LiveMaskReg,
684 auto BII = Blocks.find(&MBB);
685 if (BII == Blocks.end())
688 const BlockInfo &BI = BII->second;
690 // This is a non-entry block that is WQM throughout, so no need to do
692 if (!isEntry && BI.Needs == StateWQM && BI.OutNeeds != StateExact)
695 LLVM_DEBUG(dbgs() << "\nProcessing block " << printMBBReference(MBB)
698 unsigned SavedWQMReg = 0;
699 unsigned SavedNonWWMReg = 0;
700 bool WQMFromExec = isEntry;
701 char State = (isEntry || !(BI.InNeeds & StateWQM)) ? StateExact : StateWQM;
702 char NonWWMState = 0;
703 const TargetRegisterClass *BoolRC = TRI->getBoolRC();
705 auto II = MBB.getFirstNonPHI(), IE = MBB.end();
707 ++II; // Skip the instruction that saves LiveMask
709 // This stores the first instruction where it's safe to switch from WQM to
710 // Exact or vice versa.
711 MachineBasicBlock::iterator FirstWQM = IE;
713 // This stores the first instruction where it's safe to switch from WWM to
714 // Exact/WQM or to switch to WWM. It must always be the same as, or after,
715 // FirstWQM since if it's safe to switch to/from WWM, it must be safe to
716 // switch to/from WQM as well.
717 MachineBasicBlock::iterator FirstWWM = IE;
719 MachineBasicBlock::iterator Next = II;
720 char Needs = StateExact | StateWQM; // WWM is disabled by default
729 // First, figure out the allowed states (Needs) based on the propagated
732 MachineInstr &MI = *II;
734 if (requiresCorrectState(MI)) {
735 auto III = Instructions.find(&MI);
736 if (III != Instructions.end()) {
737 if (III->second.Needs & StateWWM)
739 else if (III->second.Needs & StateWQM)
742 Needs &= ~III->second.Disabled;
743 OutNeeds = III->second.OutNeeds;
746 // If the instruction doesn't actually need a correct EXEC, then we can
747 // safely leave WWM enabled.
748 Needs = StateExact | StateWQM | StateWWM;
751 if (MI.isTerminator() && OutNeeds == StateExact)
754 if (MI.getOpcode() == AMDGPU::SI_ELSE && BI.OutNeeds == StateExact)
755 MI.getOperand(3).setImm(1);
759 // End of basic block
760 if (BI.OutNeeds & StateWQM)
762 else if (BI.OutNeeds == StateExact)
765 Needs = StateWQM | StateExact;
768 // Now, transition if necessary.
769 if (!(Needs & State)) {
770 MachineBasicBlock::iterator First;
771 if (State == StateWWM || Needs == StateWWM) {
772 // We must switch to or from WWM
775 // We only need to switch to/from WQM, so we can use FirstWQM
779 MachineBasicBlock::iterator Before =
780 prepareInsertion(MBB, First, II, Needs == StateWQM,
781 Needs == StateExact || WQMFromExec);
783 if (State == StateWWM) {
784 assert(SavedNonWWMReg);
785 fromWWM(MBB, Before, SavedNonWWMReg);
789 if (Needs == StateWWM) {
791 SavedNonWWMReg = MRI->createVirtualRegister(BoolRC);
792 toWWM(MBB, Before, SavedNonWWMReg);
795 if (State == StateWQM && (Needs & StateExact) && !(Needs & StateWQM)) {
796 if (!WQMFromExec && (OutNeeds & StateWQM))
797 SavedWQMReg = MRI->createVirtualRegister(BoolRC);
799 toExact(MBB, Before, SavedWQMReg, LiveMaskReg);
801 } else if (State == StateExact && (Needs & StateWQM) &&
802 !(Needs & StateExact)) {
803 assert(WQMFromExec == (SavedWQMReg == 0));
805 toWQM(MBB, Before, SavedWQMReg);
808 LIS->createAndComputeVirtRegInterval(SavedWQMReg);
813 // We can get here if we transitioned from WWM to a non-WWM state that
814 // already matches our needs, but we shouldn't need to do anything.
815 assert(Needs & State);
820 if (Needs != (StateExact | StateWQM | StateWWM)) {
821 if (Needs != (StateExact | StateWQM))
832 void SIWholeQuadMode::lowerLiveMaskQueries(unsigned LiveMaskReg) {
833 for (MachineInstr *MI : LiveMaskQueries) {
834 const DebugLoc &DL = MI->getDebugLoc();
835 unsigned Dest = MI->getOperand(0).getReg();
837 BuildMI(*MI->getParent(), MI, DL, TII->get(AMDGPU::COPY), Dest)
838 .addReg(LiveMaskReg);
840 LIS->ReplaceMachineInstrInMaps(*MI, *Copy);
841 MI->eraseFromParent();
845 void SIWholeQuadMode::lowerCopyInstrs() {
846 for (MachineInstr *MI : LowerToCopyInstrs) {
847 for (unsigned i = MI->getNumExplicitOperands() - 1; i > 1; i--)
848 MI->RemoveOperand(i);
850 const unsigned Reg = MI->getOperand(0).getReg();
852 if (TRI->isVGPR(*MRI, Reg)) {
853 const TargetRegisterClass *regClass =
854 TargetRegisterInfo::isVirtualRegister(Reg)
855 ? MRI->getRegClass(Reg)
856 : TRI->getPhysRegClass(Reg);
858 const unsigned MovOp = TII->getMovOpcode(regClass);
859 MI->setDesc(TII->get(MovOp));
861 // And make it implicitly depend on exec (like all VALU movs should do).
862 MI->addOperand(MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
864 MI->setDesc(TII->get(AMDGPU::COPY));
869 bool SIWholeQuadMode::runOnMachineFunction(MachineFunction &MF) {
870 Instructions.clear();
872 LiveMaskQueries.clear();
873 LowerToCopyInstrs.clear();
874 CallingConv = MF.getFunction().getCallingConv();
876 ST = &MF.getSubtarget<GCNSubtarget>();
878 TII = ST->getInstrInfo();
879 TRI = &TII->getRegisterInfo();
880 MRI = &MF.getRegInfo();
881 LIS = &getAnalysis<LiveIntervals>();
883 char GlobalFlags = analyzeFunction(MF);
884 unsigned LiveMaskReg = 0;
885 unsigned Exec = ST->isWave32() ? AMDGPU::EXEC_LO : AMDGPU::EXEC;
886 if (!(GlobalFlags & StateWQM)) {
887 lowerLiveMaskQueries(Exec);
888 if (!(GlobalFlags & StateWWM))
889 return !LiveMaskQueries.empty();
891 // Store a copy of the original live mask when required
892 MachineBasicBlock &Entry = MF.front();
893 MachineBasicBlock::iterator EntryMI = Entry.getFirstNonPHI();
895 if (GlobalFlags & StateExact || !LiveMaskQueries.empty()) {
896 LiveMaskReg = MRI->createVirtualRegister(TRI->getBoolRC());
897 MachineInstr *MI = BuildMI(Entry, EntryMI, DebugLoc(),
898 TII->get(AMDGPU::COPY), LiveMaskReg)
900 LIS->InsertMachineInstrInMaps(*MI);
903 lowerLiveMaskQueries(LiveMaskReg);
905 if (GlobalFlags == StateWQM) {
906 // For a shader that needs only WQM, we can just set it once.
907 BuildMI(Entry, EntryMI, DebugLoc(), TII->get(ST->isWave32() ?
908 AMDGPU::S_WQM_B32 : AMDGPU::S_WQM_B64),
913 // EntryMI may become invalid here
918 LLVM_DEBUG(printInfo());
922 // Handle the general case
923 for (auto BII : Blocks)
924 processBlock(*BII.first, LiveMaskReg, BII.first == &*MF.begin());
926 // Physical registers like SCC aren't tracked by default anyway, so just
927 // removing the ranges we computed is the simplest option for maintaining
928 // the analysis results.
929 LIS->removeRegUnit(*MCRegUnitIterator(AMDGPU::SCC, TRI));