contrib/llvm/lib/Target/AMDGPU/SMInstructions.td

   1 //===---- SMInstructions.td - Scalar Memory Instruction Defintions --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 def smrd_offset_8 : NamedOperandU32<"SMRDOffset8",
  11                                   NamedMatchClass<"SMRDOffset8">> {
  12   let OperandType = "OPERAND_IMMEDIATE";
  13 }
  14
  15 def smrd_offset_20 : NamedOperandU32<"SMRDOffset20",
  16                                   NamedMatchClass<"SMRDOffset20">> {
  17   let OperandType = "OPERAND_IMMEDIATE";
  18 }
  19
  20 //===----------------------------------------------------------------------===//
  21 // Scalar Memory classes
  22 //===----------------------------------------------------------------------===//
  23
  24 class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
  25   InstSI <outs, ins, "", pattern>,
  26   SIMCInstr<opName, SIEncodingFamily.NONE> {
  27   let isPseudo = 1;
  28   let isCodeGenOnly = 1;
  29
  30   let LGKM_CNT = 1;
  31   let SMRD = 1;
  32   let mayStore = 0;
  33   let mayLoad = 1;
  34   let hasSideEffects = 0;
  35   let UseNamedOperandTable = 1;
  36   let SchedRW = [WriteSMEM];
  37   let SubtargetPredicate = isGCN;
  38
  39   string Mnemonic = opName;
  40   string AsmOperands = asmOps;
  41
  42   bits<1> has_sbase = 1;
  43   bits<1> has_sdst = 1;
  44   bit has_glc = 0;
  45   bits<1> has_offset = 1;
  46   bits<1> offset_is_imm = 0;
  47 }
  48
  49 class SM_Real <SM_Pseudo ps>
  50   : InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
  51
  52   let isPseudo = 0;
  53   let isCodeGenOnly = 0;
  54
  55   // copy relevant pseudo op flags
  56   let SubtargetPredicate = ps.SubtargetPredicate;
  57   let AsmMatchConverter  = ps.AsmMatchConverter;
  58
  59   // encoding
  60   bits<7>  sbase;
  61   bits<7>  sdst;
  62   bits<32> offset;
  63   bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
  64 }
  65
  66 class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
  67   : SM_Pseudo<opName, outs, ins, asmOps, pattern> {
  68   RegisterClass BaseClass;
  69   let mayLoad = 1;
  70   let mayStore = 0;
  71   let has_glc = 1;
  72 }
  73
  74 class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []>
  75   : SM_Pseudo<opName, (outs), ins, asmOps, pattern> {
  76   RegisterClass BaseClass;
  77   RegisterClass SrcClass;
  78   let mayLoad = 0;
  79   let mayStore = 1;
  80   let has_glc = 1;
  81   let ScalarStore = 1;
  82 }
  83
  84 multiclass SM_Pseudo_Loads<string opName,
  85                            RegisterClass baseClass,
  86                            RegisterClass dstClass> {
  87   def _IMM  : SM_Load_Pseudo <opName,
  88                               (outs dstClass:$sdst),
  89                               (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc),
  90                               " $sdst, $sbase, $offset$glc", []> {
  91     let offset_is_imm = 1;
  92     let BaseClass = baseClass;
  93     let PseudoInstr = opName # "_IMM";
  94     let has_glc = 1;
  95   }
  96
  97   def _SGPR  : SM_Load_Pseudo <opName,
  98                               (outs dstClass:$sdst),
  99                               (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
 100                               " $sdst, $sbase, $offset$glc", []> {
 101     let BaseClass = baseClass;
 102     let PseudoInstr = opName # "_SGPR";
 103     let has_glc = 1;
 104   }
 105 }
 106
 107 multiclass SM_Pseudo_Stores<string opName,
 108                            RegisterClass baseClass,
 109                            RegisterClass srcClass> {
 110   def _IMM  : SM_Store_Pseudo <opName,
 111     (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc),
 112     " $sdata, $sbase, $offset$glc", []> {
 113     let offset_is_imm = 1;
 114     let BaseClass = baseClass;
 115     let SrcClass = srcClass;
 116     let PseudoInstr = opName # "_IMM";
 117   }
 118
 119   def _SGPR  : SM_Store_Pseudo <opName,
 120     (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
 121     " $sdata, $sbase, $offset$glc", []> {
 122     let BaseClass = baseClass;
 123     let SrcClass = srcClass;
 124     let PseudoInstr = opName # "_SGPR";
 125   }
 126 }
 127
 128 class SM_Time_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
 129   opName, (outs SReg_64_XEXEC:$sdst), (ins),
 130   " $sdst", [(set i64:$sdst, (node))]> {
 131   let hasSideEffects = 1;
 132   // FIXME: mayStore = ? is a workaround for tablegen bug for different
 133   // inferred mayStore flags for the instruction pattern vs. standalone
 134   // Pat. Each considers the other contradictory.
 135   let mayStore = ?;
 136   let mayLoad = ?;
 137   let has_sbase = 0;
 138   let has_offset = 0;
 139 }
 140
 141 class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo<
 142   opName, (outs), (ins), "", [(node)]> {
 143   let hasSideEffects = 1;
 144   let mayStore = 1;
 145   let has_sdst = 0;
 146   let has_sbase = 0;
 147   let has_offset = 0;
 148 }
 149
 150
 151 //===----------------------------------------------------------------------===//
 152 // Scalar Memory Instructions
 153 //===----------------------------------------------------------------------===//
 154
 155 // We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
 156 // SMRD instructions, because the SReg_32_XM0 register class does not include M0
 157 // and writing to M0 from an SMRD instruction will hang the GPU.
 158
 159 // XXX - SMEM instructions do not allow exec for data operand, but
 160 // does sdst for SMRD on SI/CI?
 161 defm S_LOAD_DWORD    : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0_XEXEC>;
 162 defm S_LOAD_DWORDX2  : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64_XEXEC>;
 163 defm S_LOAD_DWORDX4  : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>;
 164 defm S_LOAD_DWORDX8  : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>;
 165 defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>;
 166
 167 defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads <
 168   "s_buffer_load_dword", SReg_128, SReg_32_XM0_XEXEC
 169 >;
 170
 171 // FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on
 172 // SI/CI, bit disallowed for SMEM on VI.
 173 defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads <
 174   "s_buffer_load_dwordx2", SReg_128, SReg_64_XEXEC
 175 >;
 176
 177 defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <
 178   "s_buffer_load_dwordx4", SReg_128, SReg_128
 179 >;
 180
 181 defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <
 182   "s_buffer_load_dwordx8", SReg_128, SReg_256
 183 >;
 184
 185 defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <
 186   "s_buffer_load_dwordx16", SReg_128, SReg_512
 187 >;
 188
 189 defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>;
 190 defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>;
 191 defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>;
 192
 193 defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores <
 194   "s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC
 195 >;
 196
 197 defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores <
 198   "s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC
 199 >;
 200
 201 defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores <
 202   "s_buffer_store_dwordx4", SReg_128, SReg_128
 203 >;
 204
 205
 206 def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
 207 def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
 208
 209 let SubtargetPredicate = isCIVI in {
 210 def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
 211 } // let SubtargetPredicate = isCIVI
 212
 213 let SubtargetPredicate = isVI in {
 214 def S_DCACHE_WB     : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
 215 def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
 216 def S_MEMREALTIME   : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
 217 } // SubtargetPredicate = isVI
 218
 219
 220
 221 //===----------------------------------------------------------------------===//
 222 // Scalar Memory Patterns
 223 //===----------------------------------------------------------------------===//
 224
 225
 226 def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
 227   auto Ld = cast<LoadSDNode>(N);
 228   return Ld->getAlignment() >= 4  &&
 229     ((Ld->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS &&
 230     static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N)) ||
 231     (Subtarget->getScalarizeGlobalBehavior() && Ld->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS &&
 232     !Ld->isVolatile() &&
 233     static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N) &&
 234     static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpHasNoClobberedMemOperand(N)));
 235 }]>;
 236
 237 def SMRDImm         : ComplexPattern<i64, 2, "SelectSMRDImm">;
 238 def SMRDImm32       : ComplexPattern<i64, 2, "SelectSMRDImm32">;
 239 def SMRDSgpr        : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
 240 def SMRDBufferImm   : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
 241 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
 242 def SMRDBufferSgpr  : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
 243
 244 let Predicates = [isGCN] in {
 245
 246 multiclass SMRD_Pattern <string Instr, ValueType vt> {
 247
 248   // 1. IMM offset
 249   def : Pat <
 250     (smrd_load (SMRDImm i64:$sbase, i32:$offset)),
 251     (vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, 0))
 252   >;
 253
 254   // 2. SGPR offset
 255   def : Pat <
 256     (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
 257     (vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0))
 258   >;
 259 }
 260
 261 let Predicates = [isSICI] in {
 262 def : Pat <
 263   (i64 (readcyclecounter)),
 264   (S_MEMTIME)
 265 >;
 266 }
 267
 268 // Global and constant loads can be selected to either MUBUF or SMRD
 269 // instructions, but SMRD instructions are faster so we want the instruction
 270 // selector to prefer those.
 271 let AddedComplexity = 100 in {
 272
 273 defm : SMRD_Pattern <"S_LOAD_DWORD",    i32>;
 274 defm : SMRD_Pattern <"S_LOAD_DWORDX2",  v2i32>;
 275 defm : SMRD_Pattern <"S_LOAD_DWORDX4",  v4i32>;
 276 defm : SMRD_Pattern <"S_LOAD_DWORDX8",  v8i32>;
 277 defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
 278
 279 // 1. Offset as an immediate
 280 def SM_LOAD_PATTERN : Pat <  // name this pattern to reuse AddedComplexity on CI
 281   (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
 282   (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset, 0)
 283 >;
 284
 285 // 2. Offset loaded in an 32bit SGPR
 286 def : Pat <
 287   (SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
 288   (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset, 0)
 289 >;
 290
 291 } // End let AddedComplexity = 100
 292
 293 } // let Predicates = [isGCN]
 294
 295 let Predicates = [isVI] in {
 296
 297 def : Pat <
 298   (i64 (readcyclecounter)),
 299   (S_MEMREALTIME)
 300 >;
 301
 302 } // let Predicates = [isVI]
 303
 304
 305 //===----------------------------------------------------------------------===//
 306 // Targets
 307 //===----------------------------------------------------------------------===//
 308
 309 //===----------------------------------------------------------------------===//
 310 // SI
 311 //===----------------------------------------------------------------------===//
 312
 313 class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
 314   : SM_Real<ps>
 315   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
 316   , Enc32 {
 317
 318   let AssemblerPredicates = [isSICI];
 319   let DecoderNamespace = "SICI";
 320
 321   let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, ?);
 322   let Inst{8}     = imm;
 323   let Inst{14-9}  = !if(ps.has_sbase, sbase{6-1}, ?);
 324   let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
 325   let Inst{26-22} = op;
 326   let Inst{31-27} = 0x18; //encoding
 327 }
 328
 329 // FIXME: Assembler should reject trying to use glc on SMRD
 330 // instructions on SI.
 331 multiclass SM_Real_Loads_si<bits<5> op, string ps,
 332                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
 333                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
 334
 335   def _IMM_si : SMRD_Real_si <op, immPs> {
 336     let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc);
 337   }
 338
 339   // FIXME: The operand name $offset is inconsistent with $soff used
 340   // in the pseudo
 341   def _SGPR_si : SMRD_Real_si <op, sgprPs> {
 342     let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
 343   }
 344
 345 }
 346
 347 defm S_LOAD_DWORD           : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
 348 defm S_LOAD_DWORDX2         : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
 349 defm S_LOAD_DWORDX4         : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
 350 defm S_LOAD_DWORDX8         : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
 351 defm S_LOAD_DWORDX16        : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">;
 352 defm S_BUFFER_LOAD_DWORD    : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">;
 353 defm S_BUFFER_LOAD_DWORDX2  : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">;
 354 defm S_BUFFER_LOAD_DWORDX4  : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">;
 355 defm S_BUFFER_LOAD_DWORDX8  : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">;
 356 defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">;
 357
 358 def S_MEMTIME_si    : SMRD_Real_si <0x1e, S_MEMTIME>;
 359 def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>;
 360
 361
 362 //===----------------------------------------------------------------------===//
 363 // VI
 364 //===----------------------------------------------------------------------===//
 365
 366 class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
 367   : SM_Real<ps>
 368   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
 369   , Enc64 {
 370   bit glc;
 371
 372   let AssemblerPredicates = [isVI];
 373   let DecoderNamespace = "VI";
 374
 375   let Inst{5-0}   = !if(ps.has_sbase, sbase{6-1}, ?);
 376   let Inst{12-6}  = !if(ps.has_sdst, sdst{6-0}, ?);
 377
 378   let Inst{16} = !if(ps.has_glc, glc, ?);
 379   let Inst{17} = imm;
 380   let Inst{25-18} = op;
 381   let Inst{31-26} = 0x30; //encoding
 382   let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?);
 383 }
 384
 385 multiclass SM_Real_Loads_vi<bits<8> op, string ps,
 386                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
 387                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
 388   def _IMM_vi : SMEM_Real_vi <op, immPs> {
 389     let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
 390   }
 391   def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
 392     let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
 393   }
 394 }
 395
 396 class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
 397   // encoding
 398   bits<7> sdata;
 399
 400   let sdst = ?;
 401   let Inst{12-6}  = !if(ps.has_sdst, sdata{6-0}, ?);
 402 }
 403
 404 multiclass SM_Real_Stores_vi<bits<8> op, string ps,
 405                             SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
 406                             SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
 407   // FIXME: The operand name $offset is inconsistent with $soff used
 408   // in the pseudo
 409   def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
 410     let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
 411   }
 412
 413   def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
 414     let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
 415   }
 416 }
 417
 418 defm S_LOAD_DWORD           : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
 419 defm S_LOAD_DWORDX2         : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;
 420 defm S_LOAD_DWORDX4         : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">;
 421 defm S_LOAD_DWORDX8         : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">;
 422 defm S_LOAD_DWORDX16        : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">;
 423 defm S_BUFFER_LOAD_DWORD    : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">;
 424 defm S_BUFFER_LOAD_DWORDX2  : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">;
 425 defm S_BUFFER_LOAD_DWORDX4  : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">;
 426 defm S_BUFFER_LOAD_DWORDX8  : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">;
 427 defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">;
 428
 429 defm S_STORE_DWORD : SM_Real_Stores_vi <0x10, "S_STORE_DWORD">;
 430 defm S_STORE_DWORDX2 : SM_Real_Stores_vi <0x11, "S_STORE_DWORDX2">;
 431 defm S_STORE_DWORDX4 : SM_Real_Stores_vi <0x12, "S_STORE_DWORDX4">;
 432
 433 defm S_BUFFER_STORE_DWORD    : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">;
 434 defm S_BUFFER_STORE_DWORDX2  : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">;
 435 defm S_BUFFER_STORE_DWORDX4  : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">;
 436
 437 // These instructions use same encoding
 438 def S_DCACHE_INV_vi         : SMEM_Real_vi <0x20, S_DCACHE_INV>;
 439 def S_DCACHE_WB_vi          : SMEM_Real_vi <0x21, S_DCACHE_WB>;
 440 def S_DCACHE_INV_VOL_vi     : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
 441 def S_DCACHE_WB_VOL_vi      : SMEM_Real_vi <0x23, S_DCACHE_WB_VOL>;
 442 def S_MEMTIME_vi            : SMEM_Real_vi <0x24, S_MEMTIME>;
 443 def S_MEMREALTIME_vi        : SMEM_Real_vi <0x25, S_MEMREALTIME>;
 444
 445
 446 //===----------------------------------------------------------------------===//
 447 // CI
 448 //===----------------------------------------------------------------------===//
 449
 450 def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
 451                                           NamedMatchClass<"SMRDLiteralOffset">> {
 452   let OperandType = "OPERAND_IMMEDIATE";
 453 }
 454
 455 class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
 456   SM_Real<ps>,
 457   Enc64 {
 458
 459   let AssemblerPredicates = [isCIOnly];
 460   let DecoderNamespace = "CI";
 461   let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc);
 462
 463   let LGKM_CNT = ps.LGKM_CNT;
 464   let SMRD = ps.SMRD;
 465   let mayLoad = ps.mayLoad;
 466   let mayStore = ps.mayStore;
 467   let hasSideEffects = ps.hasSideEffects;
 468   let SchedRW = ps.SchedRW;
 469   let UseNamedOperandTable = ps.UseNamedOperandTable;
 470
 471   let Inst{7-0}   = 0xff;
 472   let Inst{8}     = 0;
 473   let Inst{14-9}  = sbase{6-1};
 474   let Inst{21-15} = sdst{6-0};
 475   let Inst{26-22} = op;
 476   let Inst{31-27} = 0x18; //encoding
 477   let Inst{63-32} = offset{31-0};
 478 }
 479
 480 def S_LOAD_DWORD_IMM_ci           : SMRD_Real_Load_IMM_ci <0x00, S_LOAD_DWORD_IMM>;
 481 def S_LOAD_DWORDX2_IMM_ci         : SMRD_Real_Load_IMM_ci <0x01, S_LOAD_DWORDX2_IMM>;
 482 def S_LOAD_DWORDX4_IMM_ci         : SMRD_Real_Load_IMM_ci <0x02, S_LOAD_DWORDX4_IMM>;
 483 def S_LOAD_DWORDX8_IMM_ci         : SMRD_Real_Load_IMM_ci <0x03, S_LOAD_DWORDX8_IMM>;
 484 def S_LOAD_DWORDX16_IMM_ci        : SMRD_Real_Load_IMM_ci <0x04, S_LOAD_DWORDX16_IMM>;
 485 def S_BUFFER_LOAD_DWORD_IMM_ci    : SMRD_Real_Load_IMM_ci <0x08, S_BUFFER_LOAD_DWORD_IMM>;
 486 def S_BUFFER_LOAD_DWORDX2_IMM_ci  : SMRD_Real_Load_IMM_ci <0x09, S_BUFFER_LOAD_DWORDX2_IMM>;
 487 def S_BUFFER_LOAD_DWORDX4_IMM_ci  : SMRD_Real_Load_IMM_ci <0x0a, S_BUFFER_LOAD_DWORDX4_IMM>;
 488 def S_BUFFER_LOAD_DWORDX8_IMM_ci  : SMRD_Real_Load_IMM_ci <0x0b, S_BUFFER_LOAD_DWORDX8_IMM>;
 489 def S_BUFFER_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x0c, S_BUFFER_LOAD_DWORDX16_IMM>;
 490
 491 class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
 492   : SM_Real<ps>
 493   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
 494   , Enc32 {
 495
 496   let AssemblerPredicates = [isCIOnly];
 497   let DecoderNamespace = "CI";
 498
 499   let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, ?);
 500   let Inst{8}     = imm;
 501   let Inst{14-9}  = !if(ps.has_sbase, sbase{6-1}, ?);
 502   let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
 503   let Inst{26-22} = op;
 504   let Inst{31-27} = 0x18; //encoding
 505 }
 506
 507 def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
 508
 509 let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in {
 510
 511 class SMRD_Pattern_ci <string Instr, ValueType vt> : Pat <
 512   (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
 513   (vt (!cast<SM_Pseudo>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
 514   let Predicates = [isCIOnly];
 515 }
 516
 517 def : SMRD_Pattern_ci <"S_LOAD_DWORD",    i32>;
 518 def : SMRD_Pattern_ci <"S_LOAD_DWORDX2",  v2i32>;
 519 def : SMRD_Pattern_ci <"S_LOAD_DWORDX4",  v4i32>;
 520 def : SMRD_Pattern_ci <"S_LOAD_DWORDX8",  v8i32>;
 521 def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>;
 522
 523 def : Pat <
 524   (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
 525   (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset, 0)> {
 526   let Predicates = [isCI]; // should this be isCIOnly?
 527 }
 528
 529 } // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity
 530