contrib/llvm/lib/Target/AMDGPU/SMInstructions.td

   1 //===---- SMInstructions.td - Scalar Memory Instruction Defintions --------===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9
  10 def smrd_offset_8 : NamedOperandU32<"SMRDOffset8",
  11                                   NamedMatchClass<"SMRDOffset8">> {
  12   let OperandType = "OPERAND_IMMEDIATE";
  13 }
  14
  15 def smrd_offset_20 : NamedOperandU32<"SMRDOffset20",
  16                                   NamedMatchClass<"SMRDOffset20">> {
  17   let OperandType = "OPERAND_IMMEDIATE";
  18 }
  19
  20 //===----------------------------------------------------------------------===//
  21 // Scalar Memory classes
  22 //===----------------------------------------------------------------------===//
  23
  24 class SM_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]> :
  25   InstSI <outs, ins, "", pattern>,
  26   SIMCInstr<opName, SIEncodingFamily.NONE> {
  27   let isPseudo = 1;
  28   let isCodeGenOnly = 1;
  29
  30   let LGKM_CNT = 1;
  31   let SMRD = 1;
  32   let mayStore = 0;
  33   let mayLoad = 1;
  34   let hasSideEffects = 0;
  35   let UseNamedOperandTable = 1;
  36   let SchedRW = [WriteSMEM];
  37   let SubtargetPredicate = isGCN;
  38
  39   string Mnemonic = opName;
  40   string AsmOperands = asmOps;
  41
  42   bits<1> has_sbase = 1;
  43   bits<1> has_sdst = 1;
  44   bit has_glc = 0;
  45   bits<1> has_offset = 1;
  46   bits<1> offset_is_imm = 0;
  47 }
  48
  49 class SM_Real <SM_Pseudo ps>
  50   : InstSI<ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []> {
  51
  52   let isPseudo = 0;
  53   let isCodeGenOnly = 0;
  54
  55   // copy relevant pseudo op flags
  56   let SubtargetPredicate = ps.SubtargetPredicate;
  57   let AsmMatchConverter  = ps.AsmMatchConverter;
  58
  59   // encoding
  60   bits<7>  sbase;
  61   bits<7>  sdst;
  62   bits<32> offset;
  63   bits<1> imm = !if(ps.has_offset, ps.offset_is_imm, 0);
  64 }
  65
  66 class SM_Load_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> pattern=[]>
  67   : SM_Pseudo<opName, outs, ins, asmOps, pattern> {
  68   RegisterClass BaseClass;
  69   let mayLoad = 1;
  70   let mayStore = 0;
  71   let has_glc = 1;
  72 }
  73
  74 class SM_Store_Pseudo <string opName, dag ins, string asmOps, list<dag> pattern = []>
  75   : SM_Pseudo<opName, (outs), ins, asmOps, pattern> {
  76   RegisterClass BaseClass;
  77   RegisterClass SrcClass;
  78   let mayLoad = 0;
  79   let mayStore = 1;
  80   let has_glc = 1;
  81   let ScalarStore = 1;
  82 }
  83
  84 multiclass SM_Pseudo_Loads<string opName,
  85                            RegisterClass baseClass,
  86                            RegisterClass dstClass> {
  87   def _IMM  : SM_Load_Pseudo <opName,
  88                               (outs dstClass:$sdst),
  89                               (ins baseClass:$sbase, i32imm:$offset, i1imm:$glc),
  90                               " $sdst, $sbase, $offset$glc", []> {
  91     let offset_is_imm = 1;
  92     let BaseClass = baseClass;
  93     let PseudoInstr = opName # "_IMM";
  94     let has_glc = 1;
  95   }
  96
  97   def _SGPR  : SM_Load_Pseudo <opName,
  98                               (outs dstClass:$sdst),
  99                               (ins baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
 100                               " $sdst, $sbase, $offset$glc", []> {
 101     let BaseClass = baseClass;
 102     let PseudoInstr = opName # "_SGPR";
 103     let has_glc = 1;
 104   }
 105 }
 106
 107 multiclass SM_Pseudo_Stores<string opName,
 108                            RegisterClass baseClass,
 109                            RegisterClass srcClass> {
 110   def _IMM  : SM_Store_Pseudo <opName,
 111     (ins srcClass:$sdata, baseClass:$sbase, i32imm:$offset, i1imm:$glc),
 112     " $sdata, $sbase, $offset$glc", []> {
 113     let offset_is_imm = 1;
 114     let BaseClass = baseClass;
 115     let SrcClass = srcClass;
 116     let PseudoInstr = opName # "_IMM";
 117   }
 118
 119   def _SGPR  : SM_Store_Pseudo <opName,
 120     (ins srcClass:$sdata, baseClass:$sbase, SReg_32:$soff, i1imm:$glc),
 121     " $sdata, $sbase, $offset$glc", []> {
 122     let BaseClass = baseClass;
 123     let SrcClass = srcClass;
 124     let PseudoInstr = opName # "_SGPR";
 125   }
 126 }
 127
 128 class SM_Time_Pseudo<string opName, SDPatternOperator node> : SM_Pseudo<
 129   opName, (outs SReg_64_XEXEC:$sdst), (ins),
 130   " $sdst", [(set i64:$sdst, (node))]> {
 131   let hasSideEffects = 1;
 132   let mayStore = 0;
 133   let mayLoad = 1;
 134   let has_sbase = 0;
 135   let has_offset = 0;
 136 }
 137
 138 class SM_Inval_Pseudo <string opName, SDPatternOperator node> : SM_Pseudo<
 139   opName, (outs), (ins), "", [(node)]> {
 140   let hasSideEffects = 1;
 141   let mayStore = 1;
 142   let has_sdst = 0;
 143   let has_sbase = 0;
 144   let has_offset = 0;
 145 }
 146
 147
 148 //===----------------------------------------------------------------------===//
 149 // Scalar Memory Instructions
 150 //===----------------------------------------------------------------------===//
 151
 152 // We are using the SReg_32_XM0 and not the SReg_32 register class for 32-bit
 153 // SMRD instructions, because the SReg_32_XM0 register class does not include M0
 154 // and writing to M0 from an SMRD instruction will hang the GPU.
 155
 156 // XXX - SMEM instructions do not allow exec for data operand, but
 157 // does sdst for SMRD on SI/CI?
 158 defm S_LOAD_DWORD    : SM_Pseudo_Loads <"s_load_dword", SReg_64, SReg_32_XM0_XEXEC>;
 159 defm S_LOAD_DWORDX2  : SM_Pseudo_Loads <"s_load_dwordx2", SReg_64, SReg_64_XEXEC>;
 160 defm S_LOAD_DWORDX4  : SM_Pseudo_Loads <"s_load_dwordx4", SReg_64, SReg_128>;
 161 defm S_LOAD_DWORDX8  : SM_Pseudo_Loads <"s_load_dwordx8", SReg_64, SReg_256>;
 162 defm S_LOAD_DWORDX16 : SM_Pseudo_Loads <"s_load_dwordx16", SReg_64, SReg_512>;
 163
 164 defm S_BUFFER_LOAD_DWORD : SM_Pseudo_Loads <
 165   "s_buffer_load_dword", SReg_128, SReg_32_XM0_XEXEC
 166 >;
 167
 168 // FIXME: exec_lo/exec_hi appear to be allowed for SMRD loads on
 169 // SI/CI, bit disallowed for SMEM on VI.
 170 defm S_BUFFER_LOAD_DWORDX2 : SM_Pseudo_Loads <
 171   "s_buffer_load_dwordx2", SReg_128, SReg_64_XEXEC
 172 >;
 173
 174 defm S_BUFFER_LOAD_DWORDX4 : SM_Pseudo_Loads <
 175   "s_buffer_load_dwordx4", SReg_128, SReg_128
 176 >;
 177
 178 defm S_BUFFER_LOAD_DWORDX8 : SM_Pseudo_Loads <
 179   "s_buffer_load_dwordx8", SReg_128, SReg_256
 180 >;
 181
 182 defm S_BUFFER_LOAD_DWORDX16 : SM_Pseudo_Loads <
 183   "s_buffer_load_dwordx16", SReg_128, SReg_512
 184 >;
 185
 186 defm S_STORE_DWORD : SM_Pseudo_Stores <"s_store_dword", SReg_64, SReg_32_XM0_XEXEC>;
 187 defm S_STORE_DWORDX2 : SM_Pseudo_Stores <"s_store_dwordx2", SReg_64, SReg_64_XEXEC>;
 188 defm S_STORE_DWORDX4 : SM_Pseudo_Stores <"s_store_dwordx4", SReg_64, SReg_128>;
 189
 190 defm S_BUFFER_STORE_DWORD : SM_Pseudo_Stores <
 191   "s_buffer_store_dword", SReg_128, SReg_32_XM0_XEXEC
 192 >;
 193
 194 defm S_BUFFER_STORE_DWORDX2 : SM_Pseudo_Stores <
 195   "s_buffer_store_dwordx2", SReg_128, SReg_64_XEXEC
 196 >;
 197
 198 defm S_BUFFER_STORE_DWORDX4 : SM_Pseudo_Stores <
 199   "s_buffer_store_dwordx4", SReg_128, SReg_128
 200 >;
 201
 202
 203 def S_MEMTIME : SM_Time_Pseudo <"s_memtime", int_amdgcn_s_memtime>;
 204 def S_DCACHE_INV : SM_Inval_Pseudo <"s_dcache_inv", int_amdgcn_s_dcache_inv>;
 205
 206 let SubtargetPredicate = isCIVI in {
 207 def S_DCACHE_INV_VOL : SM_Inval_Pseudo <"s_dcache_inv_vol", int_amdgcn_s_dcache_inv_vol>;
 208 } // let SubtargetPredicate = isCIVI
 209
 210 let SubtargetPredicate = isVI in {
 211 def S_DCACHE_WB     : SM_Inval_Pseudo <"s_dcache_wb", int_amdgcn_s_dcache_wb>;
 212 def S_DCACHE_WB_VOL : SM_Inval_Pseudo <"s_dcache_wb_vol", int_amdgcn_s_dcache_wb_vol>;
 213 def S_MEMREALTIME   : SM_Time_Pseudo <"s_memrealtime", int_amdgcn_s_memrealtime>;
 214 } // SubtargetPredicate = isVI
 215
 216
 217
 218 //===----------------------------------------------------------------------===//
 219 // Scalar Memory Patterns
 220 //===----------------------------------------------------------------------===//
 221
 222
 223 def smrd_load : PatFrag <(ops node:$ptr), (load node:$ptr), [{
 224   auto Ld = cast<LoadSDNode>(N);
 225   return Ld->getAlignment() >= 4  &&
 226     ((Ld->getAddressSpace() == AMDGPUASI.CONSTANT_ADDRESS &&
 227     static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N)) ||
 228     (Subtarget->getScalarizeGlobalBehavior() && Ld->getAddressSpace() == AMDGPUASI.GLOBAL_ADDRESS &&
 229     !Ld->isVolatile() &&
 230     static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpUniform(N) &&
 231     static_cast<const SITargetLowering *>(getTargetLowering())->isMemOpHasNoClobberedMemOperand(N)));
 232 }]>;
 233
 234 def SMRDImm         : ComplexPattern<i64, 2, "SelectSMRDImm">;
 235 def SMRDImm32       : ComplexPattern<i64, 2, "SelectSMRDImm32">;
 236 def SMRDSgpr        : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
 237 def SMRDBufferImm   : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
 238 def SMRDBufferImm32 : ComplexPattern<i32, 1, "SelectSMRDBufferImm32">;
 239
 240 multiclass SMRD_Pattern <string Instr, ValueType vt> {
 241
 242   // 1. IMM offset
 243   def : GCNPat <
 244     (smrd_load (SMRDImm i64:$sbase, i32:$offset)),
 245     (vt (!cast<SM_Pseudo>(Instr#"_IMM") $sbase, $offset, 0))
 246   >;
 247
 248   // 2. SGPR offset
 249   def : GCNPat <
 250     (smrd_load (SMRDSgpr i64:$sbase, i32:$offset)),
 251     (vt (!cast<SM_Pseudo>(Instr#"_SGPR") $sbase, $offset, 0))
 252   >;
 253 }
 254
 255 let OtherPredicates = [isSICI] in {
 256 def : GCNPat <
 257   (i64 (readcyclecounter)),
 258   (S_MEMTIME)
 259 >;
 260 }
 261
 262 // Global and constant loads can be selected to either MUBUF or SMRD
 263 // instructions, but SMRD instructions are faster so we want the instruction
 264 // selector to prefer those.
 265 let AddedComplexity = 100 in {
 266
 267 defm : SMRD_Pattern <"S_LOAD_DWORD",    i32>;
 268 defm : SMRD_Pattern <"S_LOAD_DWORDX2",  v2i32>;
 269 defm : SMRD_Pattern <"S_LOAD_DWORDX4",  v4i32>;
 270 defm : SMRD_Pattern <"S_LOAD_DWORDX8",  v8i32>;
 271 defm : SMRD_Pattern <"S_LOAD_DWORDX16", v16i32>;
 272
 273 // 1. Offset as an immediate
 274 def SM_LOAD_PATTERN : GCNPat <  // name this pattern to reuse AddedComplexity on CI
 275   (SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
 276   (S_BUFFER_LOAD_DWORD_IMM $sbase, $offset, 0)
 277 >;
 278
 279 // 2. Offset loaded in an 32bit SGPR
 280 def : GCNPat <
 281   (SIload_constant v4i32:$sbase, i32:$offset),
 282   (S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset, 0)
 283 >;
 284
 285 } // End let AddedComplexity = 100
 286
 287 let OtherPredicates = [isVI] in {
 288
 289 def : GCNPat <
 290   (i64 (readcyclecounter)),
 291   (S_MEMREALTIME)
 292 >;
 293
 294 } // let OtherPredicates = [isVI]
 295
 296
 297 //===----------------------------------------------------------------------===//
 298 // Targets
 299 //===----------------------------------------------------------------------===//
 300
 301 //===----------------------------------------------------------------------===//
 302 // SI
 303 //===----------------------------------------------------------------------===//
 304
 305 class SMRD_Real_si <bits<5> op, SM_Pseudo ps>
 306   : SM_Real<ps>
 307   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
 308   , Enc32 {
 309
 310   let AssemblerPredicates = [isSICI];
 311   let DecoderNamespace = "SICI";
 312
 313   let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, ?);
 314   let Inst{8}     = imm;
 315   let Inst{14-9}  = !if(ps.has_sbase, sbase{6-1}, ?);
 316   let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
 317   let Inst{26-22} = op;
 318   let Inst{31-27} = 0x18; //encoding
 319 }
 320
 321 // FIXME: Assembler should reject trying to use glc on SMRD
 322 // instructions on SI.
 323 multiclass SM_Real_Loads_si<bits<5> op, string ps,
 324                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
 325                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
 326
 327   def _IMM_si : SMRD_Real_si <op, immPs> {
 328     let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_8:$offset, GLC:$glc);
 329   }
 330
 331   // FIXME: The operand name $offset is inconsistent with $soff used
 332   // in the pseudo
 333   def _SGPR_si : SMRD_Real_si <op, sgprPs> {
 334     let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
 335   }
 336
 337 }
 338
 339 defm S_LOAD_DWORD           : SM_Real_Loads_si <0x00, "S_LOAD_DWORD">;
 340 defm S_LOAD_DWORDX2         : SM_Real_Loads_si <0x01, "S_LOAD_DWORDX2">;
 341 defm S_LOAD_DWORDX4         : SM_Real_Loads_si <0x02, "S_LOAD_DWORDX4">;
 342 defm S_LOAD_DWORDX8         : SM_Real_Loads_si <0x03, "S_LOAD_DWORDX8">;
 343 defm S_LOAD_DWORDX16        : SM_Real_Loads_si <0x04, "S_LOAD_DWORDX16">;
 344 defm S_BUFFER_LOAD_DWORD    : SM_Real_Loads_si <0x08, "S_BUFFER_LOAD_DWORD">;
 345 defm S_BUFFER_LOAD_DWORDX2  : SM_Real_Loads_si <0x09, "S_BUFFER_LOAD_DWORDX2">;
 346 defm S_BUFFER_LOAD_DWORDX4  : SM_Real_Loads_si <0x0a, "S_BUFFER_LOAD_DWORDX4">;
 347 defm S_BUFFER_LOAD_DWORDX8  : SM_Real_Loads_si <0x0b, "S_BUFFER_LOAD_DWORDX8">;
 348 defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_si <0x0c, "S_BUFFER_LOAD_DWORDX16">;
 349
 350 def S_MEMTIME_si    : SMRD_Real_si <0x1e, S_MEMTIME>;
 351 def S_DCACHE_INV_si : SMRD_Real_si <0x1f, S_DCACHE_INV>;
 352
 353
 354 //===----------------------------------------------------------------------===//
 355 // VI
 356 //===----------------------------------------------------------------------===//
 357
 358 class SMEM_Real_vi <bits<8> op, SM_Pseudo ps>
 359   : SM_Real<ps>
 360   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
 361   , Enc64 {
 362   bit glc;
 363
 364   let AssemblerPredicates = [isVI];
 365   let DecoderNamespace = "VI";
 366
 367   let Inst{5-0}   = !if(ps.has_sbase, sbase{6-1}, ?);
 368   let Inst{12-6}  = !if(ps.has_sdst, sdst{6-0}, ?);
 369
 370   let Inst{16} = !if(ps.has_glc, glc, ?);
 371   let Inst{17} = imm;
 372   let Inst{25-18} = op;
 373   let Inst{31-26} = 0x30; //encoding
 374   let Inst{51-32} = !if(ps.has_offset, offset{19-0}, ?);
 375 }
 376
 377 multiclass SM_Real_Loads_vi<bits<8> op, string ps,
 378                             SM_Load_Pseudo immPs = !cast<SM_Load_Pseudo>(ps#_IMM),
 379                             SM_Load_Pseudo sgprPs = !cast<SM_Load_Pseudo>(ps#_SGPR)> {
 380   def _IMM_vi : SMEM_Real_vi <op, immPs> {
 381     let InOperandList = (ins immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
 382   }
 383   def _SGPR_vi : SMEM_Real_vi <op, sgprPs> {
 384     let InOperandList = (ins sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
 385   }
 386 }
 387
 388 class SMEM_Real_Store_vi <bits<8> op, SM_Pseudo ps> : SMEM_Real_vi <op, ps> {
 389   // encoding
 390   bits<7> sdata;
 391
 392   let sdst = ?;
 393   let Inst{12-6}  = !if(ps.has_sdst, sdata{6-0}, ?);
 394 }
 395
 396 multiclass SM_Real_Stores_vi<bits<8> op, string ps,
 397                             SM_Store_Pseudo immPs = !cast<SM_Store_Pseudo>(ps#_IMM),
 398                             SM_Store_Pseudo sgprPs = !cast<SM_Store_Pseudo>(ps#_SGPR)> {
 399   // FIXME: The operand name $offset is inconsistent with $soff used
 400   // in the pseudo
 401   def _IMM_vi : SMEM_Real_Store_vi <op, immPs> {
 402     let InOperandList = (ins immPs.SrcClass:$sdata, immPs.BaseClass:$sbase, smrd_offset_20:$offset, GLC:$glc);
 403   }
 404
 405   def _SGPR_vi : SMEM_Real_Store_vi <op, sgprPs> {
 406     let InOperandList = (ins sgprPs.SrcClass:$sdata, sgprPs.BaseClass:$sbase, SReg_32:$offset, GLC:$glc);
 407   }
 408 }
 409
 410 defm S_LOAD_DWORD           : SM_Real_Loads_vi <0x00, "S_LOAD_DWORD">;
 411 defm S_LOAD_DWORDX2         : SM_Real_Loads_vi <0x01, "S_LOAD_DWORDX2">;
 412 defm S_LOAD_DWORDX4         : SM_Real_Loads_vi <0x02, "S_LOAD_DWORDX4">;
 413 defm S_LOAD_DWORDX8         : SM_Real_Loads_vi <0x03, "S_LOAD_DWORDX8">;
 414 defm S_LOAD_DWORDX16        : SM_Real_Loads_vi <0x04, "S_LOAD_DWORDX16">;
 415 defm S_BUFFER_LOAD_DWORD    : SM_Real_Loads_vi <0x08, "S_BUFFER_LOAD_DWORD">;
 416 defm S_BUFFER_LOAD_DWORDX2  : SM_Real_Loads_vi <0x09, "S_BUFFER_LOAD_DWORDX2">;
 417 defm S_BUFFER_LOAD_DWORDX4  : SM_Real_Loads_vi <0x0a, "S_BUFFER_LOAD_DWORDX4">;
 418 defm S_BUFFER_LOAD_DWORDX8  : SM_Real_Loads_vi <0x0b, "S_BUFFER_LOAD_DWORDX8">;
 419 defm S_BUFFER_LOAD_DWORDX16 : SM_Real_Loads_vi <0x0c, "S_BUFFER_LOAD_DWORDX16">;
 420
 421 defm S_STORE_DWORD : SM_Real_Stores_vi <0x10, "S_STORE_DWORD">;
 422 defm S_STORE_DWORDX2 : SM_Real_Stores_vi <0x11, "S_STORE_DWORDX2">;
 423 defm S_STORE_DWORDX4 : SM_Real_Stores_vi <0x12, "S_STORE_DWORDX4">;
 424
 425 defm S_BUFFER_STORE_DWORD    : SM_Real_Stores_vi <0x18, "S_BUFFER_STORE_DWORD">;
 426 defm S_BUFFER_STORE_DWORDX2  : SM_Real_Stores_vi <0x19, "S_BUFFER_STORE_DWORDX2">;
 427 defm S_BUFFER_STORE_DWORDX4  : SM_Real_Stores_vi <0x1a, "S_BUFFER_STORE_DWORDX4">;
 428
 429 // These instructions use same encoding
 430 def S_DCACHE_INV_vi         : SMEM_Real_vi <0x20, S_DCACHE_INV>;
 431 def S_DCACHE_WB_vi          : SMEM_Real_vi <0x21, S_DCACHE_WB>;
 432 def S_DCACHE_INV_VOL_vi     : SMEM_Real_vi <0x22, S_DCACHE_INV_VOL>;
 433 def S_DCACHE_WB_VOL_vi      : SMEM_Real_vi <0x23, S_DCACHE_WB_VOL>;
 434 def S_MEMTIME_vi            : SMEM_Real_vi <0x24, S_MEMTIME>;
 435 def S_MEMREALTIME_vi        : SMEM_Real_vi <0x25, S_MEMREALTIME>;
 436
 437
 438 //===----------------------------------------------------------------------===//
 439 // CI
 440 //===----------------------------------------------------------------------===//
 441
 442 def smrd_literal_offset : NamedOperandU32<"SMRDLiteralOffset",
 443                                           NamedMatchClass<"SMRDLiteralOffset">> {
 444   let OperandType = "OPERAND_IMMEDIATE";
 445 }
 446
 447 class SMRD_Real_Load_IMM_ci <bits<5> op, SM_Load_Pseudo ps> :
 448   SM_Real<ps>,
 449   Enc64 {
 450
 451   let AssemblerPredicates = [isCIOnly];
 452   let DecoderNamespace = "CI";
 453   let InOperandList = (ins ps.BaseClass:$sbase, smrd_literal_offset:$offset, GLC:$glc);
 454
 455   let LGKM_CNT = ps.LGKM_CNT;
 456   let SMRD = ps.SMRD;
 457   let mayLoad = ps.mayLoad;
 458   let mayStore = ps.mayStore;
 459   let hasSideEffects = ps.hasSideEffects;
 460   let SchedRW = ps.SchedRW;
 461   let UseNamedOperandTable = ps.UseNamedOperandTable;
 462
 463   let Inst{7-0}   = 0xff;
 464   let Inst{8}     = 0;
 465   let Inst{14-9}  = sbase{6-1};
 466   let Inst{21-15} = sdst{6-0};
 467   let Inst{26-22} = op;
 468   let Inst{31-27} = 0x18; //encoding
 469   let Inst{63-32} = offset{31-0};
 470 }
 471
 472 def S_LOAD_DWORD_IMM_ci           : SMRD_Real_Load_IMM_ci <0x00, S_LOAD_DWORD_IMM>;
 473 def S_LOAD_DWORDX2_IMM_ci         : SMRD_Real_Load_IMM_ci <0x01, S_LOAD_DWORDX2_IMM>;
 474 def S_LOAD_DWORDX4_IMM_ci         : SMRD_Real_Load_IMM_ci <0x02, S_LOAD_DWORDX4_IMM>;
 475 def S_LOAD_DWORDX8_IMM_ci         : SMRD_Real_Load_IMM_ci <0x03, S_LOAD_DWORDX8_IMM>;
 476 def S_LOAD_DWORDX16_IMM_ci        : SMRD_Real_Load_IMM_ci <0x04, S_LOAD_DWORDX16_IMM>;
 477 def S_BUFFER_LOAD_DWORD_IMM_ci    : SMRD_Real_Load_IMM_ci <0x08, S_BUFFER_LOAD_DWORD_IMM>;
 478 def S_BUFFER_LOAD_DWORDX2_IMM_ci  : SMRD_Real_Load_IMM_ci <0x09, S_BUFFER_LOAD_DWORDX2_IMM>;
 479 def S_BUFFER_LOAD_DWORDX4_IMM_ci  : SMRD_Real_Load_IMM_ci <0x0a, S_BUFFER_LOAD_DWORDX4_IMM>;
 480 def S_BUFFER_LOAD_DWORDX8_IMM_ci  : SMRD_Real_Load_IMM_ci <0x0b, S_BUFFER_LOAD_DWORDX8_IMM>;
 481 def S_BUFFER_LOAD_DWORDX16_IMM_ci : SMRD_Real_Load_IMM_ci <0x0c, S_BUFFER_LOAD_DWORDX16_IMM>;
 482
 483 class SMRD_Real_ci <bits<5> op, SM_Pseudo ps>
 484   : SM_Real<ps>
 485   , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
 486   , Enc32 {
 487
 488   let AssemblerPredicates = [isCIOnly];
 489   let DecoderNamespace = "CI";
 490
 491   let Inst{7-0}   = !if(ps.has_offset, offset{7-0}, ?);
 492   let Inst{8}     = imm;
 493   let Inst{14-9}  = !if(ps.has_sbase, sbase{6-1}, ?);
 494   let Inst{21-15} = !if(ps.has_sdst, sdst{6-0}, ?);
 495   let Inst{26-22} = op;
 496   let Inst{31-27} = 0x18; //encoding
 497 }
 498
 499 def S_DCACHE_INV_VOL_ci : SMRD_Real_ci <0x1d, S_DCACHE_INV_VOL>;
 500
 501 let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity in {
 502
 503 class SMRD_Pattern_ci <string Instr, ValueType vt> : GCNPat <
 504   (smrd_load (SMRDImm32 i64:$sbase, i32:$offset)),
 505   (vt (!cast<SM_Pseudo>(Instr#"_IMM_ci") $sbase, $offset, 0))> {
 506   let OtherPredicates = [isCIOnly];
 507 }
 508
 509 def : SMRD_Pattern_ci <"S_LOAD_DWORD",    i32>;
 510 def : SMRD_Pattern_ci <"S_LOAD_DWORDX2",  v2i32>;
 511 def : SMRD_Pattern_ci <"S_LOAD_DWORDX4",  v4i32>;
 512 def : SMRD_Pattern_ci <"S_LOAD_DWORDX8",  v8i32>;
 513 def : SMRD_Pattern_ci <"S_LOAD_DWORDX16", v16i32>;
 514
 515 def : GCNPat <
 516   (SIload_constant v4i32:$sbase, (SMRDBufferImm32 i32:$offset)),
 517   (S_BUFFER_LOAD_DWORD_IMM_ci $sbase, $offset, 0)> {
 518   let OtherPredicates = [isCI]; // should this be isCIOnly?
 519 }
 520
 521 } // End let AddedComplexity = SM_LOAD_PATTERN.AddedComplexity
 522