1 //===-- SOPInstructions.td - SOP Instruction Defintions -------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 def GPRIdxModeMatchClass : AsmOperandClass {
11 let Name = "GPRIdxMode";
12 let PredicateMethod = "isGPRIdxMode";
13 let RenderMethod = "addImmOperands";
16 def GPRIdxMode : Operand<i32> {
17 let PrintMethod = "printVGPRIndexMode";
18 let ParserMatchClass = GPRIdxModeMatchClass;
19 let OperandType = "OPERAND_IMMEDIATE";
22 //===----------------------------------------------------------------------===//
24 //===----------------------------------------------------------------------===//
26 class SOP1_Pseudo <string opName, dag outs, dag ins,
27 string asmOps, list<dag> pattern=[]> :
28 InstSI <outs, ins, "", pattern>,
29 SIMCInstr<opName, SIEncodingFamily.NONE> {
31 let isCodeGenOnly = 1;
32 let SubtargetPredicate = isGCN;
36 let hasSideEffects = 0;
39 let SchedRW = [WriteSALU];
41 let UseNamedOperandTable = 1;
43 string Mnemonic = opName;
44 string AsmOperands = asmOps;
50 class SOP1_Real<bits<8> op, SOP1_Pseudo ps> :
51 InstSI <ps.OutOperandList, ps.InOperandList,
52 ps.Mnemonic # " " # ps.AsmOperands, []>,
56 let isCodeGenOnly = 0;
59 // copy relevant pseudo op flags
60 let SubtargetPredicate = ps.SubtargetPredicate;
61 let AsmMatchConverter = ps.AsmMatchConverter;
67 let Inst{7-0} = !if(ps.has_src0, src0, ?);
69 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
70 let Inst{31-23} = 0x17d; //encoding;
73 class SOP1_32 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
74 opName, (outs SReg_32:$sdst), (ins SSrc_b32:$src0),
75 "$sdst, $src0", pattern
78 // 32-bit input, no output.
79 class SOP1_0_32 <string opName, list<dag> pattern = []> : SOP1_Pseudo <
80 opName, (outs), (ins SSrc_b32:$src0),
85 class SOP1_0_32R <string opName, list<dag> pattern = []> : SOP1_Pseudo <
86 opName, (outs), (ins SReg_32:$src0),
91 class SOP1_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
92 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0),
93 "$sdst, $src0", pattern
96 // 64-bit input, 32-bit output.
97 class SOP1_32_64 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
98 opName, (outs SReg_32:$sdst), (ins SSrc_b64:$src0),
99 "$sdst, $src0", pattern
102 // 32-bit input, 64-bit output.
103 class SOP1_64_32 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
104 opName, (outs SReg_64:$sdst), (ins SSrc_b32:$src0),
105 "$sdst, $src0", pattern
108 // no input, 64-bit output.
109 class SOP1_64_0 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
110 opName, (outs SReg_64:$sdst), (ins), "$sdst", pattern> {
114 // 64-bit input, no output
115 class SOP1_1 <string opName, list<dag> pattern=[]> : SOP1_Pseudo <
116 opName, (outs), (ins SReg_64:$src0), "$src0", pattern> {
121 let isMoveImm = 1 in {
122 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
123 def S_MOV_B32 : SOP1_32 <"s_mov_b32">;
124 def S_MOV_B64 : SOP1_64 <"s_mov_b64">;
125 } // End isRematerializeable = 1
127 let Uses = [SCC] in {
128 def S_CMOV_B32 : SOP1_32 <"s_cmov_b32">;
129 def S_CMOV_B64 : SOP1_64 <"s_cmov_b64">;
130 } // End Uses = [SCC]
131 } // End isMoveImm = 1
133 let Defs = [SCC] in {
134 def S_NOT_B32 : SOP1_32 <"s_not_b32",
135 [(set i32:$sdst, (not i32:$src0))]
138 def S_NOT_B64 : SOP1_64 <"s_not_b64",
139 [(set i64:$sdst, (not i64:$src0))]
141 def S_WQM_B32 : SOP1_32 <"s_wqm_b32">;
142 def S_WQM_B64 : SOP1_64 <"s_wqm_b64",
143 [(set i1:$sdst, (int_amdgcn_wqm_vote i1:$src0))]
145 } // End Defs = [SCC]
148 def S_BREV_B32 : SOP1_32 <"s_brev_b32",
149 [(set i32:$sdst, (bitreverse i32:$src0))]
151 def S_BREV_B64 : SOP1_64 <"s_brev_b64">;
153 let Defs = [SCC] in {
154 def S_BCNT0_I32_B32 : SOP1_32 <"s_bcnt0_i32_b32">;
155 def S_BCNT0_I32_B64 : SOP1_32_64 <"s_bcnt0_i32_b64">;
156 def S_BCNT1_I32_B32 : SOP1_32 <"s_bcnt1_i32_b32",
157 [(set i32:$sdst, (ctpop i32:$src0))]
159 def S_BCNT1_I32_B64 : SOP1_32_64 <"s_bcnt1_i32_b64">;
160 } // End Defs = [SCC]
162 def S_FF0_I32_B32 : SOP1_32 <"s_ff0_i32_b32">;
163 def S_FF0_I32_B64 : SOP1_32_64 <"s_ff0_i32_b64">;
164 def S_FF1_I32_B64 : SOP1_32_64 <"s_ff1_i32_b64">;
166 def S_FF1_I32_B32 : SOP1_32 <"s_ff1_i32_b32",
167 [(set i32:$sdst, (AMDGPUffbl_b32 i32:$src0))]
170 def S_FLBIT_I32_B32 : SOP1_32 <"s_flbit_i32_b32",
171 [(set i32:$sdst, (AMDGPUffbh_u32 i32:$src0))]
174 def S_FLBIT_I32_B64 : SOP1_32_64 <"s_flbit_i32_b64">;
175 def S_FLBIT_I32 : SOP1_32 <"s_flbit_i32",
176 [(set i32:$sdst, (AMDGPUffbh_i32 i32:$src0))]
178 def S_FLBIT_I32_I64 : SOP1_32_64 <"s_flbit_i32_i64">;
179 def S_SEXT_I32_I8 : SOP1_32 <"s_sext_i32_i8",
180 [(set i32:$sdst, (sext_inreg i32:$src0, i8))]
182 def S_SEXT_I32_I16 : SOP1_32 <"s_sext_i32_i16",
183 [(set i32:$sdst, (sext_inreg i32:$src0, i16))]
186 def S_BITSET0_B32 : SOP1_32 <"s_bitset0_b32">;
187 def S_BITSET0_B64 : SOP1_64_32 <"s_bitset0_b64">;
188 def S_BITSET1_B32 : SOP1_32 <"s_bitset1_b32">;
189 def S_BITSET1_B64 : SOP1_64_32 <"s_bitset1_b64">;
190 def S_GETPC_B64 : SOP1_64_0 <"s_getpc_b64",
191 [(set i64:$sdst, (int_amdgcn_s_getpc))]
194 let isTerminator = 1, isBarrier = 1, SchedRW = [WriteBranch] in {
196 let isBranch = 1, isIndirectBranch = 1 in {
197 def S_SETPC_B64 : SOP1_1 <"s_setpc_b64">;
198 } // End isBranch = 1, isIndirectBranch = 1
200 let isReturn = 1 in {
201 // Define variant marked as return rather than branch.
202 def S_SETPC_B64_return : SOP1_1<"", [(AMDGPUret_flag i64:$src0)]>;
204 } // End isTerminator = 1, isBarrier = 1
207 def S_SWAPPC_B64 : SOP1_64 <"s_swappc_b64"
211 def S_RFE_B64 : SOP1_1 <"s_rfe_b64">;
213 let hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC] in {
215 def S_AND_SAVEEXEC_B64 : SOP1_64 <"s_and_saveexec_b64">;
216 def S_OR_SAVEEXEC_B64 : SOP1_64 <"s_or_saveexec_b64">;
217 def S_XOR_SAVEEXEC_B64 : SOP1_64 <"s_xor_saveexec_b64">;
218 def S_ANDN2_SAVEEXEC_B64 : SOP1_64 <"s_andn2_saveexec_b64">;
219 def S_ORN2_SAVEEXEC_B64 : SOP1_64 <"s_orn2_saveexec_b64">;
220 def S_NAND_SAVEEXEC_B64 : SOP1_64 <"s_nand_saveexec_b64">;
221 def S_NOR_SAVEEXEC_B64 : SOP1_64 <"s_nor_saveexec_b64">;
222 def S_XNOR_SAVEEXEC_B64 : SOP1_64 <"s_xnor_saveexec_b64">;
224 } // End hasSideEffects = 1, Uses = [EXEC], Defs = [EXEC, SCC]
226 def S_QUADMASK_B32 : SOP1_32 <"s_quadmask_b32">;
227 def S_QUADMASK_B64 : SOP1_64 <"s_quadmask_b64">;
230 def S_MOVRELS_B32 : SOP1_32 <"s_movrels_b32">;
231 def S_MOVRELS_B64 : SOP1_64 <"s_movrels_b64">;
232 def S_MOVRELD_B32 : SOP1_32 <"s_movreld_b32">;
233 def S_MOVRELD_B64 : SOP1_64 <"s_movreld_b64">;
236 def S_CBRANCH_JOIN : SOP1_0_32R <"s_cbranch_join">;
237 def S_MOV_REGRD_B32 : SOP1_32 <"s_mov_regrd_b32">;
238 let Defs = [SCC] in {
239 def S_ABS_I32 : SOP1_32 <"s_abs_i32">;
240 } // End Defs = [SCC]
241 def S_MOV_FED_B32 : SOP1_32 <"s_mov_fed_b32">;
243 let SubtargetPredicate = HasVGPRIndexMode in {
244 def S_SET_GPR_IDX_IDX : SOP1_0_32<"s_set_gpr_idx_idx"> {
250 //===----------------------------------------------------------------------===//
252 //===----------------------------------------------------------------------===//
254 class SOP2_Pseudo<string opName, dag outs, dag ins,
255 string asmOps, list<dag> pattern=[]> :
256 InstSI<outs, ins, "", pattern>,
257 SIMCInstr<opName, SIEncodingFamily.NONE> {
259 let isCodeGenOnly = 1;
260 let SubtargetPredicate = isGCN;
263 let hasSideEffects = 0;
266 let SchedRW = [WriteSALU];
267 let UseNamedOperandTable = 1;
269 string Mnemonic = opName;
270 string AsmOperands = asmOps;
272 bits<1> has_sdst = 1;
274 // Pseudo instructions have no encodings, but adding this field here allows
276 // let sdst = xxx in {
277 // for multiclasses that include both real and pseudo instructions.
278 // field bits<7> sdst = 0;
279 // let Size = 4; // Do we need size here?
282 class SOP2_Real<bits<7> op, SOP2_Pseudo ps> :
283 InstSI <ps.OutOperandList, ps.InOperandList,
284 ps.Mnemonic # " " # ps.AsmOperands, []>,
287 let isCodeGenOnly = 0;
289 // copy relevant pseudo op flags
290 let SubtargetPredicate = ps.SubtargetPredicate;
291 let AsmMatchConverter = ps.AsmMatchConverter;
298 let Inst{7-0} = src0;
299 let Inst{15-8} = src1;
300 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
301 let Inst{29-23} = op;
302 let Inst{31-30} = 0x2; // encoding
306 class SOP2_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
307 opName, (outs SReg_32:$sdst), (ins SSrc_b32:$src0, SSrc_b32:$src1),
308 "$sdst, $src0, $src1", pattern
311 class SOP2_64 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
312 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b64:$src1),
313 "$sdst, $src0, $src1", pattern
316 class SOP2_64_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
317 opName, (outs SReg_64:$sdst), (ins SSrc_b64:$src0, SSrc_b32:$src1),
318 "$sdst, $src0, $src1", pattern
321 class SOP2_64_32_32 <string opName, list<dag> pattern=[]> : SOP2_Pseudo <
322 opName, (outs SReg_64:$sdst), (ins SSrc_b32:$src0, SSrc_b32:$src1),
323 "$sdst, $src0, $src1", pattern
326 let Defs = [SCC] in { // Carry out goes to SCC
327 let isCommutable = 1 in {
328 def S_ADD_U32 : SOP2_32 <"s_add_u32">;
329 def S_ADD_I32 : SOP2_32 <"s_add_i32",
330 [(set i32:$sdst, (add SSrc_b32:$src0, SSrc_b32:$src1))]
332 } // End isCommutable = 1
334 def S_SUB_U32 : SOP2_32 <"s_sub_u32">;
335 def S_SUB_I32 : SOP2_32 <"s_sub_i32",
336 [(set i32:$sdst, (sub SSrc_b32:$src0, SSrc_b32:$src1))]
339 let Uses = [SCC] in { // Carry in comes from SCC
340 let isCommutable = 1 in {
341 def S_ADDC_U32 : SOP2_32 <"s_addc_u32",
342 [(set i32:$sdst, (adde (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;
343 } // End isCommutable = 1
345 def S_SUBB_U32 : SOP2_32 <"s_subb_u32",
346 [(set i32:$sdst, (sube (i32 SSrc_b32:$src0), (i32 SSrc_b32:$src1)))]>;
347 } // End Uses = [SCC]
350 let isCommutable = 1 in {
351 def S_MIN_I32 : SOP2_32 <"s_min_i32",
352 [(set i32:$sdst, (smin i32:$src0, i32:$src1))]
354 def S_MIN_U32 : SOP2_32 <"s_min_u32",
355 [(set i32:$sdst, (umin i32:$src0, i32:$src1))]
357 def S_MAX_I32 : SOP2_32 <"s_max_i32",
358 [(set i32:$sdst, (smax i32:$src0, i32:$src1))]
360 def S_MAX_U32 : SOP2_32 <"s_max_u32",
361 [(set i32:$sdst, (umax i32:$src0, i32:$src1))]
363 } // End isCommutable = 1
364 } // End Defs = [SCC]
367 let Uses = [SCC] in {
368 def S_CSELECT_B32 : SOP2_32 <"s_cselect_b32">;
369 def S_CSELECT_B64 : SOP2_64 <"s_cselect_b64">;
370 } // End Uses = [SCC]
372 let Defs = [SCC] in {
373 let isCommutable = 1 in {
374 def S_AND_B32 : SOP2_32 <"s_and_b32",
375 [(set i32:$sdst, (and i32:$src0, i32:$src1))]
378 def S_AND_B64 : SOP2_64 <"s_and_b64",
379 [(set i64:$sdst, (and i64:$src0, i64:$src1))]
382 def S_OR_B32 : SOP2_32 <"s_or_b32",
383 [(set i32:$sdst, (or i32:$src0, i32:$src1))]
386 def S_OR_B64 : SOP2_64 <"s_or_b64",
387 [(set i64:$sdst, (or i64:$src0, i64:$src1))]
390 def S_XOR_B32 : SOP2_32 <"s_xor_b32",
391 [(set i32:$sdst, (xor i32:$src0, i32:$src1))]
394 def S_XOR_B64 : SOP2_64 <"s_xor_b64",
395 [(set i64:$sdst, (xor i64:$src0, i64:$src1))]
398 def S_XNOR_B32 : SOP2_32 <"s_xnor_b32",
399 [(set i32:$sdst, (not (xor_oneuse i32:$src0, i32:$src1)))]
402 def S_XNOR_B64 : SOP2_64 <"s_xnor_b64",
403 [(set i64:$sdst, (not (xor_oneuse i64:$src0, i64:$src1)))]
405 } // End isCommutable = 1
407 def S_ANDN2_B32 : SOP2_32 <"s_andn2_b32">;
408 def S_ANDN2_B64 : SOP2_64 <"s_andn2_b64">;
409 def S_ORN2_B32 : SOP2_32 <"s_orn2_b32">;
410 def S_ORN2_B64 : SOP2_64 <"s_orn2_b64">;
411 def S_NAND_B32 : SOP2_32 <"s_nand_b32">;
412 def S_NAND_B64 : SOP2_64 <"s_nand_b64">;
413 def S_NOR_B32 : SOP2_32 <"s_nor_b32">;
414 def S_NOR_B64 : SOP2_64 <"s_nor_b64">;
415 } // End Defs = [SCC]
417 // Use added complexity so these patterns are preferred to the VALU patterns.
418 let AddedComplexity = 1 in {
420 let Defs = [SCC] in {
421 def S_LSHL_B32 : SOP2_32 <"s_lshl_b32",
422 [(set i32:$sdst, (shl i32:$src0, i32:$src1))]
424 def S_LSHL_B64 : SOP2_64_32 <"s_lshl_b64",
425 [(set i64:$sdst, (shl i64:$src0, i32:$src1))]
427 def S_LSHR_B32 : SOP2_32 <"s_lshr_b32",
428 [(set i32:$sdst, (srl i32:$src0, i32:$src1))]
430 def S_LSHR_B64 : SOP2_64_32 <"s_lshr_b64",
431 [(set i64:$sdst, (srl i64:$src0, i32:$src1))]
433 def S_ASHR_I32 : SOP2_32 <"s_ashr_i32",
434 [(set i32:$sdst, (sra i32:$src0, i32:$src1))]
436 def S_ASHR_I64 : SOP2_64_32 <"s_ashr_i64",
437 [(set i64:$sdst, (sra i64:$src0, i32:$src1))]
439 } // End Defs = [SCC]
441 def S_BFM_B32 : SOP2_32 <"s_bfm_b32",
442 [(set i32:$sdst, (AMDGPUbfm i32:$src0, i32:$src1))]>;
443 def S_BFM_B64 : SOP2_64_32_32 <"s_bfm_b64">;
444 def S_MUL_I32 : SOP2_32 <"s_mul_i32",
445 [(set i32:$sdst, (mul i32:$src0, i32:$src1))]> {
446 let isCommutable = 1;
449 } // End AddedComplexity = 1
451 let Defs = [SCC] in {
452 def S_BFE_U32 : SOP2_32 <"s_bfe_u32">;
453 def S_BFE_I32 : SOP2_32 <"s_bfe_i32">;
454 def S_BFE_U64 : SOP2_64_32 <"s_bfe_u64">;
455 def S_BFE_I64 : SOP2_64_32 <"s_bfe_i64">;
456 } // End Defs = [SCC]
458 def S_CBRANCH_G_FORK : SOP2_Pseudo <
459 "s_cbranch_g_fork", (outs),
460 (ins SCSrc_b64:$src0, SCSrc_b64:$src1),
466 let Defs = [SCC] in {
467 def S_ABSDIFF_I32 : SOP2_32 <"s_absdiff_i32">;
468 } // End Defs = [SCC]
470 let SubtargetPredicate = isVI in {
471 def S_RFE_RESTORE_B64 : SOP2_Pseudo <
472 "s_rfe_restore_b64", (outs),
473 (ins SSrc_b64:$src0, SSrc_b32:$src1),
476 let hasSideEffects = 1;
481 let SubtargetPredicate = isGFX9 in {
482 def S_PACK_LL_B32_B16 : SOP2_32<"s_pack_ll_b32_b16">;
483 def S_PACK_LH_B32_B16 : SOP2_32<"s_pack_lh_b32_b16">;
484 def S_PACK_HH_B32_B16 : SOP2_32<"s_pack_hh_b32_b16">;
487 //===----------------------------------------------------------------------===//
489 //===----------------------------------------------------------------------===//
491 class SOPK_Pseudo <string opName, dag outs, dag ins,
492 string asmOps, list<dag> pattern=[]> :
493 InstSI <outs, ins, "", pattern>,
494 SIMCInstr<opName, SIEncodingFamily.NONE> {
496 let isCodeGenOnly = 1;
497 let SubtargetPredicate = isGCN;
500 let hasSideEffects = 0;
503 let SchedRW = [WriteSALU];
504 let UseNamedOperandTable = 1;
505 string Mnemonic = opName;
506 string AsmOperands = asmOps;
508 bits<1> has_sdst = 1;
511 class SOPK_Real<bits<5> op, SOPK_Pseudo ps> :
512 InstSI <ps.OutOperandList, ps.InOperandList,
513 ps.Mnemonic # " " # ps.AsmOperands, []> {
515 let isCodeGenOnly = 0;
517 // copy relevant pseudo op flags
518 let SubtargetPredicate = ps.SubtargetPredicate;
519 let AsmMatchConverter = ps.AsmMatchConverter;
520 let DisableEncoding = ps.DisableEncoding;
521 let Constraints = ps.Constraints;
529 class SOPK_Real32<bits<5> op, SOPK_Pseudo ps> :
532 let Inst{15-0} = simm16;
533 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
534 let Inst{27-23} = op;
535 let Inst{31-28} = 0xb; //encoding
538 class SOPK_Real64<bits<5> op, SOPK_Pseudo ps> :
541 let Inst{15-0} = simm16;
542 let Inst{22-16} = !if(ps.has_sdst, sdst, ?);
543 let Inst{27-23} = op;
544 let Inst{31-28} = 0xb; //encoding
545 let Inst{63-32} = imm;
548 class SOPKInstTable <bit is_sopk, string cmpOp = ""> {
549 bit IsSOPK = is_sopk;
550 string BaseCmpOp = cmpOp;
553 class SOPK_32 <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
555 (outs SReg_32:$sdst),
556 (ins s16imm:$simm16),
560 class SOPK_SCC <string opName, string base_op, bit isSignExt> : SOPK_Pseudo <
564 (ins SReg_32:$sdst, s16imm:$simm16),
565 (ins SReg_32:$sdst, u16imm:$simm16)),
566 "$sdst, $simm16", []>,
567 SOPKInstTable<1, base_op>{
571 class SOPK_32TIE <string opName, list<dag> pattern=[]> : SOPK_Pseudo <
573 (outs SReg_32:$sdst),
574 (ins SReg_32:$src0, s16imm:$simm16),
579 let isReMaterializable = 1, isMoveImm = 1 in {
580 def S_MOVK_I32 : SOPK_32 <"s_movk_i32">;
581 } // End isReMaterializable = 1
582 let Uses = [SCC] in {
583 def S_CMOVK_I32 : SOPK_32 <"s_cmovk_i32">;
586 let isCompare = 1 in {
588 // This instruction is disabled for now until we can figure out how to teach
589 // the instruction selector to correctly use the S_CMP* vs V_CMP*
592 // When this instruction is enabled the code generator sometimes produces this
595 // SCC = S_CMPK_EQ_I32 SGPR0, imm
597 // VGPR0 = V_CNDMASK VCC, VGPR0, VGPR1
599 // def S_CMPK_EQ_I32 : SOPK_SCC <"s_cmpk_eq_i32",
600 // [(set i1:$dst, (setcc i32:$src0, imm:$src1, SETEQ))]
603 def S_CMPK_EQ_I32 : SOPK_SCC <"s_cmpk_eq_i32", "s_cmp_eq_i32", 1>;
604 def S_CMPK_LG_I32 : SOPK_SCC <"s_cmpk_lg_i32", "s_cmp_lg_i32", 1>;
605 def S_CMPK_GT_I32 : SOPK_SCC <"s_cmpk_gt_i32", "s_cmp_gt_i32", 1>;
606 def S_CMPK_GE_I32 : SOPK_SCC <"s_cmpk_ge_i32", "s_cmp_ge_i32", 1>;
607 def S_CMPK_LT_I32 : SOPK_SCC <"s_cmpk_lt_i32", "s_cmp_lt_i32", 1>;
608 def S_CMPK_LE_I32 : SOPK_SCC <"s_cmpk_le_i32", "s_cmp_le_i32", 1>;
610 let SOPKZext = 1 in {
611 def S_CMPK_EQ_U32 : SOPK_SCC <"s_cmpk_eq_u32", "s_cmp_eq_u32", 0>;
612 def S_CMPK_LG_U32 : SOPK_SCC <"s_cmpk_lg_u32", "s_cmp_lg_u32", 0>;
613 def S_CMPK_GT_U32 : SOPK_SCC <"s_cmpk_gt_u32", "s_cmp_gt_u32", 0>;
614 def S_CMPK_GE_U32 : SOPK_SCC <"s_cmpk_ge_u32", "s_cmp_ge_u32", 0>;
615 def S_CMPK_LT_U32 : SOPK_SCC <"s_cmpk_lt_u32", "s_cmp_lt_u32", 0>;
616 def S_CMPK_LE_U32 : SOPK_SCC <"s_cmpk_le_u32", "s_cmp_le_u32", 0>;
617 } // End SOPKZext = 1
618 } // End isCompare = 1
620 let Defs = [SCC], isCommutable = 1, DisableEncoding = "$src0",
621 Constraints = "$sdst = $src0" in {
622 def S_ADDK_I32 : SOPK_32TIE <"s_addk_i32">;
623 def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">;
626 def S_CBRANCH_I_FORK : SOPK_Pseudo <
628 (outs), (ins SReg_64:$sdst, s16imm:$simm16),
633 def S_GETREG_B32 : SOPK_Pseudo <
635 (outs SReg_32:$sdst), (ins hwreg:$simm16),
640 let hasSideEffects = 1 in {
642 def S_SETREG_B32 : SOPK_Pseudo <
644 (outs), (ins SReg_32:$sdst, hwreg:$simm16),
646 [(AMDGPUsetreg i32:$sdst, (i16 timm:$simm16))]
650 //def S_GETREG_REGRD_B32 : SOPK_32 <sopk<0x14, 0x13>, "s_getreg_regrd_b32">;
652 def S_SETREG_IMM32_B32 : SOPK_Pseudo <
653 "s_setreg_imm32_b32",
654 (outs), (ins i32imm:$imm, hwreg:$simm16),
656 let Size = 8; // Unlike every other SOPK instruction.
660 } // End hasSideEffects = 1
662 //===----------------------------------------------------------------------===//
664 //===----------------------------------------------------------------------===//
666 class SOPCe <bits<7> op> : Enc32 {
670 let Inst{7-0} = src0;
671 let Inst{15-8} = src1;
672 let Inst{22-16} = op;
673 let Inst{31-23} = 0x17e;
676 class SOPC <bits<7> op, dag outs, dag ins, string asm,
677 list<dag> pattern = []> :
678 InstSI<outs, ins, asm, pattern>, SOPCe <op> {
681 let hasSideEffects = 0;
684 let isCodeGenOnly = 0;
686 let SchedRW = [WriteSALU];
687 let UseNamedOperandTable = 1;
688 let SubtargetPredicate = isGCN;
691 class SOPC_Base <bits<7> op, RegisterOperand rc0, RegisterOperand rc1,
692 string opName, list<dag> pattern = []> : SOPC <
693 op, (outs), (ins rc0:$src0, rc1:$src1),
694 opName#" $src0, $src1", pattern > {
697 class SOPC_Helper <bits<7> op, RegisterOperand rc, ValueType vt,
698 string opName, PatLeaf cond> : SOPC_Base <
700 [(set SCC, (si_setcc_uniform vt:$src0, vt:$src1, cond))] > {
703 class SOPC_CMP_32<bits<7> op, string opName,
704 PatLeaf cond = COND_NULL, string revOp = opName>
705 : SOPC_Helper<op, SSrc_b32, i32, opName, cond>,
706 Commutable_REV<revOp, !eq(revOp, opName)>,
707 SOPKInstTable<0, opName> {
709 let isCommutable = 1;
712 class SOPC_CMP_64<bits<7> op, string opName,
713 PatLeaf cond = COND_NULL, string revOp = opName>
714 : SOPC_Helper<op, SSrc_b64, i64, opName, cond>,
715 Commutable_REV<revOp, !eq(revOp, opName)> {
717 let isCommutable = 1;
720 class SOPC_32<bits<7> op, string opName, list<dag> pattern = []>
721 : SOPC_Base<op, SSrc_b32, SSrc_b32, opName, pattern>;
723 class SOPC_64_32<bits<7> op, string opName, list<dag> pattern = []>
724 : SOPC_Base<op, SSrc_b64, SSrc_b32, opName, pattern>;
726 def S_CMP_EQ_I32 : SOPC_CMP_32 <0x00, "s_cmp_eq_i32">;
727 def S_CMP_LG_I32 : SOPC_CMP_32 <0x01, "s_cmp_lg_i32">;
728 def S_CMP_GT_I32 : SOPC_CMP_32 <0x02, "s_cmp_gt_i32", COND_SGT>;
729 def S_CMP_GE_I32 : SOPC_CMP_32 <0x03, "s_cmp_ge_i32", COND_SGE>;
730 def S_CMP_LT_I32 : SOPC_CMP_32 <0x04, "s_cmp_lt_i32", COND_SLT, "s_cmp_gt_i32">;
731 def S_CMP_LE_I32 : SOPC_CMP_32 <0x05, "s_cmp_le_i32", COND_SLE, "s_cmp_ge_i32">;
732 def S_CMP_EQ_U32 : SOPC_CMP_32 <0x06, "s_cmp_eq_u32", COND_EQ>;
733 def S_CMP_LG_U32 : SOPC_CMP_32 <0x07, "s_cmp_lg_u32", COND_NE>;
734 def S_CMP_GT_U32 : SOPC_CMP_32 <0x08, "s_cmp_gt_u32", COND_UGT>;
735 def S_CMP_GE_U32 : SOPC_CMP_32 <0x09, "s_cmp_ge_u32", COND_UGE>;
736 def S_CMP_LT_U32 : SOPC_CMP_32 <0x0a, "s_cmp_lt_u32", COND_ULT, "s_cmp_gt_u32">;
737 def S_CMP_LE_U32 : SOPC_CMP_32 <0x0b, "s_cmp_le_u32", COND_ULE, "s_cmp_ge_u32">;
739 def S_BITCMP0_B32 : SOPC_32 <0x0c, "s_bitcmp0_b32">;
740 def S_BITCMP1_B32 : SOPC_32 <0x0d, "s_bitcmp1_b32">;
741 def S_BITCMP0_B64 : SOPC_64_32 <0x0e, "s_bitcmp0_b64">;
742 def S_BITCMP1_B64 : SOPC_64_32 <0x0f, "s_bitcmp1_b64">;
743 def S_SETVSKIP : SOPC_32 <0x10, "s_setvskip">;
745 let SubtargetPredicate = isVI in {
746 def S_CMP_EQ_U64 : SOPC_CMP_64 <0x12, "s_cmp_eq_u64", COND_EQ>;
747 def S_CMP_LG_U64 : SOPC_CMP_64 <0x13, "s_cmp_lg_u64", COND_NE>;
750 let SubtargetPredicate = HasVGPRIndexMode in {
751 def S_SET_GPR_IDX_ON : SOPC <0x11,
753 (ins SSrc_b32:$src0, GPRIdxMode:$src1),
754 "s_set_gpr_idx_on $src0,$src1"> {
755 let Defs = [M0]; // No scc def
756 let Uses = [M0]; // Other bits of m0 unmodified.
757 let hasSideEffects = 1; // Sets mode.gpr_idx_en
762 //===----------------------------------------------------------------------===//
764 //===----------------------------------------------------------------------===//
766 class SOPPe <bits<7> op> : Enc32 {
769 let Inst{15-0} = simm16;
770 let Inst{22-16} = op;
771 let Inst{31-23} = 0x17f; // encoding
774 class SOPP <bits<7> op, dag ins, string asm, list<dag> pattern = []> :
775 InstSI <(outs), ins, asm, pattern >, SOPPe <op> {
779 let hasSideEffects = 0;
783 let SchedRW = [WriteSALU];
785 let UseNamedOperandTable = 1;
786 let SubtargetPredicate = isGCN;
790 def S_NOP : SOPP <0x00000000, (ins i16imm:$simm16), "s_nop $simm16">;
792 let isTerminator = 1 in {
794 def S_ENDPGM : SOPP <0x00000001, (ins), "s_endpgm",
801 let SubtargetPredicate = isVI in {
802 def S_ENDPGM_SAVED : SOPP <0x0000001B, (ins), "s_endpgm_saved"> {
809 let isBranch = 1, SchedRW = [WriteBranch] in {
810 def S_BRANCH : SOPP <
811 0x00000002, (ins sopp_brtarget:$simm16), "s_branch $simm16",
816 let Uses = [SCC] in {
817 def S_CBRANCH_SCC0 : SOPP <
818 0x00000004, (ins sopp_brtarget:$simm16),
819 "s_cbranch_scc0 $simm16"
821 def S_CBRANCH_SCC1 : SOPP <
822 0x00000005, (ins sopp_brtarget:$simm16),
823 "s_cbranch_scc1 $simm16"
825 } // End Uses = [SCC]
827 let Uses = [VCC] in {
828 def S_CBRANCH_VCCZ : SOPP <
829 0x00000006, (ins sopp_brtarget:$simm16),
830 "s_cbranch_vccz $simm16"
832 def S_CBRANCH_VCCNZ : SOPP <
833 0x00000007, (ins sopp_brtarget:$simm16),
834 "s_cbranch_vccnz $simm16"
836 } // End Uses = [VCC]
838 let Uses = [EXEC] in {
839 def S_CBRANCH_EXECZ : SOPP <
840 0x00000008, (ins sopp_brtarget:$simm16),
841 "s_cbranch_execz $simm16"
843 def S_CBRANCH_EXECNZ : SOPP <
844 0x00000009, (ins sopp_brtarget:$simm16),
845 "s_cbranch_execnz $simm16"
847 } // End Uses = [EXEC]
849 def S_CBRANCH_CDBGSYS : SOPP <
850 0x00000017, (ins sopp_brtarget:$simm16),
851 "s_cbranch_cdbgsys $simm16"
854 def S_CBRANCH_CDBGSYS_AND_USER : SOPP <
855 0x0000001A, (ins sopp_brtarget:$simm16),
856 "s_cbranch_cdbgsys_and_user $simm16"
859 def S_CBRANCH_CDBGSYS_OR_USER : SOPP <
860 0x00000019, (ins sopp_brtarget:$simm16),
861 "s_cbranch_cdbgsys_or_user $simm16"
864 def S_CBRANCH_CDBGUSER : SOPP <
865 0x00000018, (ins sopp_brtarget:$simm16),
866 "s_cbranch_cdbguser $simm16"
869 } // End isBranch = 1
870 } // End isTerminator = 1
872 let hasSideEffects = 1 in {
873 def S_BARRIER : SOPP <0x0000000a, (ins), "s_barrier",
874 [(int_amdgcn_s_barrier)]> {
875 let SchedRW = [WriteBarrier];
879 let isConvergent = 1;
882 let SubtargetPredicate = isVI in {
883 def S_WAKEUP : SOPP <0x00000003, (ins), "s_wakeup"> {
890 let mayLoad = 1, mayStore = 1, hasSideEffects = 1 in
891 def S_WAITCNT : SOPP <0x0000000c, (ins WAIT_FLAG:$simm16), "s_waitcnt $simm16">;
892 def S_SETHALT : SOPP <0x0000000d, (ins i16imm:$simm16), "s_sethalt $simm16">;
893 def S_SETKILL : SOPP <0x0000000b, (ins i16imm:$simm16), "s_setkill $simm16">;
895 // On SI the documentation says sleep for approximately 64 * low 2
896 // bits, consistent with the reported maximum of 448. On VI the
897 // maximum reported is 960 cycles, so 960 / 64 = 15 max, so is the
898 // maximum really 15 on VI?
899 def S_SLEEP : SOPP <0x0000000e, (ins i32imm:$simm16),
900 "s_sleep $simm16", [(int_amdgcn_s_sleep SIMM16bit:$simm16)]> {
901 let hasSideEffects = 1;
906 def S_SETPRIO : SOPP <0x0000000f, (ins i16imm:$simm16), "s_setprio $simm16">;
908 let Uses = [EXEC, M0] in {
909 // FIXME: Should this be mayLoad+mayStore?
910 def S_SENDMSG : SOPP <0x00000010, (ins SendMsgImm:$simm16), "s_sendmsg $simm16",
911 [(AMDGPUsendmsg (i32 imm:$simm16))]
914 def S_SENDMSGHALT : SOPP <0x00000011, (ins SendMsgImm:$simm16), "s_sendmsghalt $simm16",
915 [(AMDGPUsendmsghalt (i32 imm:$simm16))]
917 } // End Uses = [EXEC, M0]
919 def S_TRAP : SOPP <0x00000012, (ins i16imm:$simm16), "s_trap $simm16">;
920 def S_ICACHE_INV : SOPP <0x00000013, (ins), "s_icache_inv"> {
923 def S_INCPERFLEVEL : SOPP <0x00000014, (ins i32imm:$simm16), "s_incperflevel $simm16",
924 [(int_amdgcn_s_incperflevel SIMM16bit:$simm16)]> {
925 let hasSideEffects = 1;
929 def S_DECPERFLEVEL : SOPP <0x00000015, (ins i32imm:$simm16), "s_decperflevel $simm16",
930 [(int_amdgcn_s_decperflevel SIMM16bit:$simm16)]> {
931 let hasSideEffects = 1;
935 def S_TTRACEDATA : SOPP <0x00000016, (ins), "s_ttracedata"> {
939 let SubtargetPredicate = HasVGPRIndexMode in {
940 def S_SET_GPR_IDX_OFF : SOPP<0x1c, (ins), "s_set_gpr_idx_off"> {
944 } // End hasSideEffects
946 let SubtargetPredicate = HasVGPRIndexMode in {
947 def S_SET_GPR_IDX_MODE : SOPP<0x1d, (ins GPRIdxMode:$simm16),
948 "s_set_gpr_idx_mode$simm16"> {
953 //===----------------------------------------------------------------------===//
954 // S_GETREG_B32 Intrinsic Pattern.
955 //===----------------------------------------------------------------------===//
957 (int_amdgcn_s_getreg imm:$simm16),
958 (S_GETREG_B32 (as_i16imm $simm16))
961 //===----------------------------------------------------------------------===//
963 //===----------------------------------------------------------------------===//
966 (i64 (ctpop i64:$src)),
967 (i64 (REG_SEQUENCE SReg_64,
968 (i32 (COPY_TO_REGCLASS (S_BCNT1_I32_B64 $src), SReg_32)), sub0,
969 (S_MOV_B32 (i32 0)), sub1))
973 (i32 (smax i32:$x, (i32 (ineg i32:$x)))),
982 // Same as a 32-bit inreg
984 (i32 (sext i16:$src)),
985 (S_SEXT_I32_I16 $src)
989 //===----------------------------------------------------------------------===//
991 //===----------------------------------------------------------------------===//
993 // V_ADD_I32_e32/S_ADD_U32 produces carry in VCC/SCC. For the vector
994 // case, the sgpr-copies pass will fix this to use the vector version.
996 (i32 (addc i32:$src0, i32:$src1)),
997 (S_ADD_U32 $src0, $src1)
1000 // FIXME: We need to use COPY_TO_REGCLASS to work-around the fact that
1001 // REG_SEQUENCE patterns don't support instructions with multiple
1004 (i64 (zext i16:$src)),
1005 (REG_SEQUENCE SReg_64,
1006 (i32 (COPY_TO_REGCLASS (S_AND_B32 $src, (S_MOV_B32 (i32 0xffff))), SGPR_32)), sub0,
1007 (S_MOV_B32 (i32 0)), sub1)
1011 (i64 (sext i16:$src)),
1012 (REG_SEQUENCE SReg_64, (i32 (S_SEXT_I32_I16 $src)), sub0,
1013 (i32 (COPY_TO_REGCLASS (S_ASHR_I32 (i32 (S_SEXT_I32_I16 $src)), (S_MOV_B32 (i32 31))), SGPR_32)), sub1)
1017 (i32 (zext i16:$src)),
1018 (S_AND_B32 (S_MOV_B32 (i32 0xffff)), $src)
1023 //===----------------------------------------------------------------------===//
1025 //===----------------------------------------------------------------------===//
1028 (int_amdgcn_s_waitcnt i32:$simm16),
1029 (S_WAITCNT (as_i16imm $simm16))
1033 //===----------------------------------------------------------------------===//
1034 // Real target instructions, move this to the appropriate subtarget TD file
1035 //===----------------------------------------------------------------------===//
1037 class Select_si<string opName> :
1038 SIMCInstr<opName, SIEncodingFamily.SI> {
1039 list<Predicate> AssemblerPredicates = [isSICI];
1040 string DecoderNamespace = "SICI";
1043 class SOP1_Real_si<bits<8> op, SOP1_Pseudo ps> :
1045 Select_si<ps.Mnemonic>;
1047 class SOP2_Real_si<bits<7> op, SOP2_Pseudo ps> :
1049 Select_si<ps.Mnemonic>;
1051 class SOPK_Real_si<bits<5> op, SOPK_Pseudo ps> :
1052 SOPK_Real32<op, ps>,
1053 Select_si<ps.Mnemonic>;
1055 def S_MOV_B32_si : SOP1_Real_si <0x03, S_MOV_B32>;
1056 def S_MOV_B64_si : SOP1_Real_si <0x04, S_MOV_B64>;
1057 def S_CMOV_B32_si : SOP1_Real_si <0x05, S_CMOV_B32>;
1058 def S_CMOV_B64_si : SOP1_Real_si <0x06, S_CMOV_B64>;
1059 def S_NOT_B32_si : SOP1_Real_si <0x07, S_NOT_B32>;
1060 def S_NOT_B64_si : SOP1_Real_si <0x08, S_NOT_B64>;
1061 def S_WQM_B32_si : SOP1_Real_si <0x09, S_WQM_B32>;
1062 def S_WQM_B64_si : SOP1_Real_si <0x0a, S_WQM_B64>;
1063 def S_BREV_B32_si : SOP1_Real_si <0x0b, S_BREV_B32>;
1064 def S_BREV_B64_si : SOP1_Real_si <0x0c, S_BREV_B64>;
1065 def S_BCNT0_I32_B32_si : SOP1_Real_si <0x0d, S_BCNT0_I32_B32>;
1066 def S_BCNT0_I32_B64_si : SOP1_Real_si <0x0e, S_BCNT0_I32_B64>;
1067 def S_BCNT1_I32_B32_si : SOP1_Real_si <0x0f, S_BCNT1_I32_B32>;
1068 def S_BCNT1_I32_B64_si : SOP1_Real_si <0x10, S_BCNT1_I32_B64>;
1069 def S_FF0_I32_B32_si : SOP1_Real_si <0x11, S_FF0_I32_B32>;
1070 def S_FF0_I32_B64_si : SOP1_Real_si <0x12, S_FF0_I32_B64>;
1071 def S_FF1_I32_B32_si : SOP1_Real_si <0x13, S_FF1_I32_B32>;
1072 def S_FF1_I32_B64_si : SOP1_Real_si <0x14, S_FF1_I32_B64>;
1073 def S_FLBIT_I32_B32_si : SOP1_Real_si <0x15, S_FLBIT_I32_B32>;
1074 def S_FLBIT_I32_B64_si : SOP1_Real_si <0x16, S_FLBIT_I32_B64>;
1075 def S_FLBIT_I32_si : SOP1_Real_si <0x17, S_FLBIT_I32>;
1076 def S_FLBIT_I32_I64_si : SOP1_Real_si <0x18, S_FLBIT_I32_I64>;
1077 def S_SEXT_I32_I8_si : SOP1_Real_si <0x19, S_SEXT_I32_I8>;
1078 def S_SEXT_I32_I16_si : SOP1_Real_si <0x1a, S_SEXT_I32_I16>;
1079 def S_BITSET0_B32_si : SOP1_Real_si <0x1b, S_BITSET0_B32>;
1080 def S_BITSET0_B64_si : SOP1_Real_si <0x1c, S_BITSET0_B64>;
1081 def S_BITSET1_B32_si : SOP1_Real_si <0x1d, S_BITSET1_B32>;
1082 def S_BITSET1_B64_si : SOP1_Real_si <0x1e, S_BITSET1_B64>;
1083 def S_GETPC_B64_si : SOP1_Real_si <0x1f, S_GETPC_B64>;
1084 def S_SETPC_B64_si : SOP1_Real_si <0x20, S_SETPC_B64>;
1085 def S_SWAPPC_B64_si : SOP1_Real_si <0x21, S_SWAPPC_B64>;
1086 def S_RFE_B64_si : SOP1_Real_si <0x22, S_RFE_B64>;
1087 def S_AND_SAVEEXEC_B64_si : SOP1_Real_si <0x24, S_AND_SAVEEXEC_B64>;
1088 def S_OR_SAVEEXEC_B64_si : SOP1_Real_si <0x25, S_OR_SAVEEXEC_B64>;
1089 def S_XOR_SAVEEXEC_B64_si : SOP1_Real_si <0x26, S_XOR_SAVEEXEC_B64>;
1090 def S_ANDN2_SAVEEXEC_B64_si: SOP1_Real_si <0x27, S_ANDN2_SAVEEXEC_B64>;
1091 def S_ORN2_SAVEEXEC_B64_si : SOP1_Real_si <0x28, S_ORN2_SAVEEXEC_B64>;
1092 def S_NAND_SAVEEXEC_B64_si : SOP1_Real_si <0x29, S_NAND_SAVEEXEC_B64>;
1093 def S_NOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2a, S_NOR_SAVEEXEC_B64>;
1094 def S_XNOR_SAVEEXEC_B64_si : SOP1_Real_si <0x2b, S_XNOR_SAVEEXEC_B64>;
1095 def S_QUADMASK_B32_si : SOP1_Real_si <0x2c, S_QUADMASK_B32>;
1096 def S_QUADMASK_B64_si : SOP1_Real_si <0x2d, S_QUADMASK_B64>;
1097 def S_MOVRELS_B32_si : SOP1_Real_si <0x2e, S_MOVRELS_B32>;
1098 def S_MOVRELS_B64_si : SOP1_Real_si <0x2f, S_MOVRELS_B64>;
1099 def S_MOVRELD_B32_si : SOP1_Real_si <0x30, S_MOVRELD_B32>;
1100 def S_MOVRELD_B64_si : SOP1_Real_si <0x31, S_MOVRELD_B64>;
1101 def S_CBRANCH_JOIN_si : SOP1_Real_si <0x32, S_CBRANCH_JOIN>;
1102 def S_MOV_REGRD_B32_si : SOP1_Real_si <0x33, S_MOV_REGRD_B32>;
1103 def S_ABS_I32_si : SOP1_Real_si <0x34, S_ABS_I32>;
1104 def S_MOV_FED_B32_si : SOP1_Real_si <0x35, S_MOV_FED_B32>;
1106 def S_ADD_U32_si : SOP2_Real_si <0x00, S_ADD_U32>;
1107 def S_ADD_I32_si : SOP2_Real_si <0x02, S_ADD_I32>;
1108 def S_SUB_U32_si : SOP2_Real_si <0x01, S_SUB_U32>;
1109 def S_SUB_I32_si : SOP2_Real_si <0x03, S_SUB_I32>;
1110 def S_ADDC_U32_si : SOP2_Real_si <0x04, S_ADDC_U32>;
1111 def S_SUBB_U32_si : SOP2_Real_si <0x05, S_SUBB_U32>;
1112 def S_MIN_I32_si : SOP2_Real_si <0x06, S_MIN_I32>;
1113 def S_MIN_U32_si : SOP2_Real_si <0x07, S_MIN_U32>;
1114 def S_MAX_I32_si : SOP2_Real_si <0x08, S_MAX_I32>;
1115 def S_MAX_U32_si : SOP2_Real_si <0x09, S_MAX_U32>;
1116 def S_CSELECT_B32_si : SOP2_Real_si <0x0a, S_CSELECT_B32>;
1117 def S_CSELECT_B64_si : SOP2_Real_si <0x0b, S_CSELECT_B64>;
1118 def S_AND_B32_si : SOP2_Real_si <0x0e, S_AND_B32>;
1119 def S_AND_B64_si : SOP2_Real_si <0x0f, S_AND_B64>;
1120 def S_OR_B32_si : SOP2_Real_si <0x10, S_OR_B32>;
1121 def S_OR_B64_si : SOP2_Real_si <0x11, S_OR_B64>;
1122 def S_XOR_B32_si : SOP2_Real_si <0x12, S_XOR_B32>;
1123 def S_XOR_B64_si : SOP2_Real_si <0x13, S_XOR_B64>;
1124 def S_ANDN2_B32_si : SOP2_Real_si <0x14, S_ANDN2_B32>;
1125 def S_ANDN2_B64_si : SOP2_Real_si <0x15, S_ANDN2_B64>;
1126 def S_ORN2_B32_si : SOP2_Real_si <0x16, S_ORN2_B32>;
1127 def S_ORN2_B64_si : SOP2_Real_si <0x17, S_ORN2_B64>;
1128 def S_NAND_B32_si : SOP2_Real_si <0x18, S_NAND_B32>;
1129 def S_NAND_B64_si : SOP2_Real_si <0x19, S_NAND_B64>;
1130 def S_NOR_B32_si : SOP2_Real_si <0x1a, S_NOR_B32>;
1131 def S_NOR_B64_si : SOP2_Real_si <0x1b, S_NOR_B64>;
1132 def S_XNOR_B32_si : SOP2_Real_si <0x1c, S_XNOR_B32>;
1133 def S_XNOR_B64_si : SOP2_Real_si <0x1d, S_XNOR_B64>;
1134 def S_LSHL_B32_si : SOP2_Real_si <0x1e, S_LSHL_B32>;
1135 def S_LSHL_B64_si : SOP2_Real_si <0x1f, S_LSHL_B64>;
1136 def S_LSHR_B32_si : SOP2_Real_si <0x20, S_LSHR_B32>;
1137 def S_LSHR_B64_si : SOP2_Real_si <0x21, S_LSHR_B64>;
1138 def S_ASHR_I32_si : SOP2_Real_si <0x22, S_ASHR_I32>;
1139 def S_ASHR_I64_si : SOP2_Real_si <0x23, S_ASHR_I64>;
1140 def S_BFM_B32_si : SOP2_Real_si <0x24, S_BFM_B32>;
1141 def S_BFM_B64_si : SOP2_Real_si <0x25, S_BFM_B64>;
1142 def S_MUL_I32_si : SOP2_Real_si <0x26, S_MUL_I32>;
1143 def S_BFE_U32_si : SOP2_Real_si <0x27, S_BFE_U32>;
1144 def S_BFE_I32_si : SOP2_Real_si <0x28, S_BFE_I32>;
1145 def S_BFE_U64_si : SOP2_Real_si <0x29, S_BFE_U64>;
1146 def S_BFE_I64_si : SOP2_Real_si <0x2a, S_BFE_I64>;
1147 def S_CBRANCH_G_FORK_si : SOP2_Real_si <0x2b, S_CBRANCH_G_FORK>;
1148 def S_ABSDIFF_I32_si : SOP2_Real_si <0x2c, S_ABSDIFF_I32>;
1150 def S_MOVK_I32_si : SOPK_Real_si <0x00, S_MOVK_I32>;
1151 def S_CMOVK_I32_si : SOPK_Real_si <0x02, S_CMOVK_I32>;
1152 def S_CMPK_EQ_I32_si : SOPK_Real_si <0x03, S_CMPK_EQ_I32>;
1153 def S_CMPK_LG_I32_si : SOPK_Real_si <0x04, S_CMPK_LG_I32>;
1154 def S_CMPK_GT_I32_si : SOPK_Real_si <0x05, S_CMPK_GT_I32>;
1155 def S_CMPK_GE_I32_si : SOPK_Real_si <0x06, S_CMPK_GE_I32>;
1156 def S_CMPK_LT_I32_si : SOPK_Real_si <0x07, S_CMPK_LT_I32>;
1157 def S_CMPK_LE_I32_si : SOPK_Real_si <0x08, S_CMPK_LE_I32>;
1158 def S_CMPK_EQ_U32_si : SOPK_Real_si <0x09, S_CMPK_EQ_U32>;
1159 def S_CMPK_LG_U32_si : SOPK_Real_si <0x0a, S_CMPK_LG_U32>;
1160 def S_CMPK_GT_U32_si : SOPK_Real_si <0x0b, S_CMPK_GT_U32>;
1161 def S_CMPK_GE_U32_si : SOPK_Real_si <0x0c, S_CMPK_GE_U32>;
1162 def S_CMPK_LT_U32_si : SOPK_Real_si <0x0d, S_CMPK_LT_U32>;
1163 def S_CMPK_LE_U32_si : SOPK_Real_si <0x0e, S_CMPK_LE_U32>;
1164 def S_ADDK_I32_si : SOPK_Real_si <0x0f, S_ADDK_I32>;
1165 def S_MULK_I32_si : SOPK_Real_si <0x10, S_MULK_I32>;
1166 def S_CBRANCH_I_FORK_si : SOPK_Real_si <0x11, S_CBRANCH_I_FORK>;
1167 def S_GETREG_B32_si : SOPK_Real_si <0x12, S_GETREG_B32>;
1168 def S_SETREG_B32_si : SOPK_Real_si <0x13, S_SETREG_B32>;
1169 //def S_GETREG_REGRD_B32_si : SOPK_Real_si <0x14, S_GETREG_REGRD_B32>; // see pseudo for comments
1170 def S_SETREG_IMM32_B32_si : SOPK_Real64<0x15, S_SETREG_IMM32_B32>,
1171 Select_si<S_SETREG_IMM32_B32.Mnemonic>;
1174 class Select_vi<string opName> :
1175 SIMCInstr<opName, SIEncodingFamily.VI> {
1176 list<Predicate> AssemblerPredicates = [isVI];
1177 string DecoderNamespace = "VI";
1180 class SOP1_Real_vi<bits<8> op, SOP1_Pseudo ps> :
1182 Select_vi<ps.Mnemonic>;
1185 class SOP2_Real_vi<bits<7> op, SOP2_Pseudo ps> :
1187 Select_vi<ps.Mnemonic>;
1189 class SOPK_Real_vi<bits<5> op, SOPK_Pseudo ps> :
1190 SOPK_Real32<op, ps>,
1191 Select_vi<ps.Mnemonic>;
1193 def S_MOV_B32_vi : SOP1_Real_vi <0x00, S_MOV_B32>;
1194 def S_MOV_B64_vi : SOP1_Real_vi <0x01, S_MOV_B64>;
1195 def S_CMOV_B32_vi : SOP1_Real_vi <0x02, S_CMOV_B32>;
1196 def S_CMOV_B64_vi : SOP1_Real_vi <0x03, S_CMOV_B64>;
1197 def S_NOT_B32_vi : SOP1_Real_vi <0x04, S_NOT_B32>;
1198 def S_NOT_B64_vi : SOP1_Real_vi <0x05, S_NOT_B64>;
1199 def S_WQM_B32_vi : SOP1_Real_vi <0x06, S_WQM_B32>;
1200 def S_WQM_B64_vi : SOP1_Real_vi <0x07, S_WQM_B64>;
1201 def S_BREV_B32_vi : SOP1_Real_vi <0x08, S_BREV_B32>;
1202 def S_BREV_B64_vi : SOP1_Real_vi <0x09, S_BREV_B64>;
1203 def S_BCNT0_I32_B32_vi : SOP1_Real_vi <0x0a, S_BCNT0_I32_B32>;
1204 def S_BCNT0_I32_B64_vi : SOP1_Real_vi <0x0b, S_BCNT0_I32_B64>;
1205 def S_BCNT1_I32_B32_vi : SOP1_Real_vi <0x0c, S_BCNT1_I32_B32>;
1206 def S_BCNT1_I32_B64_vi : SOP1_Real_vi <0x0d, S_BCNT1_I32_B64>;
1207 def S_FF0_I32_B32_vi : SOP1_Real_vi <0x0e, S_FF0_I32_B32>;
1208 def S_FF0_I32_B64_vi : SOP1_Real_vi <0x0f, S_FF0_I32_B64>;
1209 def S_FF1_I32_B32_vi : SOP1_Real_vi <0x10, S_FF1_I32_B32>;
1210 def S_FF1_I32_B64_vi : SOP1_Real_vi <0x11, S_FF1_I32_B64>;
1211 def S_FLBIT_I32_B32_vi : SOP1_Real_vi <0x12, S_FLBIT_I32_B32>;
1212 def S_FLBIT_I32_B64_vi : SOP1_Real_vi <0x13, S_FLBIT_I32_B64>;
1213 def S_FLBIT_I32_vi : SOP1_Real_vi <0x14, S_FLBIT_I32>;
1214 def S_FLBIT_I32_I64_vi : SOP1_Real_vi <0x15, S_FLBIT_I32_I64>;
1215 def S_SEXT_I32_I8_vi : SOP1_Real_vi <0x16, S_SEXT_I32_I8>;
1216 def S_SEXT_I32_I16_vi : SOP1_Real_vi <0x17, S_SEXT_I32_I16>;
1217 def S_BITSET0_B32_vi : SOP1_Real_vi <0x18, S_BITSET0_B32>;
1218 def S_BITSET0_B64_vi : SOP1_Real_vi <0x19, S_BITSET0_B64>;
1219 def S_BITSET1_B32_vi : SOP1_Real_vi <0x1a, S_BITSET1_B32>;
1220 def S_BITSET1_B64_vi : SOP1_Real_vi <0x1b, S_BITSET1_B64>;
1221 def S_GETPC_B64_vi : SOP1_Real_vi <0x1c, S_GETPC_B64>;
1222 def S_SETPC_B64_vi : SOP1_Real_vi <0x1d, S_SETPC_B64>;
1223 def S_SWAPPC_B64_vi : SOP1_Real_vi <0x1e, S_SWAPPC_B64>;
1224 def S_RFE_B64_vi : SOP1_Real_vi <0x1f, S_RFE_B64>;
1225 def S_AND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x20, S_AND_SAVEEXEC_B64>;
1226 def S_OR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x21, S_OR_SAVEEXEC_B64>;
1227 def S_XOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x22, S_XOR_SAVEEXEC_B64>;
1228 def S_ANDN2_SAVEEXEC_B64_vi: SOP1_Real_vi <0x23, S_ANDN2_SAVEEXEC_B64>;
1229 def S_ORN2_SAVEEXEC_B64_vi : SOP1_Real_vi <0x24, S_ORN2_SAVEEXEC_B64>;
1230 def S_NAND_SAVEEXEC_B64_vi : SOP1_Real_vi <0x25, S_NAND_SAVEEXEC_B64>;
1231 def S_NOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x26, S_NOR_SAVEEXEC_B64>;
1232 def S_XNOR_SAVEEXEC_B64_vi : SOP1_Real_vi <0x27, S_XNOR_SAVEEXEC_B64>;
1233 def S_QUADMASK_B32_vi : SOP1_Real_vi <0x28, S_QUADMASK_B32>;
1234 def S_QUADMASK_B64_vi : SOP1_Real_vi <0x29, S_QUADMASK_B64>;
1235 def S_MOVRELS_B32_vi : SOP1_Real_vi <0x2a, S_MOVRELS_B32>;
1236 def S_MOVRELS_B64_vi : SOP1_Real_vi <0x2b, S_MOVRELS_B64>;
1237 def S_MOVRELD_B32_vi : SOP1_Real_vi <0x2c, S_MOVRELD_B32>;
1238 def S_MOVRELD_B64_vi : SOP1_Real_vi <0x2d, S_MOVRELD_B64>;
1239 def S_CBRANCH_JOIN_vi : SOP1_Real_vi <0x2e, S_CBRANCH_JOIN>;
1240 def S_MOV_REGRD_B32_vi : SOP1_Real_vi <0x2f, S_MOV_REGRD_B32>;
1241 def S_ABS_I32_vi : SOP1_Real_vi <0x30, S_ABS_I32>;
1242 def S_MOV_FED_B32_vi : SOP1_Real_vi <0x31, S_MOV_FED_B32>;
1243 def S_SET_GPR_IDX_IDX_vi : SOP1_Real_vi <0x32, S_SET_GPR_IDX_IDX>;
1245 def S_ADD_U32_vi : SOP2_Real_vi <0x00, S_ADD_U32>;
1246 def S_ADD_I32_vi : SOP2_Real_vi <0x02, S_ADD_I32>;
1247 def S_SUB_U32_vi : SOP2_Real_vi <0x01, S_SUB_U32>;
1248 def S_SUB_I32_vi : SOP2_Real_vi <0x03, S_SUB_I32>;
1249 def S_ADDC_U32_vi : SOP2_Real_vi <0x04, S_ADDC_U32>;
1250 def S_SUBB_U32_vi : SOP2_Real_vi <0x05, S_SUBB_U32>;
1251 def S_MIN_I32_vi : SOP2_Real_vi <0x06, S_MIN_I32>;
1252 def S_MIN_U32_vi : SOP2_Real_vi <0x07, S_MIN_U32>;
1253 def S_MAX_I32_vi : SOP2_Real_vi <0x08, S_MAX_I32>;
1254 def S_MAX_U32_vi : SOP2_Real_vi <0x09, S_MAX_U32>;
1255 def S_CSELECT_B32_vi : SOP2_Real_vi <0x0a, S_CSELECT_B32>;
1256 def S_CSELECT_B64_vi : SOP2_Real_vi <0x0b, S_CSELECT_B64>;
1257 def S_AND_B32_vi : SOP2_Real_vi <0x0c, S_AND_B32>;
1258 def S_AND_B64_vi : SOP2_Real_vi <0x0d, S_AND_B64>;
1259 def S_OR_B32_vi : SOP2_Real_vi <0x0e, S_OR_B32>;
1260 def S_OR_B64_vi : SOP2_Real_vi <0x0f, S_OR_B64>;
1261 def S_XOR_B32_vi : SOP2_Real_vi <0x10, S_XOR_B32>;
1262 def S_XOR_B64_vi : SOP2_Real_vi <0x11, S_XOR_B64>;
1263 def S_ANDN2_B32_vi : SOP2_Real_vi <0x12, S_ANDN2_B32>;
1264 def S_ANDN2_B64_vi : SOP2_Real_vi <0x13, S_ANDN2_B64>;
1265 def S_ORN2_B32_vi : SOP2_Real_vi <0x14, S_ORN2_B32>;
1266 def S_ORN2_B64_vi : SOP2_Real_vi <0x15, S_ORN2_B64>;
1267 def S_NAND_B32_vi : SOP2_Real_vi <0x16, S_NAND_B32>;
1268 def S_NAND_B64_vi : SOP2_Real_vi <0x17, S_NAND_B64>;
1269 def S_NOR_B32_vi : SOP2_Real_vi <0x18, S_NOR_B32>;
1270 def S_NOR_B64_vi : SOP2_Real_vi <0x19, S_NOR_B64>;
1271 def S_XNOR_B32_vi : SOP2_Real_vi <0x1a, S_XNOR_B32>;
1272 def S_XNOR_B64_vi : SOP2_Real_vi <0x1b, S_XNOR_B64>;
1273 def S_LSHL_B32_vi : SOP2_Real_vi <0x1c, S_LSHL_B32>;
1274 def S_LSHL_B64_vi : SOP2_Real_vi <0x1d, S_LSHL_B64>;
1275 def S_LSHR_B32_vi : SOP2_Real_vi <0x1e, S_LSHR_B32>;
1276 def S_LSHR_B64_vi : SOP2_Real_vi <0x1f, S_LSHR_B64>;
1277 def S_ASHR_I32_vi : SOP2_Real_vi <0x20, S_ASHR_I32>;
1278 def S_ASHR_I64_vi : SOP2_Real_vi <0x21, S_ASHR_I64>;
1279 def S_BFM_B32_vi : SOP2_Real_vi <0x22, S_BFM_B32>;
1280 def S_BFM_B64_vi : SOP2_Real_vi <0x23, S_BFM_B64>;
1281 def S_MUL_I32_vi : SOP2_Real_vi <0x24, S_MUL_I32>;
1282 def S_BFE_U32_vi : SOP2_Real_vi <0x25, S_BFE_U32>;
1283 def S_BFE_I32_vi : SOP2_Real_vi <0x26, S_BFE_I32>;
1284 def S_BFE_U64_vi : SOP2_Real_vi <0x27, S_BFE_U64>;
1285 def S_BFE_I64_vi : SOP2_Real_vi <0x28, S_BFE_I64>;
1286 def S_CBRANCH_G_FORK_vi : SOP2_Real_vi <0x29, S_CBRANCH_G_FORK>;
1287 def S_ABSDIFF_I32_vi : SOP2_Real_vi <0x2a, S_ABSDIFF_I32>;
1288 def S_PACK_LL_B32_B16_vi : SOP2_Real_vi <0x32, S_PACK_LL_B32_B16>;
1289 def S_PACK_LH_B32_B16_vi : SOP2_Real_vi <0x33, S_PACK_LH_B32_B16>;
1290 def S_PACK_HH_B32_B16_vi : SOP2_Real_vi <0x34, S_PACK_HH_B32_B16>;
1291 def S_RFE_RESTORE_B64_vi : SOP2_Real_vi <0x2b, S_RFE_RESTORE_B64>;
1293 def S_MOVK_I32_vi : SOPK_Real_vi <0x00, S_MOVK_I32>;
1294 def S_CMOVK_I32_vi : SOPK_Real_vi <0x01, S_CMOVK_I32>;
1295 def S_CMPK_EQ_I32_vi : SOPK_Real_vi <0x02, S_CMPK_EQ_I32>;
1296 def S_CMPK_LG_I32_vi : SOPK_Real_vi <0x03, S_CMPK_LG_I32>;
1297 def S_CMPK_GT_I32_vi : SOPK_Real_vi <0x04, S_CMPK_GT_I32>;
1298 def S_CMPK_GE_I32_vi : SOPK_Real_vi <0x05, S_CMPK_GE_I32>;
1299 def S_CMPK_LT_I32_vi : SOPK_Real_vi <0x06, S_CMPK_LT_I32>;
1300 def S_CMPK_LE_I32_vi : SOPK_Real_vi <0x07, S_CMPK_LE_I32>;
1301 def S_CMPK_EQ_U32_vi : SOPK_Real_vi <0x08, S_CMPK_EQ_U32>;
1302 def S_CMPK_LG_U32_vi : SOPK_Real_vi <0x09, S_CMPK_LG_U32>;
1303 def S_CMPK_GT_U32_vi : SOPK_Real_vi <0x0A, S_CMPK_GT_U32>;
1304 def S_CMPK_GE_U32_vi : SOPK_Real_vi <0x0B, S_CMPK_GE_U32>;
1305 def S_CMPK_LT_U32_vi : SOPK_Real_vi <0x0C, S_CMPK_LT_U32>;
1306 def S_CMPK_LE_U32_vi : SOPK_Real_vi <0x0D, S_CMPK_LE_U32>;
1307 def S_ADDK_I32_vi : SOPK_Real_vi <0x0E, S_ADDK_I32>;
1308 def S_MULK_I32_vi : SOPK_Real_vi <0x0F, S_MULK_I32>;
1309 def S_CBRANCH_I_FORK_vi : SOPK_Real_vi <0x10, S_CBRANCH_I_FORK>;
1310 def S_GETREG_B32_vi : SOPK_Real_vi <0x11, S_GETREG_B32>;
1311 def S_SETREG_B32_vi : SOPK_Real_vi <0x12, S_SETREG_B32>;
1312 //def S_GETREG_REGRD_B32_vi : SOPK_Real_vi <0x13, S_GETREG_REGRD_B32>; // see pseudo for comments
1313 def S_SETREG_IMM32_B32_vi : SOPK_Real64<0x14, S_SETREG_IMM32_B32>,
1314 Select_vi<S_SETREG_IMM32_B32.Mnemonic>;