1 //===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 #include "AMDGPUBaseInfo.h"
12 #include "SIDefines.h"
13 #include "llvm/ADT/StringRef.h"
14 #include "llvm/ADT/Triple.h"
15 #include "llvm/CodeGen/MachineMemOperand.h"
16 #include "llvm/IR/Attributes.h"
17 #include "llvm/IR/Constants.h"
18 #include "llvm/IR/Function.h"
19 #include "llvm/IR/GlobalValue.h"
20 #include "llvm/IR/Instruction.h"
21 #include "llvm/IR/LLVMContext.h"
22 #include "llvm/IR/Module.h"
23 #include "llvm/MC/MCContext.h"
24 #include "llvm/MC/MCInstrDesc.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCSectionELF.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/SubtargetFeature.h"
29 #include "llvm/Support/Casting.h"
30 #include "llvm/Support/ELF.h"
31 #include "llvm/Support/ErrorHandling.h"
32 #include "llvm/Support/MathExtras.h"
39 #include "MCTargetDesc/AMDGPUMCTargetDesc.h"
42 #define GET_INSTRINFO_NAMED_OPS
43 #include "AMDGPUGenInstrInfo.inc"
44 #undef GET_INSTRINFO_NAMED_OPS
48 /// \returns Bit mask for given bit \p Shift and bit \p Width.
49 unsigned getBitMask(unsigned Shift, unsigned Width) {
50 return ((1 << Width) - 1) << Shift;
53 /// \brief Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
55 /// \returns Packed \p Dst.
56 unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
57 Dst &= ~(1 << Shift) & ~getBitMask(Shift, Width);
58 Dst |= (Src << Shift) & getBitMask(Shift, Width);
62 /// \brief Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
64 /// \returns Unpacked bits.
65 unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
66 return (Src & getBitMask(Shift, Width)) >> Shift;
69 /// \returns Vmcnt bit shift (lower bits).
70 unsigned getVmcntBitShiftLo() { return 0; }
72 /// \returns Vmcnt bit width (lower bits).
73 unsigned getVmcntBitWidthLo() { return 4; }
75 /// \returns Expcnt bit shift.
76 unsigned getExpcntBitShift() { return 4; }
78 /// \returns Expcnt bit width.
79 unsigned getExpcntBitWidth() { return 3; }
81 /// \returns Lgkmcnt bit shift.
82 unsigned getLgkmcntBitShift() { return 8; }
84 /// \returns Lgkmcnt bit width.
85 unsigned getLgkmcntBitWidth() { return 4; }
87 /// \returns Vmcnt bit shift (higher bits).
88 unsigned getVmcntBitShiftHi() { return 14; }
90 /// \returns Vmcnt bit width (higher bits).
91 unsigned getVmcntBitWidthHi() { return 2; }
93 } // end namespace anonymous
97 static cl::opt<bool> EnablePackedInlinableLiterals(
98 "enable-packed-inlinable-literals",
99 cl::desc("Enable packed inlinable literals (v2f16, v2i16)"),
106 IsaVersion getIsaVersion(const FeatureBitset &Features) {
108 if (Features.test(FeatureISAVersion7_0_0))
110 if (Features.test(FeatureISAVersion7_0_1))
112 if (Features.test(FeatureISAVersion7_0_2))
116 if (Features.test(FeatureISAVersion8_0_0))
118 if (Features.test(FeatureISAVersion8_0_1))
120 if (Features.test(FeatureISAVersion8_0_2))
122 if (Features.test(FeatureISAVersion8_0_3))
124 if (Features.test(FeatureISAVersion8_0_4))
126 if (Features.test(FeatureISAVersion8_1_0))
130 if (Features.test(FeatureISAVersion9_0_0))
132 if (Features.test(FeatureISAVersion9_0_1))
135 if (!Features.test(FeatureGCN) || Features.test(FeatureSouthernIslands))
140 unsigned getWavefrontSize(const FeatureBitset &Features) {
141 if (Features.test(FeatureWavefrontSize16))
143 if (Features.test(FeatureWavefrontSize32))
149 unsigned getLocalMemorySize(const FeatureBitset &Features) {
150 if (Features.test(FeatureLocalMemorySize32768))
152 if (Features.test(FeatureLocalMemorySize65536))
158 unsigned getEUsPerCU(const FeatureBitset &Features) {
162 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
163 unsigned FlatWorkGroupSize) {
164 if (!Features.test(FeatureGCN))
166 unsigned N = getWavesPerWorkGroup(Features, FlatWorkGroupSize);
170 return std::min(N, 16u);
173 unsigned getMaxWavesPerCU(const FeatureBitset &Features) {
174 return getMaxWavesPerEU(Features) * getEUsPerCU(Features);
177 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
178 unsigned FlatWorkGroupSize) {
179 return getWavesPerWorkGroup(Features, FlatWorkGroupSize);
182 unsigned getMinWavesPerEU(const FeatureBitset &Features) {
186 unsigned getMaxWavesPerEU(const FeatureBitset &Features) {
187 if (!Features.test(FeatureGCN))
189 // FIXME: Need to take scratch memory into account.
193 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
194 unsigned FlatWorkGroupSize) {
195 return alignTo(getMaxWavesPerCU(Features, FlatWorkGroupSize),
196 getEUsPerCU(Features)) / getEUsPerCU(Features);
199 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features) {
203 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features) {
207 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
208 unsigned FlatWorkGroupSize) {
209 return alignTo(FlatWorkGroupSize, getWavefrontSize(Features)) /
210 getWavefrontSize(Features);
213 unsigned getSGPRAllocGranule(const FeatureBitset &Features) {
214 IsaVersion Version = getIsaVersion(Features);
215 if (Version.Major >= 8)
220 unsigned getSGPREncodingGranule(const FeatureBitset &Features) {
224 unsigned getTotalNumSGPRs(const FeatureBitset &Features) {
225 IsaVersion Version = getIsaVersion(Features);
226 if (Version.Major >= 8)
231 unsigned getAddressableNumSGPRs(const FeatureBitset &Features) {
232 if (Features.test(FeatureSGPRInitBug))
233 return FIXED_NUM_SGPRS_FOR_INIT_BUG;
235 IsaVersion Version = getIsaVersion(Features);
236 if (Version.Major >= 8)
241 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
242 assert(WavesPerEU != 0);
244 if (WavesPerEU >= getMaxWavesPerEU(Features))
246 unsigned MinNumSGPRs =
247 alignDown(getTotalNumSGPRs(Features) / (WavesPerEU + 1),
248 getSGPRAllocGranule(Features)) + 1;
249 return std::min(MinNumSGPRs, getAddressableNumSGPRs(Features));
252 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
254 assert(WavesPerEU != 0);
256 IsaVersion Version = getIsaVersion(Features);
257 unsigned MaxNumSGPRs = alignDown(getTotalNumSGPRs(Features) / WavesPerEU,
258 getSGPRAllocGranule(Features));
259 unsigned AddressableNumSGPRs = getAddressableNumSGPRs(Features);
260 if (Version.Major >= 8 && !Addressable)
261 AddressableNumSGPRs = 112;
262 return std::min(MaxNumSGPRs, AddressableNumSGPRs);
265 unsigned getVGPRAllocGranule(const FeatureBitset &Features) {
269 unsigned getVGPREncodingGranule(const FeatureBitset &Features) {
270 return getVGPRAllocGranule(Features);
273 unsigned getTotalNumVGPRs(const FeatureBitset &Features) {
277 unsigned getAddressableNumVGPRs(const FeatureBitset &Features) {
278 return getTotalNumVGPRs(Features);
281 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
282 assert(WavesPerEU != 0);
284 if (WavesPerEU >= getMaxWavesPerEU(Features))
286 unsigned MinNumVGPRs =
287 alignDown(getTotalNumVGPRs(Features) / (WavesPerEU + 1),
288 getVGPRAllocGranule(Features)) + 1;
289 return std::min(MinNumVGPRs, getAddressableNumVGPRs(Features));
292 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU) {
293 assert(WavesPerEU != 0);
295 unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(Features) / WavesPerEU,
296 getVGPRAllocGranule(Features));
297 unsigned AddressableNumVGPRs = getAddressableNumVGPRs(Features);
298 return std::min(MaxNumVGPRs, AddressableNumVGPRs);
301 } // end namespace IsaInfo
303 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
304 const FeatureBitset &Features) {
305 IsaInfo::IsaVersion ISA = IsaInfo::getIsaVersion(Features);
307 memset(&Header, 0, sizeof(Header));
309 Header.amd_kernel_code_version_major = 1;
310 Header.amd_kernel_code_version_minor = 1;
311 Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
312 Header.amd_machine_version_major = ISA.Major;
313 Header.amd_machine_version_minor = ISA.Minor;
314 Header.amd_machine_version_stepping = ISA.Stepping;
315 Header.kernel_code_entry_byte_offset = sizeof(Header);
316 // wavefront_size is specified as a power of 2: 2^6 = 64 threads.
317 Header.wavefront_size = 6;
319 // If the code object does not support indirect functions, then the value must
321 Header.call_convention = -1;
323 // These alignment values are specified in powers of two, so alignment =
324 // 2^n. The minimum alignment is 2^4 = 16.
325 Header.kernarg_segment_alignment = 4;
326 Header.group_segment_alignment = 4;
327 Header.private_segment_alignment = 4;
330 MCSection *getHSATextSection(MCContext &Ctx) {
331 return Ctx.getELFSection(".hsatext", ELF::SHT_PROGBITS,
332 ELF::SHF_ALLOC | ELF::SHF_WRITE |
334 ELF::SHF_AMDGPU_HSA_AGENT |
335 ELF::SHF_AMDGPU_HSA_CODE);
338 MCSection *getHSADataGlobalAgentSection(MCContext &Ctx) {
339 return Ctx.getELFSection(".hsadata_global_agent", ELF::SHT_PROGBITS,
340 ELF::SHF_ALLOC | ELF::SHF_WRITE |
341 ELF::SHF_AMDGPU_HSA_GLOBAL |
342 ELF::SHF_AMDGPU_HSA_AGENT);
345 MCSection *getHSADataGlobalProgramSection(MCContext &Ctx) {
346 return Ctx.getELFSection(".hsadata_global_program", ELF::SHT_PROGBITS,
347 ELF::SHF_ALLOC | ELF::SHF_WRITE |
348 ELF::SHF_AMDGPU_HSA_GLOBAL);
351 MCSection *getHSARodataReadonlyAgentSection(MCContext &Ctx) {
352 return Ctx.getELFSection(".hsarodata_readonly_agent", ELF::SHT_PROGBITS,
353 ELF::SHF_ALLOC | ELF::SHF_AMDGPU_HSA_READONLY |
354 ELF::SHF_AMDGPU_HSA_AGENT);
357 bool isGroupSegment(const GlobalValue *GV, AMDGPUAS AS) {
358 return GV->getType()->getAddressSpace() == AS.LOCAL_ADDRESS;
361 bool isGlobalSegment(const GlobalValue *GV, AMDGPUAS AS) {
362 return GV->getType()->getAddressSpace() == AS.GLOBAL_ADDRESS;
365 bool isReadOnlySegment(const GlobalValue *GV, AMDGPUAS AS) {
366 return GV->getType()->getAddressSpace() == AS.CONSTANT_ADDRESS;
369 bool shouldEmitConstantsToTextSection(const Triple &TT) {
370 return TT.getOS() != Triple::AMDHSA;
373 int getIntegerAttribute(const Function &F, StringRef Name, int Default) {
374 Attribute A = F.getFnAttribute(Name);
375 int Result = Default;
377 if (A.isStringAttribute()) {
378 StringRef Str = A.getValueAsString();
379 if (Str.getAsInteger(0, Result)) {
380 LLVMContext &Ctx = F.getContext();
381 Ctx.emitError("can't parse integer attribute " + Name);
388 std::pair<int, int> getIntegerPairAttribute(const Function &F,
390 std::pair<int, int> Default,
391 bool OnlyFirstRequired) {
392 Attribute A = F.getFnAttribute(Name);
393 if (!A.isStringAttribute())
396 LLVMContext &Ctx = F.getContext();
397 std::pair<int, int> Ints = Default;
398 std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
399 if (Strs.first.trim().getAsInteger(0, Ints.first)) {
400 Ctx.emitError("can't parse first integer attribute " + Name);
403 if (Strs.second.trim().getAsInteger(0, Ints.second)) {
404 if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
405 Ctx.emitError("can't parse second integer attribute " + Name);
413 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version) {
414 unsigned VmcntLo = (1 << getVmcntBitWidthLo()) - 1;
415 if (Version.Major < 9)
418 unsigned VmcntHi = ((1 << getVmcntBitWidthHi()) - 1) << getVmcntBitWidthLo();
419 return VmcntLo | VmcntHi;
422 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version) {
423 return (1 << getExpcntBitWidth()) - 1;
426 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version) {
427 return (1 << getLgkmcntBitWidth()) - 1;
430 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version) {
431 unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(), getVmcntBitWidthLo());
432 unsigned Expcnt = getBitMask(getExpcntBitShift(), getExpcntBitWidth());
433 unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(), getLgkmcntBitWidth());
434 unsigned Waitcnt = VmcntLo | Expcnt | Lgkmcnt;
435 if (Version.Major < 9)
438 unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(), getVmcntBitWidthHi());
439 return Waitcnt | VmcntHi;
442 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
444 unpackBits(Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
445 if (Version.Major < 9)
449 unpackBits(Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
450 VmcntHi <<= getVmcntBitWidthLo();
451 return VmcntLo | VmcntHi;
454 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
455 return unpackBits(Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
458 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt) {
459 return unpackBits(Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
462 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
463 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
464 Vmcnt = decodeVmcnt(Version, Waitcnt);
465 Expcnt = decodeExpcnt(Version, Waitcnt);
466 Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
469 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
472 packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(), getVmcntBitWidthLo());
473 if (Version.Major < 9)
476 Vmcnt >>= getVmcntBitWidthLo();
477 return packBits(Vmcnt, Waitcnt, getVmcntBitShiftHi(), getVmcntBitWidthHi());
480 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
482 return packBits(Expcnt, Waitcnt, getExpcntBitShift(), getExpcntBitWidth());
485 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
487 return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(), getLgkmcntBitWidth());
490 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
491 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
492 unsigned Waitcnt = getWaitcntBitMask(Version);
493 Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
494 Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
495 Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
499 unsigned getInitialPSInputAddr(const Function &F) {
500 return getIntegerAttribute(F, "InitialPSInputAddr", 0);
503 bool isShader(CallingConv::ID cc) {
505 case CallingConv::AMDGPU_VS:
506 case CallingConv::AMDGPU_HS:
507 case CallingConv::AMDGPU_GS:
508 case CallingConv::AMDGPU_PS:
509 case CallingConv::AMDGPU_CS:
516 bool isCompute(CallingConv::ID cc) {
517 return !isShader(cc) || cc == CallingConv::AMDGPU_CS;
520 bool isEntryFunctionCC(CallingConv::ID CC) {
522 case CallingConv::AMDGPU_KERNEL:
523 case CallingConv::SPIR_KERNEL:
524 case CallingConv::AMDGPU_VS:
525 case CallingConv::AMDGPU_GS:
526 case CallingConv::AMDGPU_PS:
527 case CallingConv::AMDGPU_CS:
528 case CallingConv::AMDGPU_HS:
535 bool isSI(const MCSubtargetInfo &STI) {
536 return STI.getFeatureBits()[AMDGPU::FeatureSouthernIslands];
539 bool isCI(const MCSubtargetInfo &STI) {
540 return STI.getFeatureBits()[AMDGPU::FeatureSeaIslands];
543 bool isVI(const MCSubtargetInfo &STI) {
544 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
547 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
551 case AMDGPU::FLAT_SCR:
553 return isCI(STI) ? AMDGPU::FLAT_SCR_ci : AMDGPU::FLAT_SCR_vi;
555 case AMDGPU::FLAT_SCR_LO:
557 return isCI(STI) ? AMDGPU::FLAT_SCR_LO_ci : AMDGPU::FLAT_SCR_LO_vi;
559 case AMDGPU::FLAT_SCR_HI:
561 return isCI(STI) ? AMDGPU::FLAT_SCR_HI_ci : AMDGPU::FLAT_SCR_HI_vi;
566 unsigned mc2PseudoReg(unsigned Reg) {
568 case AMDGPU::FLAT_SCR_ci:
569 case AMDGPU::FLAT_SCR_vi:
572 case AMDGPU::FLAT_SCR_LO_ci:
573 case AMDGPU::FLAT_SCR_LO_vi:
574 return AMDGPU::FLAT_SCR_LO;
576 case AMDGPU::FLAT_SCR_HI_ci:
577 case AMDGPU::FLAT_SCR_HI_vi:
578 return AMDGPU::FLAT_SCR_HI;
585 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
586 assert(OpNo < Desc.NumOperands);
587 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
588 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
589 OpType <= AMDGPU::OPERAND_SRC_LAST;
592 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
593 assert(OpNo < Desc.NumOperands);
594 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
596 case AMDGPU::OPERAND_REG_IMM_FP32:
597 case AMDGPU::OPERAND_REG_IMM_FP64:
598 case AMDGPU::OPERAND_REG_IMM_FP16:
599 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
600 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
601 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
602 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
609 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
610 assert(OpNo < Desc.NumOperands);
611 unsigned OpType = Desc.OpInfo[OpNo].OperandType;
612 return OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
613 OpType <= AMDGPU::OPERAND_REG_INLINE_C_LAST;
616 // Avoid using MCRegisterClass::getSize, since that function will go away
617 // (move from MC* level to Target* level). Return size in bits.
618 unsigned getRegBitWidth(unsigned RCID) {
620 case AMDGPU::SGPR_32RegClassID:
621 case AMDGPU::VGPR_32RegClassID:
622 case AMDGPU::VS_32RegClassID:
623 case AMDGPU::SReg_32RegClassID:
624 case AMDGPU::SReg_32_XM0RegClassID:
626 case AMDGPU::SGPR_64RegClassID:
627 case AMDGPU::VS_64RegClassID:
628 case AMDGPU::SReg_64RegClassID:
629 case AMDGPU::VReg_64RegClassID:
631 case AMDGPU::VReg_96RegClassID:
633 case AMDGPU::SGPR_128RegClassID:
634 case AMDGPU::SReg_128RegClassID:
635 case AMDGPU::VReg_128RegClassID:
637 case AMDGPU::SReg_256RegClassID:
638 case AMDGPU::VReg_256RegClassID:
640 case AMDGPU::SReg_512RegClassID:
641 case AMDGPU::VReg_512RegClassID:
644 llvm_unreachable("Unexpected register class");
648 unsigned getRegBitWidth(const MCRegisterClass &RC) {
649 return getRegBitWidth(RC.getID());
652 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
654 assert(OpNo < Desc.NumOperands);
655 unsigned RCID = Desc.OpInfo[OpNo].RegClass;
656 return getRegBitWidth(MRI->getRegClass(RCID)) / 8;
659 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
660 if (Literal >= -16 && Literal <= 64)
663 uint64_t Val = static_cast<uint64_t>(Literal);
664 return (Val == DoubleToBits(0.0)) ||
665 (Val == DoubleToBits(1.0)) ||
666 (Val == DoubleToBits(-1.0)) ||
667 (Val == DoubleToBits(0.5)) ||
668 (Val == DoubleToBits(-0.5)) ||
669 (Val == DoubleToBits(2.0)) ||
670 (Val == DoubleToBits(-2.0)) ||
671 (Val == DoubleToBits(4.0)) ||
672 (Val == DoubleToBits(-4.0)) ||
673 (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
676 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
677 if (Literal >= -16 && Literal <= 64)
680 // The actual type of the operand does not seem to matter as long
681 // as the bits match one of the inline immediate values. For example:
683 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
684 // so it is a legal inline immediate.
686 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
687 // floating-point, so it is a legal inline immediate.
689 uint32_t Val = static_cast<uint32_t>(Literal);
690 return (Val == FloatToBits(0.0f)) ||
691 (Val == FloatToBits(1.0f)) ||
692 (Val == FloatToBits(-1.0f)) ||
693 (Val == FloatToBits(0.5f)) ||
694 (Val == FloatToBits(-0.5f)) ||
695 (Val == FloatToBits(2.0f)) ||
696 (Val == FloatToBits(-2.0f)) ||
697 (Val == FloatToBits(4.0f)) ||
698 (Val == FloatToBits(-4.0f)) ||
699 (Val == 0x3e22f983 && HasInv2Pi);
702 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi) {
706 if (Literal >= -16 && Literal <= 64)
709 uint16_t Val = static_cast<uint16_t>(Literal);
710 return Val == 0x3C00 || // 1.0
711 Val == 0xBC00 || // -1.0
712 Val == 0x3800 || // 0.5
713 Val == 0xB800 || // -0.5
714 Val == 0x4000 || // 2.0
715 Val == 0xC000 || // -2.0
716 Val == 0x4400 || // 4.0
717 Val == 0xC400 || // -4.0
718 Val == 0x3118; // 1/2pi
721 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi) {
724 if (!EnablePackedInlinableLiterals)
727 int16_t Lo16 = static_cast<int16_t>(Literal);
728 int16_t Hi16 = static_cast<int16_t>(Literal >> 16);
729 return Lo16 == Hi16 && isInlinableLiteral16(Lo16, HasInv2Pi);
732 bool isUniformMMO(const MachineMemOperand *MMO) {
733 const Value *Ptr = MMO->getValue();
734 // UndefValue means this is a load of a kernel input. These are uniform.
735 // Sometimes LDS instructions have constant pointers.
736 // If Ptr is null, then that means this mem operand contains a
737 // PseudoSourceValue like GOT.
738 if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
739 isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
742 const Instruction *I = dyn_cast<Instruction>(Ptr);
743 return I && I->getMetadata("amdgpu.uniform");
746 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
747 if (isSI(ST) || isCI(ST))
748 return ByteOffset >> 2;
753 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset) {
754 int64_t EncodedOffset = getSMRDEncodedOffset(ST, ByteOffset);
755 return isSI(ST) || isCI(ST) ? isUInt<8>(EncodedOffset) :
756 isUInt<20>(EncodedOffset);
758 } // end namespace AMDGPU
760 } // end namespace llvm
762 const unsigned AMDGPUAS::MAX_COMMON_ADDRESS;
763 const unsigned AMDGPUAS::GLOBAL_ADDRESS;
764 const unsigned AMDGPUAS::LOCAL_ADDRESS;
765 const unsigned AMDGPUAS::PARAM_D_ADDRESS;
766 const unsigned AMDGPUAS::PARAM_I_ADDRESS;
767 const unsigned AMDGPUAS::CONSTANT_BUFFER_0;
768 const unsigned AMDGPUAS::CONSTANT_BUFFER_1;
769 const unsigned AMDGPUAS::CONSTANT_BUFFER_2;
770 const unsigned AMDGPUAS::CONSTANT_BUFFER_3;
771 const unsigned AMDGPUAS::CONSTANT_BUFFER_4;
772 const unsigned AMDGPUAS::CONSTANT_BUFFER_5;
773 const unsigned AMDGPUAS::CONSTANT_BUFFER_6;
774 const unsigned AMDGPUAS::CONSTANT_BUFFER_7;
775 const unsigned AMDGPUAS::CONSTANT_BUFFER_8;
776 const unsigned AMDGPUAS::CONSTANT_BUFFER_9;
777 const unsigned AMDGPUAS::CONSTANT_BUFFER_10;
778 const unsigned AMDGPUAS::CONSTANT_BUFFER_11;
779 const unsigned AMDGPUAS::CONSTANT_BUFFER_12;
780 const unsigned AMDGPUAS::CONSTANT_BUFFER_13;
781 const unsigned AMDGPUAS::CONSTANT_BUFFER_14;
782 const unsigned AMDGPUAS::CONSTANT_BUFFER_15;
783 const unsigned AMDGPUAS::UNKNOWN_ADDRESS_SPACE;
788 AMDGPUAS getAMDGPUAS(Triple T) {
789 auto Env = T.getEnvironmentName();
791 if (Env == "amdgiz" || Env == "amdgizcl") {
793 AS.PRIVATE_ADDRESS = 5;
794 AS.REGION_ADDRESS = 4;
798 AS.PRIVATE_ADDRESS = 0;
799 AS.REGION_ADDRESS = 5;
804 AMDGPUAS getAMDGPUAS(const TargetMachine &M) {
805 return getAMDGPUAS(M.getTargetTriple());
808 AMDGPUAS getAMDGPUAS(const Module &M) {
809 return getAMDGPUAS(Triple(M.getTargetTriple()));
811 } // namespace AMDGPU