1 //===- AMDGPUBaseInfo.h - Top level definitions for AMDGPU ------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #ifndef LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
11 #define LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H
14 #include "AMDKernelCodeT.h"
15 #include "SIDefines.h"
16 #include "llvm/ADT/StringRef.h"
17 #include "llvm/IR/CallingConv.h"
18 #include "llvm/MC/MCInstrDesc.h"
19 #include "llvm/Support/AMDHSAKernelDescriptor.h"
20 #include "llvm/Support/Compiler.h"
21 #include "llvm/Support/ErrorHandling.h"
33 class MCRegisterClass;
36 class MCSubtargetInfo;
37 class MachineMemOperand;
42 #define GET_MIMGBaseOpcode_DECL
43 #define GET_MIMGDim_DECL
44 #define GET_MIMGEncoding_DECL
45 #include "AMDGPUGenSearchableTables.inc"
50 // The closed Vulkan driver sets 96, which limits the wave count to 8 but
51 // doesn't spill SGPRs as much as when 80 is set.
52 FIXED_NUM_SGPRS_FOR_INIT_BUG = 96,
56 /// Instruction set architecture version.
63 /// \returns Isa version for given subtarget \p Features.
64 IsaVersion getIsaVersion(const FeatureBitset &Features);
66 /// Streams isa version string for given subtarget \p STI into \p Stream.
67 void streamIsaVersion(const MCSubtargetInfo *STI, raw_ostream &Stream);
69 /// \returns True if given subtarget \p STI supports code object version 3,
71 bool hasCodeObjectV3(const MCSubtargetInfo *STI);
73 /// \returns Wavefront size for given subtarget \p Features.
74 unsigned getWavefrontSize(const FeatureBitset &Features);
76 /// \returns Local memory size in bytes for given subtarget \p Features.
77 unsigned getLocalMemorySize(const FeatureBitset &Features);
79 /// \returns Number of execution units per compute unit for given subtarget \p
81 unsigned getEUsPerCU(const FeatureBitset &Features);
83 /// \returns Maximum number of work groups per compute unit for given subtarget
84 /// \p Features and limited by given \p FlatWorkGroupSize.
85 unsigned getMaxWorkGroupsPerCU(const FeatureBitset &Features,
86 unsigned FlatWorkGroupSize);
88 /// \returns Maximum number of waves per compute unit for given subtarget \p
89 /// Features without any kind of limitation.
90 unsigned getMaxWavesPerCU(const FeatureBitset &Features);
92 /// \returns Maximum number of waves per compute unit for given subtarget \p
93 /// Features and limited by given \p FlatWorkGroupSize.
94 unsigned getMaxWavesPerCU(const FeatureBitset &Features,
95 unsigned FlatWorkGroupSize);
97 /// \returns Minimum number of waves per execution unit for given subtarget \p
99 unsigned getMinWavesPerEU(const FeatureBitset &Features);
101 /// \returns Maximum number of waves per execution unit for given subtarget \p
102 /// Features without any kind of limitation.
103 unsigned getMaxWavesPerEU();
105 /// \returns Maximum number of waves per execution unit for given subtarget \p
106 /// Features and limited by given \p FlatWorkGroupSize.
107 unsigned getMaxWavesPerEU(const FeatureBitset &Features,
108 unsigned FlatWorkGroupSize);
110 /// \returns Minimum flat work group size for given subtarget \p Features.
111 unsigned getMinFlatWorkGroupSize(const FeatureBitset &Features);
113 /// \returns Maximum flat work group size for given subtarget \p Features.
114 unsigned getMaxFlatWorkGroupSize(const FeatureBitset &Features);
116 /// \returns Number of waves per work group for given subtarget \p Features and
117 /// limited by given \p FlatWorkGroupSize.
118 unsigned getWavesPerWorkGroup(const FeatureBitset &Features,
119 unsigned FlatWorkGroupSize);
121 /// \returns SGPR allocation granularity for given subtarget \p Features.
122 unsigned getSGPRAllocGranule(const FeatureBitset &Features);
124 /// \returns SGPR encoding granularity for given subtarget \p Features.
125 unsigned getSGPREncodingGranule(const FeatureBitset &Features);
127 /// \returns Total number of SGPRs for given subtarget \p Features.
128 unsigned getTotalNumSGPRs(const FeatureBitset &Features);
130 /// \returns Addressable number of SGPRs for given subtarget \p Features.
131 unsigned getAddressableNumSGPRs(const FeatureBitset &Features);
133 /// \returns Minimum number of SGPRs that meets the given number of waves per
134 /// execution unit requirement for given subtarget \p Features.
135 unsigned getMinNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
137 /// \returns Maximum number of SGPRs that meets the given number of waves per
138 /// execution unit requirement for given subtarget \p Features.
139 unsigned getMaxNumSGPRs(const FeatureBitset &Features, unsigned WavesPerEU,
142 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
143 /// Features when the given special registers are used.
144 unsigned getNumExtraSGPRs(const FeatureBitset &Features, bool VCCUsed,
145 bool FlatScrUsed, bool XNACKUsed);
147 /// \returns Number of extra SGPRs implicitly required by given subtarget \p
148 /// Features when the given special registers are used. XNACK is inferred from
150 unsigned getNumExtraSGPRs(const FeatureBitset &Features, bool VCCUsed,
153 /// \returns Number of SGPR blocks needed for given subtarget \p Features when
154 /// \p NumSGPRs are used. \p NumSGPRs should already include any special
156 unsigned getNumSGPRBlocks(const FeatureBitset &Features, unsigned NumSGPRs);
158 /// \returns VGPR allocation granularity for given subtarget \p Features.
159 unsigned getVGPRAllocGranule(const FeatureBitset &Features);
161 /// \returns VGPR encoding granularity for given subtarget \p Features.
162 unsigned getVGPREncodingGranule(const FeatureBitset &Features);
164 /// \returns Total number of VGPRs for given subtarget \p Features.
165 unsigned getTotalNumVGPRs(const FeatureBitset &Features);
167 /// \returns Addressable number of VGPRs for given subtarget \p Features.
168 unsigned getAddressableNumVGPRs(const FeatureBitset &Features);
170 /// \returns Minimum number of VGPRs that meets given number of waves per
171 /// execution unit requirement for given subtarget \p Features.
172 unsigned getMinNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
174 /// \returns Maximum number of VGPRs that meets given number of waves per
175 /// execution unit requirement for given subtarget \p Features.
176 unsigned getMaxNumVGPRs(const FeatureBitset &Features, unsigned WavesPerEU);
178 /// \returns Number of VGPR blocks needed for given subtarget \p Features when
179 /// \p NumVGPRs are used.
180 unsigned getNumVGPRBlocks(const FeatureBitset &Features, unsigned NumSGPRs);
182 } // end namespace IsaInfo
185 int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
187 struct MIMGBaseOpcodeInfo {
188 MIMGBaseOpcode BaseOpcode;
194 uint8_t NumExtraArgs;
197 bool LodOrClampOrMip;
202 const MIMGBaseOpcodeInfo *getMIMGBaseOpcodeInfo(unsigned BaseOpcode);
207 uint8_t NumGradients;
212 const MIMGDimInfo *getMIMGDimInfo(unsigned Dim);
215 int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
216 unsigned VDataDwords, unsigned VAddrDwords);
219 int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels);
222 int getMCOpcode(uint16_t Opcode, unsigned Gen);
224 void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header,
225 const FeatureBitset &Features);
227 amdhsa::kernel_descriptor_t getDefaultAmdhsaKernelDescriptor();
229 bool isGroupSegment(const GlobalValue *GV);
230 bool isGlobalSegment(const GlobalValue *GV);
231 bool isReadOnlySegment(const GlobalValue *GV);
233 /// \returns True if constants should be emitted to .text section for given
234 /// target triple \p TT, false otherwise.
235 bool shouldEmitConstantsToTextSection(const Triple &TT);
237 /// \returns Integer value requested using \p F's \p Name attribute.
239 /// \returns \p Default if attribute is not present.
241 /// \returns \p Default and emits error if requested value cannot be converted
243 int getIntegerAttribute(const Function &F, StringRef Name, int Default);
245 /// \returns A pair of integer values requested using \p F's \p Name attribute
246 /// in "first[,second]" format ("second" is optional unless \p OnlyFirstRequired
249 /// \returns \p Default if attribute is not present.
251 /// \returns \p Default and emits error if one of the requested values cannot be
252 /// converted to integer, or \p OnlyFirstRequired is false and "second" value is
254 std::pair<int, int> getIntegerPairAttribute(const Function &F,
256 std::pair<int, int> Default,
257 bool OnlyFirstRequired = false);
259 /// \returns Vmcnt bit mask for given isa \p Version.
260 unsigned getVmcntBitMask(const IsaInfo::IsaVersion &Version);
262 /// \returns Expcnt bit mask for given isa \p Version.
263 unsigned getExpcntBitMask(const IsaInfo::IsaVersion &Version);
265 /// \returns Lgkmcnt bit mask for given isa \p Version.
266 unsigned getLgkmcntBitMask(const IsaInfo::IsaVersion &Version);
268 /// \returns Waitcnt bit mask for given isa \p Version.
269 unsigned getWaitcntBitMask(const IsaInfo::IsaVersion &Version);
271 /// \returns Decoded Vmcnt from given \p Waitcnt for given isa \p Version.
272 unsigned decodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
274 /// \returns Decoded Expcnt from given \p Waitcnt for given isa \p Version.
275 unsigned decodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
277 /// \returns Decoded Lgkmcnt from given \p Waitcnt for given isa \p Version.
278 unsigned decodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt);
280 /// Decodes Vmcnt, Expcnt and Lgkmcnt from given \p Waitcnt for given isa
281 /// \p Version, and writes decoded values into \p Vmcnt, \p Expcnt and
282 /// \p Lgkmcnt respectively.
284 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are decoded as follows:
285 /// \p Vmcnt = \p Waitcnt[3:0] (pre-gfx9 only)
286 /// \p Vmcnt = \p Waitcnt[3:0] | \p Waitcnt[15:14] (gfx9+ only)
287 /// \p Expcnt = \p Waitcnt[6:4]
288 /// \p Lgkmcnt = \p Waitcnt[11:8]
289 void decodeWaitcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
290 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt);
292 /// \returns \p Waitcnt with encoded \p Vmcnt for given isa \p Version.
293 unsigned encodeVmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
296 /// \returns \p Waitcnt with encoded \p Expcnt for given isa \p Version.
297 unsigned encodeExpcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
300 /// \returns \p Waitcnt with encoded \p Lgkmcnt for given isa \p Version.
301 unsigned encodeLgkmcnt(const IsaInfo::IsaVersion &Version, unsigned Waitcnt,
304 /// Encodes \p Vmcnt, \p Expcnt and \p Lgkmcnt into Waitcnt for given isa
307 /// \details \p Vmcnt, \p Expcnt and \p Lgkmcnt are encoded as follows:
308 /// Waitcnt[3:0] = \p Vmcnt (pre-gfx9 only)
309 /// Waitcnt[3:0] = \p Vmcnt[3:0] (gfx9+ only)
310 /// Waitcnt[6:4] = \p Expcnt
311 /// Waitcnt[11:8] = \p Lgkmcnt
312 /// Waitcnt[15:14] = \p Vmcnt[5:4] (gfx9+ only)
314 /// \returns Waitcnt with encoded \p Vmcnt, \p Expcnt and \p Lgkmcnt for given
316 unsigned encodeWaitcnt(const IsaInfo::IsaVersion &Version,
317 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt);
319 unsigned getInitialPSInputAddr(const Function &F);
322 bool isShader(CallingConv::ID CC);
325 bool isCompute(CallingConv::ID CC);
328 bool isEntryFunctionCC(CallingConv::ID CC);
330 // FIXME: Remove this when calling conventions cleaned up
332 inline bool isKernel(CallingConv::ID CC) {
334 case CallingConv::AMDGPU_KERNEL:
335 case CallingConv::SPIR_KERNEL:
342 bool hasXNACK(const MCSubtargetInfo &STI);
343 bool hasMIMG_R128(const MCSubtargetInfo &STI);
344 bool hasPackedD16(const MCSubtargetInfo &STI);
346 bool isSI(const MCSubtargetInfo &STI);
347 bool isCI(const MCSubtargetInfo &STI);
348 bool isVI(const MCSubtargetInfo &STI);
349 bool isGFX9(const MCSubtargetInfo &STI);
351 /// Is Reg - scalar register
352 bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI);
354 /// Is there any intersection between registers
355 bool isRegIntersect(unsigned Reg0, unsigned Reg1, const MCRegisterInfo* TRI);
357 /// If \p Reg is a pseudo reg, return the correct hardware register given
358 /// \p STI otherwise return \p Reg.
359 unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI);
361 /// Convert hardware register \p Reg to a pseudo register
363 unsigned mc2PseudoReg(unsigned Reg);
365 /// Can this operand also contain immediate values?
366 bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo);
368 /// Is this floating-point operand?
369 bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo);
371 /// Does this opearnd support only inlinable literals?
372 bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo);
374 /// Get the size in bits of a register from the register class \p RC.
375 unsigned getRegBitWidth(unsigned RCID);
377 /// Get the size in bits of a register from the register class \p RC.
378 unsigned getRegBitWidth(const MCRegisterClass &RC);
380 /// Get size of register operand
381 unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc,
385 inline unsigned getOperandSize(const MCOperandInfo &OpInfo) {
386 switch (OpInfo.OperandType) {
387 case AMDGPU::OPERAND_REG_IMM_INT32:
388 case AMDGPU::OPERAND_REG_IMM_FP32:
389 case AMDGPU::OPERAND_REG_INLINE_C_INT32:
390 case AMDGPU::OPERAND_REG_INLINE_C_FP32:
393 case AMDGPU::OPERAND_REG_IMM_INT64:
394 case AMDGPU::OPERAND_REG_IMM_FP64:
395 case AMDGPU::OPERAND_REG_INLINE_C_INT64:
396 case AMDGPU::OPERAND_REG_INLINE_C_FP64:
399 case AMDGPU::OPERAND_REG_IMM_INT16:
400 case AMDGPU::OPERAND_REG_IMM_FP16:
401 case AMDGPU::OPERAND_REG_INLINE_C_INT16:
402 case AMDGPU::OPERAND_REG_INLINE_C_FP16:
403 case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
404 case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
408 llvm_unreachable("unhandled operand type");
413 inline unsigned getOperandSize(const MCInstrDesc &Desc, unsigned OpNo) {
414 return getOperandSize(Desc.OpInfo[OpNo]);
417 /// Is this literal inlinable
419 bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi);
422 bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi);
425 bool isInlinableLiteral16(int16_t Literal, bool HasInv2Pi);
428 bool isInlinableLiteralV216(int32_t Literal, bool HasInv2Pi);
430 bool isArgPassedInSGPR(const Argument *Arg);
432 /// \returns The encoding that will be used for \p ByteOffset in the SMRD
434 int64_t getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
436 /// \returns true if this offset is small enough to fit in the SMRD
437 /// offset field. \p ByteOffset should be the offset in bytes and
438 /// not the encoded offset.
439 bool isLegalSMRDImmOffset(const MCSubtargetInfo &ST, int64_t ByteOffset);
441 /// \returns true if the intrinsic is divergent
442 bool isIntrinsicSourceOfDivergence(unsigned IntrID);
444 } // end namespace AMDGPU
445 } // end namespace llvm
447 #endif // LLVM_LIB_TARGET_AMDGPU_UTILS_AMDGPUBASEINFO_H