1 //===-- VIInstrFormats.td - VI Instruction Encodings ----------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // VI Instruction format definitions.
12 //===----------------------------------------------------------------------===//
14 class DSe_vi <bits<8> op> : Enc64 {
23 let Inst{7-0} = offset0;
24 let Inst{15-8} = offset1;
27 let Inst{31-26} = 0x36; //encoding
28 let Inst{39-32} = addr;
29 let Inst{47-40} = data0;
30 let Inst{55-48} = data1;
31 let Inst{63-56} = vdst;
34 class MUBUFe_vi <bits<7> op> : Enc64 {
47 let Inst{11-0} = offset;
54 let Inst{31-26} = 0x38; //encoding
55 let Inst{39-32} = vaddr;
56 let Inst{47-40} = vdata;
57 let Inst{52-48} = srsrc{6-2};
59 let Inst{63-56} = soffset;
62 class MTBUFe_vi <bits<4> op> : Enc64 {
76 let Inst{11-0} = offset;
81 let Inst{22-19} = dfmt;
82 let Inst{25-23} = nfmt;
83 let Inst{31-26} = 0x3a; //encoding
84 let Inst{39-32} = vaddr;
85 let Inst{47-40} = vdata;
86 let Inst{52-48} = srsrc{6-2};
89 let Inst{63-56} = soffset;
92 class SMEMe_vi <bits<8> op, bit imm> : Enc64 {
97 let Inst{5-0} = sbase{6-1};
98 let Inst{12-6} = sdst;
101 let Inst{25-18} = op;
102 let Inst{31-26} = 0x30; //encoding
105 class SMEM_IMMe_vi <bits<8> op> : SMEMe_vi<op, 1> {
107 let Inst{51-32} = offset;
110 class SMEM_SOFFe_vi <bits<8> op> : SMEMe_vi<op, 0> {
112 let Inst{51-32} = soff;
115 class VOP3a_vi <bits<10> op> : Enc64 {
116 bits<2> src0_modifiers;
118 bits<2> src1_modifiers;
120 bits<2> src2_modifiers;
125 let Inst{8} = src0_modifiers{1};
126 let Inst{9} = src1_modifiers{1};
127 let Inst{10} = src2_modifiers{1};
128 let Inst{15} = clamp;
129 let Inst{25-16} = op;
130 let Inst{31-26} = 0x34; //encoding
131 let Inst{40-32} = src0;
132 let Inst{49-41} = src1;
133 let Inst{58-50} = src2;
134 let Inst{60-59} = omod;
135 let Inst{61} = src0_modifiers{0};
136 let Inst{62} = src1_modifiers{0};
137 let Inst{63} = src2_modifiers{0};
140 class VOP3e_vi <bits<10> op> : VOP3a_vi <op> {
143 let Inst{7-0} = vdst;
146 // Encoding used for VOPC instructions encoded as VOP3
147 // Differs from VOP3e by destination name (sdst) as VOPC doesn't have vector dst
148 class VOP3ce_vi <bits<10> op> : VOP3a_vi <op> {
151 let Inst{7-0} = sdst;
154 class VOP3be_vi <bits<10> op> : Enc64 {
156 bits<2> src0_modifiers;
158 bits<2> src1_modifiers;
160 bits<2> src2_modifiers;
166 let Inst{7-0} = vdst;
167 let Inst{14-8} = sdst;
168 let Inst{15} = clamp;
169 let Inst{25-16} = op;
170 let Inst{31-26} = 0x34; //encoding
171 let Inst{40-32} = src0;
172 let Inst{49-41} = src1;
173 let Inst{58-50} = src2;
174 let Inst{60-59} = omod;
175 let Inst{61} = src0_modifiers{0};
176 let Inst{62} = src1_modifiers{0};
177 let Inst{63} = src2_modifiers{0};
180 class VOP_DPP <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
181 VOPAnyCommon <outs, ins, asm, pattern> {
185 let AsmMatchConverter = !if(!eq(HasMods,1), "cvtDPP", "");
188 class VOP_DPPe : Enc64 {
189 bits<2> src0_modifiers;
191 bits<2> src1_modifiers;
197 let Inst{39-32} = src0;
198 let Inst{48-40} = dpp_ctrl;
199 let Inst{51} = bound_ctrl;
200 let Inst{52} = src0_modifiers{0}; // src0_neg
201 let Inst{53} = src0_modifiers{1}; // src0_abs
202 let Inst{54} = src1_modifiers{0}; // src1_neg
203 let Inst{55} = src1_modifiers{1}; // src1_abs
204 let Inst{59-56} = bank_mask;
205 let Inst{63-60} = row_mask;
208 class VOP1_DPPe <bits<8> op> : VOP_DPPe {
211 let Inst{8-0} = 0xfa; // dpp
213 let Inst{24-17} = vdst;
214 let Inst{31-25} = 0x3f; //encoding
217 class VOP2_DPPe <bits<6> op> : VOP_DPPe {
221 let Inst{8-0} = 0xfa; //dpp
222 let Inst{16-9} = src1;
223 let Inst{24-17} = vdst;
224 let Inst{30-25} = op;
225 let Inst{31} = 0x0; //encoding
228 class VOP_SDWA <dag outs, dag ins, string asm, list<dag> pattern, bit HasMods = 0> :
229 VOPAnyCommon <outs, ins, asm, pattern> {
234 class VOP_SDWAe : Enc64 {
237 bits<2> src0_fmodifiers; // {abs,neg}
238 bits<1> src0_imodifiers; // sext
240 bits<2> src1_fmodifiers;
241 bits<1> src1_imodifiers;
246 let Inst{39-32} = src0;
247 let Inst{42-40} = dst_sel;
248 let Inst{44-43} = dst_unused;
249 let Inst{45} = clamp;
250 let Inst{50-48} = src0_sel;
251 let Inst{53-52} = src0_fmodifiers;
252 let Inst{51} = src0_imodifiers;
253 let Inst{58-56} = src1_sel;
254 let Inst{61-60} = src1_fmodifiers;
255 let Inst{59} = src1_imodifiers;
258 class VOP1_SDWAe <bits<8> op> : VOP_SDWAe {
261 let Inst{8-0} = 0xf9; // sdwa
263 let Inst{24-17} = vdst;
264 let Inst{31-25} = 0x3f; // encoding
267 class VOP2_SDWAe <bits<6> op> : VOP_SDWAe {
271 let Inst{8-0} = 0xf9; // sdwa
272 let Inst{16-9} = src1;
273 let Inst{24-17} = vdst;
274 let Inst{30-25} = op;
275 let Inst{31} = 0x0; // encoding
278 class VOPC_SDWAe <bits<8> op> : VOP_SDWAe {
281 let Inst{8-0} = 0xf9; // sdwa
282 let Inst{16-9} = src1;
283 let Inst{24-17} = op;
284 let Inst{31-25} = 0x3e; // encoding
286 // VOPC disallows dst_sel and dst_unused as they have no effect on destination
287 let Inst{42-40} = 0x6;
288 let Inst{44-43} = 0x2;
291 class EXPe_vi : EXPe {
292 let Inst{31-26} = 0x31; //encoding
295 class VINTRPe_vi <bits<2> op> : VINTRPe <op> {
296 let Inst{31-26} = 0x35; // encoding