1 //===-- VOP1Instructions.td - Vector Instruction Defintions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class VOP1e <bits<8> op, VOPProfile P> : Enc32 {
18 let Inst{8-0} = !if(P.HasSrc0, src0{8-0}, 0);
20 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
21 let Inst{31-25} = 0x3f; //encoding
24 class VOP1_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
27 let Inst{8-0} = 0xf9; // sdwa
29 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
30 let Inst{31-25} = 0x3f; // encoding
33 class VOP1_Pseudo <string opName, VOPProfile P, list<dag> pattern=[]> :
34 InstSI <P.Outs32, P.Ins32, "", pattern>,
36 SIMCInstr <opName#"_e32", SIEncodingFamily.NONE>,
37 MnemonicAlias<opName#"_e32", opName> {
40 let isCodeGenOnly = 1;
41 let UseNamedOperandTable = 1;
43 string Mnemonic = opName;
44 string AsmOperands = P.Asm32;
49 let hasSideEffects = 0;
50 let SubtargetPredicate = isGCN;
56 let AsmVariantName = AMDGPUAsmVariants.Default;
61 class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily> :
62 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
63 SIMCInstr <ps.PseudoInstr, EncodingFamily> {
66 let isCodeGenOnly = 0;
68 let Constraints = ps.Constraints;
69 let DisableEncoding = ps.DisableEncoding;
71 // copy relevant pseudo op flags
72 let SubtargetPredicate = ps.SubtargetPredicate;
73 let AsmMatchConverter = ps.AsmMatchConverter;
74 let AsmVariantName = ps.AsmVariantName;
75 let Constraints = ps.Constraints;
76 let DisableEncoding = ps.DisableEncoding;
77 let TSFlags = ps.TSFlags;
80 class VOP1_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
81 VOP_SDWA_Pseudo <OpName, P, pattern> {
82 let AsmMatchConverter = "cvtSdwaVOP1";
85 class getVOP1Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
86 list<dag> ret = !if(P.HasModifiers,
87 [(set P.DstVT:$vdst, (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0,
88 i32:$src0_modifiers, i1:$clamp, i32:$omod))))],
89 [(set P.DstVT:$vdst, (node P.Src0VT:$src0))]);
92 multiclass VOP1Inst <string opName, VOPProfile P,
93 SDPatternOperator node = null_frag> {
94 def _e32 : VOP1_Pseudo <opName, P>;
95 def _e64 : VOP3_Pseudo <opName, P, getVOP1Pat64<node, P>.ret>;
96 def _sdwa : VOP1_SDWA_Pseudo <opName, P>;
99 //===----------------------------------------------------------------------===//
101 //===----------------------------------------------------------------------===//
103 let VOPAsmPrefer32Bit = 1 in {
104 defm V_NOP : VOP1Inst <"v_nop", VOP_NONE>;
107 let isMoveImm = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
108 defm V_MOV_B32 : VOP1Inst <"v_mov_b32", VOP_I32_I32>;
109 } // End isMoveImm = 1
111 // FIXME: Specify SchedRW for READFIRSTLANE_B32
112 // TODO: Make profile for this, there is VOP3 encoding also
113 def V_READFIRSTLANE_B32 :
114 InstSI <(outs SReg_32:$vdst),
116 "v_readfirstlane_b32 $vdst, $src0",
117 [(set i32:$vdst, (int_amdgcn_readfirstlane i32:$src0))]>,
120 let isCodeGenOnly = 0;
121 let UseNamedOperandTable = 1;
126 let hasSideEffects = 0;
127 let SubtargetPredicate = isGCN;
132 let isConvergent = 1;
137 let Inst{8-0} = src0;
138 let Inst{16-9} = 0x2;
139 let Inst{24-17} = vdst;
140 let Inst{31-25} = 0x3f; //encoding
143 let SchedRW = [WriteQuarterRate32] in {
144 defm V_CVT_I32_F64 : VOP1Inst <"v_cvt_i32_f64", VOP_I32_F64, fp_to_sint>;
145 defm V_CVT_F64_I32 : VOP1Inst <"v_cvt_f64_i32", VOP_F64_I32, sint_to_fp>;
146 defm V_CVT_F32_I32 : VOP1Inst <"v_cvt_f32_i32", VOP_F32_I32, sint_to_fp>;
147 defm V_CVT_F32_U32 : VOP1Inst <"v_cvt_f32_u32", VOP_F32_I32, uint_to_fp>;
148 defm V_CVT_U32_F32 : VOP1Inst <"v_cvt_u32_f32", VOP_I32_F32, fp_to_uint>;
149 defm V_CVT_I32_F32 : VOP1Inst <"v_cvt_i32_f32", VOP_I32_F32, fp_to_sint>;
150 defm V_CVT_F16_F32 : VOP1Inst <"v_cvt_f16_f32", VOP_I32_F32, fp_to_f16>;
151 defm V_CVT_F32_F16 : VOP1Inst <"v_cvt_f32_f16", VOP_F32_I32, f16_to_fp>;
152 defm V_CVT_RPI_I32_F32 : VOP1Inst <"v_cvt_rpi_i32_f32", VOP_I32_F32, cvt_rpi_i32_f32>;
153 defm V_CVT_FLR_I32_F32 : VOP1Inst <"v_cvt_flr_i32_f32", VOP_I32_F32, cvt_flr_i32_f32>;
154 defm V_CVT_OFF_F32_I4 : VOP1Inst <"v_cvt_off_f32_i4", VOP_F32_I32>;
155 defm V_CVT_F32_F64 : VOP1Inst <"v_cvt_f32_f64", VOP_F32_F64, fpround>;
156 defm V_CVT_F64_F32 : VOP1Inst <"v_cvt_f64_f32", VOP_F64_F32, fpextend>;
157 defm V_CVT_F32_UBYTE0 : VOP1Inst <"v_cvt_f32_ubyte0", VOP_F32_I32, AMDGPUcvt_f32_ubyte0>;
158 defm V_CVT_F32_UBYTE1 : VOP1Inst <"v_cvt_f32_ubyte1", VOP_F32_I32, AMDGPUcvt_f32_ubyte1>;
159 defm V_CVT_F32_UBYTE2 : VOP1Inst <"v_cvt_f32_ubyte2", VOP_F32_I32, AMDGPUcvt_f32_ubyte2>;
160 defm V_CVT_F32_UBYTE3 : VOP1Inst <"v_cvt_f32_ubyte3", VOP_F32_I32, AMDGPUcvt_f32_ubyte3>;
161 defm V_CVT_U32_F64 : VOP1Inst <"v_cvt_u32_f64", VOP_I32_F64, fp_to_uint>;
162 defm V_CVT_F64_U32 : VOP1Inst <"v_cvt_f64_u32", VOP_F64_I32, uint_to_fp>;
163 } // End SchedRW = [WriteQuarterRate32]
165 defm V_FRACT_F32 : VOP1Inst <"v_fract_f32", VOP_F32_F32, AMDGPUfract>;
166 defm V_TRUNC_F32 : VOP1Inst <"v_trunc_f32", VOP_F32_F32, ftrunc>;
167 defm V_CEIL_F32 : VOP1Inst <"v_ceil_f32", VOP_F32_F32, fceil>;
168 defm V_RNDNE_F32 : VOP1Inst <"v_rndne_f32", VOP_F32_F32, frint>;
169 defm V_FLOOR_F32 : VOP1Inst <"v_floor_f32", VOP_F32_F32, ffloor>;
170 defm V_EXP_F32 : VOP1Inst <"v_exp_f32", VOP_F32_F32, fexp2>;
172 let SchedRW = [WriteQuarterRate32] in {
173 defm V_LOG_F32 : VOP1Inst <"v_log_f32", VOP_F32_F32, flog2>;
174 defm V_RCP_F32 : VOP1Inst <"v_rcp_f32", VOP_F32_F32, AMDGPUrcp>;
175 defm V_RCP_IFLAG_F32 : VOP1Inst <"v_rcp_iflag_f32", VOP_F32_F32>;
176 defm V_RSQ_F32 : VOP1Inst <"v_rsq_f32", VOP_F32_F32, AMDGPUrsq>;
177 } // End SchedRW = [WriteQuarterRate32]
179 let SchedRW = [WriteDouble] in {
180 defm V_RCP_F64 : VOP1Inst <"v_rcp_f64", VOP_F64_F64, AMDGPUrcp>;
181 defm V_RSQ_F64 : VOP1Inst <"v_rsq_f64", VOP_F64_F64, AMDGPUrsq>;
182 } // End SchedRW = [WriteDouble];
184 defm V_SQRT_F32 : VOP1Inst <"v_sqrt_f32", VOP_F32_F32, fsqrt>;
186 let SchedRW = [WriteDouble] in {
187 defm V_SQRT_F64 : VOP1Inst <"v_sqrt_f64", VOP_F64_F64, fsqrt>;
188 } // End SchedRW = [WriteDouble]
190 let SchedRW = [WriteQuarterRate32] in {
191 defm V_SIN_F32 : VOP1Inst <"v_sin_f32", VOP_F32_F32, AMDGPUsin>;
192 defm V_COS_F32 : VOP1Inst <"v_cos_f32", VOP_F32_F32, AMDGPUcos>;
193 } // End SchedRW = [WriteQuarterRate32]
195 defm V_NOT_B32 : VOP1Inst <"v_not_b32", VOP_I32_I32>;
196 defm V_BFREV_B32 : VOP1Inst <"v_bfrev_b32", VOP_I32_I32>;
197 defm V_FFBH_U32 : VOP1Inst <"v_ffbh_u32", VOP_I32_I32>;
198 defm V_FFBL_B32 : VOP1Inst <"v_ffbl_b32", VOP_I32_I32>;
199 defm V_FFBH_I32 : VOP1Inst <"v_ffbh_i32", VOP_I32_I32>;
200 defm V_FREXP_EXP_I32_F64 : VOP1Inst <"v_frexp_exp_i32_f64", VOP_I32_F64, int_amdgcn_frexp_exp>;
202 let SchedRW = [WriteDoubleAdd] in {
203 defm V_FREXP_MANT_F64 : VOP1Inst <"v_frexp_mant_f64", VOP_F64_F64, int_amdgcn_frexp_mant>;
204 defm V_FRACT_F64 : VOP1Inst <"v_fract_f64", VOP_F64_F64, AMDGPUfract>;
205 } // End SchedRW = [WriteDoubleAdd]
207 defm V_FREXP_EXP_I32_F32 : VOP1Inst <"v_frexp_exp_i32_f32", VOP_I32_F32, int_amdgcn_frexp_exp>;
208 defm V_FREXP_MANT_F32 : VOP1Inst <"v_frexp_mant_f32", VOP_F32_F32, int_amdgcn_frexp_mant>;
210 let VOPAsmPrefer32Bit = 1 in {
211 defm V_CLREXCP : VOP1Inst <"v_clrexcp", VOP_NO_EXT<VOP_NONE>>;
214 // Restrict src0 to be VGPR
215 def VOP_I32_VI32_NO_EXT : VOPProfile<[i32, i32, untyped, untyped]> {
216 let Src0RC32 = VRegSrc_32;
217 let Src0RC64 = VRegSrc_32;
222 // Special case because there are no true output operands. Hack vdst
223 // to be a src operand. The custom inserter must add a tied implicit
224 // def and use of the super register since there seems to be no way to
225 // add an implicit def of a virtual register in tablegen.
226 def VOP_MOVRELD : VOPProfile<[untyped, i32, untyped, untyped]> {
227 let Src0RC32 = VOPDstOperand<VGPR_32>;
228 let Src0RC64 = VOPDstOperand<VGPR_32>;
231 let Ins32 = (ins Src0RC32:$vdst, VSrc_b32:$src0);
232 let Ins64 = (ins Src0RC64:$vdst, VSrc_b32:$src0);
233 let InsDPP = (ins Src0RC32:$vdst, Src0RC32:$src0, dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
234 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
235 let InsSDWA = (ins Src0RC32:$vdst, Src0ModSDWA:$src0_modifiers, VCSrc_b32:$src0,
236 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
239 let Asm32 = getAsm32<1, 1>.ret;
240 let Asm64 = getAsm64<1, 1, 0>.ret;
241 let AsmDPP = getAsmDPP<1, 1, 0>.ret;
242 let AsmSDWA = getAsmSDWA<1, 1, 0>.ret;
246 let EmitDst = 1; // force vdst emission
249 let SubtargetPredicate = HasMovrel, Uses = [M0, EXEC] in {
250 // v_movreld_b32 is a special case because the destination output
251 // register is really a source. It isn't actually read (but may be
252 // written), and is only to provide the base register to start
253 // indexing from. Tablegen seems to not let you define an implicit
254 // virtual register output for the super register being written into,
255 // so this must have an implicit def of the register added to it.
256 defm V_MOVRELD_B32 : VOP1Inst <"v_movreld_b32", VOP_MOVRELD>;
257 defm V_MOVRELS_B32 : VOP1Inst <"v_movrels_b32", VOP_I32_VI32_NO_EXT>;
258 defm V_MOVRELSD_B32 : VOP1Inst <"v_movrelsd_b32", VOP_NO_EXT<VOP_I32_I32>>;
259 } // End Uses = [M0, EXEC]
261 // These instruction only exist on SI and CI
262 let SubtargetPredicate = isSICI in {
264 let SchedRW = [WriteQuarterRate32] in {
265 defm V_MOV_FED_B32 : VOP1Inst <"v_mov_fed_b32", VOP_I32_I32>;
266 defm V_LOG_CLAMP_F32 : VOP1Inst <"v_log_clamp_f32", VOP_F32_F32, int_amdgcn_log_clamp>;
267 defm V_RCP_CLAMP_F32 : VOP1Inst <"v_rcp_clamp_f32", VOP_F32_F32>;
268 defm V_RCP_LEGACY_F32 : VOP1Inst <"v_rcp_legacy_f32", VOP_F32_F32, AMDGPUrcp_legacy>;
269 defm V_RSQ_CLAMP_F32 : VOP1Inst <"v_rsq_clamp_f32", VOP_F32_F32, AMDGPUrsq_clamp>;
270 defm V_RSQ_LEGACY_F32 : VOP1Inst <"v_rsq_legacy_f32", VOP_F32_F32, AMDGPUrsq_legacy>;
271 } // End SchedRW = [WriteQuarterRate32]
273 let SchedRW = [WriteDouble] in {
274 defm V_RCP_CLAMP_F64 : VOP1Inst <"v_rcp_clamp_f64", VOP_F64_F64>;
275 defm V_RSQ_CLAMP_F64 : VOP1Inst <"v_rsq_clamp_f64", VOP_F64_F64, AMDGPUrsq_clamp>;
276 } // End SchedRW = [WriteDouble]
278 } // End SubtargetPredicate = isSICI
281 let SubtargetPredicate = isCIVI in {
283 let SchedRW = [WriteDoubleAdd] in {
284 defm V_TRUNC_F64 : VOP1Inst <"v_trunc_f64", VOP_F64_F64, ftrunc>;
285 defm V_CEIL_F64 : VOP1Inst <"v_ceil_f64", VOP_F64_F64, fceil>;
286 defm V_FLOOR_F64 : VOP1Inst <"v_floor_f64", VOP_F64_F64, ffloor>;
287 defm V_RNDNE_F64 : VOP1Inst <"v_rndne_f64", VOP_F64_F64, frint>;
288 } // End SchedRW = [WriteDoubleAdd]
290 let SchedRW = [WriteQuarterRate32] in {
291 defm V_LOG_LEGACY_F32 : VOP1Inst <"v_log_legacy_f32", VOP_F32_F32>;
292 defm V_EXP_LEGACY_F32 : VOP1Inst <"v_exp_legacy_f32", VOP_F32_F32>;
293 } // End SchedRW = [WriteQuarterRate32]
295 } // End SubtargetPredicate = isCIVI
298 let SubtargetPredicate = isVI in {
300 defm V_CVT_F16_U16 : VOP1Inst <"v_cvt_f16_u16", VOP_F16_I16, uint_to_fp>;
301 defm V_CVT_F16_I16 : VOP1Inst <"v_cvt_f16_i16", VOP_F16_I16, sint_to_fp>;
302 defm V_CVT_U16_F16 : VOP1Inst <"v_cvt_u16_f16", VOP_I16_F16, fp_to_uint>;
303 defm V_CVT_I16_F16 : VOP1Inst <"v_cvt_i16_f16", VOP_I16_F16, fp_to_sint>;
304 defm V_RCP_F16 : VOP1Inst <"v_rcp_f16", VOP_F16_F16, AMDGPUrcp>;
305 defm V_SQRT_F16 : VOP1Inst <"v_sqrt_f16", VOP_F16_F16, fsqrt>;
306 defm V_RSQ_F16 : VOP1Inst <"v_rsq_f16", VOP_F16_F16, AMDGPUrsq>;
307 defm V_LOG_F16 : VOP1Inst <"v_log_f16", VOP_F16_F16, flog2>;
308 defm V_EXP_F16 : VOP1Inst <"v_exp_f16", VOP_F16_F16, fexp2>;
309 defm V_FREXP_MANT_F16 : VOP1Inst <"v_frexp_mant_f16", VOP_F16_F16, int_amdgcn_frexp_mant>;
310 defm V_FREXP_EXP_I16_F16 : VOP1Inst <"v_frexp_exp_i16_f16", VOP_I16_F16, int_amdgcn_frexp_exp>;
311 defm V_FLOOR_F16 : VOP1Inst <"v_floor_f16", VOP_F16_F16, ffloor>;
312 defm V_CEIL_F16 : VOP1Inst <"v_ceil_f16", VOP_F16_F16, fceil>;
313 defm V_TRUNC_F16 : VOP1Inst <"v_trunc_f16", VOP_F16_F16, ftrunc>;
314 defm V_RNDNE_F16 : VOP1Inst <"v_rndne_f16", VOP_F16_F16, frint>;
315 defm V_FRACT_F16 : VOP1Inst <"v_fract_f16", VOP_F16_F16, AMDGPUfract>;
316 defm V_SIN_F16 : VOP1Inst <"v_sin_f16", VOP_F16_F16, AMDGPUsin>;
317 defm V_COS_F16 : VOP1Inst <"v_cos_f16", VOP_F16_F16, AMDGPUcos>;
321 let Predicates = [isVI] in {
324 (f32 (f16_to_fp i16:$src)),
325 (V_CVT_F32_F16_e32 $src)
329 (i16 (fp_to_f16 f32:$src)),
330 (V_CVT_F16_F32_e32 $src)
335 //===----------------------------------------------------------------------===//
337 //===----------------------------------------------------------------------===//
339 //===----------------------------------------------------------------------===//
341 //===----------------------------------------------------------------------===//
343 multiclass VOP1_Real_si <bits<9> op> {
344 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
346 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
347 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
349 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
350 VOP3e_si <{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
354 defm V_NOP : VOP1_Real_si <0x0>;
355 defm V_MOV_B32 : VOP1_Real_si <0x1>;
356 defm V_CVT_I32_F64 : VOP1_Real_si <0x3>;
357 defm V_CVT_F64_I32 : VOP1_Real_si <0x4>;
358 defm V_CVT_F32_I32 : VOP1_Real_si <0x5>;
359 defm V_CVT_F32_U32 : VOP1_Real_si <0x6>;
360 defm V_CVT_U32_F32 : VOP1_Real_si <0x7>;
361 defm V_CVT_I32_F32 : VOP1_Real_si <0x8>;
362 defm V_MOV_FED_B32 : VOP1_Real_si <0x9>;
363 defm V_CVT_F16_F32 : VOP1_Real_si <0xa>;
364 defm V_CVT_F32_F16 : VOP1_Real_si <0xb>;
365 defm V_CVT_RPI_I32_F32 : VOP1_Real_si <0xc>;
366 defm V_CVT_FLR_I32_F32 : VOP1_Real_si <0xd>;
367 defm V_CVT_OFF_F32_I4 : VOP1_Real_si <0xe>;
368 defm V_CVT_F32_F64 : VOP1_Real_si <0xf>;
369 defm V_CVT_F64_F32 : VOP1_Real_si <0x10>;
370 defm V_CVT_F32_UBYTE0 : VOP1_Real_si <0x11>;
371 defm V_CVT_F32_UBYTE1 : VOP1_Real_si <0x12>;
372 defm V_CVT_F32_UBYTE2 : VOP1_Real_si <0x13>;
373 defm V_CVT_F32_UBYTE3 : VOP1_Real_si <0x14>;
374 defm V_CVT_U32_F64 : VOP1_Real_si <0x15>;
375 defm V_CVT_F64_U32 : VOP1_Real_si <0x16>;
376 defm V_FRACT_F32 : VOP1_Real_si <0x20>;
377 defm V_TRUNC_F32 : VOP1_Real_si <0x21>;
378 defm V_CEIL_F32 : VOP1_Real_si <0x22>;
379 defm V_RNDNE_F32 : VOP1_Real_si <0x23>;
380 defm V_FLOOR_F32 : VOP1_Real_si <0x24>;
381 defm V_EXP_F32 : VOP1_Real_si <0x25>;
382 defm V_LOG_CLAMP_F32 : VOP1_Real_si <0x26>;
383 defm V_LOG_F32 : VOP1_Real_si <0x27>;
384 defm V_RCP_CLAMP_F32 : VOP1_Real_si <0x28>;
385 defm V_RCP_LEGACY_F32 : VOP1_Real_si <0x29>;
386 defm V_RCP_F32 : VOP1_Real_si <0x2a>;
387 defm V_RCP_IFLAG_F32 : VOP1_Real_si <0x2b>;
388 defm V_RSQ_CLAMP_F32 : VOP1_Real_si <0x2c>;
389 defm V_RSQ_LEGACY_F32 : VOP1_Real_si <0x2d>;
390 defm V_RSQ_F32 : VOP1_Real_si <0x2e>;
391 defm V_RCP_F64 : VOP1_Real_si <0x2f>;
392 defm V_RCP_CLAMP_F64 : VOP1_Real_si <0x30>;
393 defm V_RSQ_F64 : VOP1_Real_si <0x31>;
394 defm V_RSQ_CLAMP_F64 : VOP1_Real_si <0x32>;
395 defm V_SQRT_F32 : VOP1_Real_si <0x33>;
396 defm V_SQRT_F64 : VOP1_Real_si <0x34>;
397 defm V_SIN_F32 : VOP1_Real_si <0x35>;
398 defm V_COS_F32 : VOP1_Real_si <0x36>;
399 defm V_NOT_B32 : VOP1_Real_si <0x37>;
400 defm V_BFREV_B32 : VOP1_Real_si <0x38>;
401 defm V_FFBH_U32 : VOP1_Real_si <0x39>;
402 defm V_FFBL_B32 : VOP1_Real_si <0x3a>;
403 defm V_FFBH_I32 : VOP1_Real_si <0x3b>;
404 defm V_FREXP_EXP_I32_F64 : VOP1_Real_si <0x3c>;
405 defm V_FREXP_MANT_F64 : VOP1_Real_si <0x3d>;
406 defm V_FRACT_F64 : VOP1_Real_si <0x3e>;
407 defm V_FREXP_EXP_I32_F32 : VOP1_Real_si <0x3f>;
408 defm V_FREXP_MANT_F32 : VOP1_Real_si <0x40>;
409 defm V_CLREXCP : VOP1_Real_si <0x41>;
410 defm V_MOVRELD_B32 : VOP1_Real_si <0x42>;
411 defm V_MOVRELS_B32 : VOP1_Real_si <0x43>;
412 defm V_MOVRELSD_B32 : VOP1_Real_si <0x44>;
414 //===----------------------------------------------------------------------===//
416 //===----------------------------------------------------------------------===//
418 multiclass VOP1_Real_ci <bits<9> op> {
419 let AssemblerPredicates = [isCIOnly], DecoderNamespace = "CI" in {
421 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
422 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
424 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
425 VOP3e_si <{1, 1, op{6-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
429 defm V_TRUNC_F64 : VOP1_Real_ci <0x17>;
430 defm V_CEIL_F64 : VOP1_Real_ci <0x18>;
431 defm V_FLOOR_F64 : VOP1_Real_ci <0x1A>;
432 defm V_RNDNE_F64 : VOP1_Real_ci <0x19>;
433 defm V_LOG_LEGACY_F32 : VOP1_Real_ci <0x45>;
434 defm V_EXP_LEGACY_F32 : VOP1_Real_ci <0x46>;
436 //===----------------------------------------------------------------------===//
438 //===----------------------------------------------------------------------===//
440 class VOP1_DPP <bits<8> op, VOP1_Pseudo ps, VOPProfile P = ps.Pfl> :
441 VOP_DPP <ps.OpName, P> {
444 let SchedRW = ps.SchedRW;
445 let hasSideEffects = ps.hasSideEffects;
446 let Constraints = ps.Constraints;
447 let DisableEncoding = ps.DisableEncoding;
450 let Inst{8-0} = 0xfa; // dpp
452 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
453 let Inst{31-25} = 0x3f; //encoding
456 multiclass VOP1_Real_vi <bits<10> op> {
457 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
459 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
460 VOP1e<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32").Pfl>;
462 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
463 VOP3e_vi <!add(0x140, op), !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
467 VOP_SDWA_Real <!cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa")>,
468 VOP1_SDWAe <op{7-0}, !cast<VOP1_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
470 // For now left dpp only for asm/dasm
471 // TODO: add corresponding pseudo
472 def _dpp : VOP1_DPP<op{7-0}, !cast<VOP1_Pseudo>(NAME#"_e32")>;
475 defm V_NOP : VOP1_Real_vi <0x0>;
476 defm V_MOV_B32 : VOP1_Real_vi <0x1>;
477 defm V_CVT_I32_F64 : VOP1_Real_vi <0x3>;
478 defm V_CVT_F64_I32 : VOP1_Real_vi <0x4>;
479 defm V_CVT_F32_I32 : VOP1_Real_vi <0x5>;
480 defm V_CVT_F32_U32 : VOP1_Real_vi <0x6>;
481 defm V_CVT_U32_F32 : VOP1_Real_vi <0x7>;
482 defm V_CVT_I32_F32 : VOP1_Real_vi <0x8>;
483 defm V_CVT_F16_F32 : VOP1_Real_vi <0xa>;
484 defm V_CVT_F32_F16 : VOP1_Real_vi <0xb>;
485 defm V_CVT_RPI_I32_F32 : VOP1_Real_vi <0xc>;
486 defm V_CVT_FLR_I32_F32 : VOP1_Real_vi <0xd>;
487 defm V_CVT_OFF_F32_I4 : VOP1_Real_vi <0xe>;
488 defm V_CVT_F32_F64 : VOP1_Real_vi <0xf>;
489 defm V_CVT_F64_F32 : VOP1_Real_vi <0x10>;
490 defm V_CVT_F32_UBYTE0 : VOP1_Real_vi <0x11>;
491 defm V_CVT_F32_UBYTE1 : VOP1_Real_vi <0x12>;
492 defm V_CVT_F32_UBYTE2 : VOP1_Real_vi <0x13>;
493 defm V_CVT_F32_UBYTE3 : VOP1_Real_vi <0x14>;
494 defm V_CVT_U32_F64 : VOP1_Real_vi <0x15>;
495 defm V_CVT_F64_U32 : VOP1_Real_vi <0x16>;
496 defm V_FRACT_F32 : VOP1_Real_vi <0x1b>;
497 defm V_TRUNC_F32 : VOP1_Real_vi <0x1c>;
498 defm V_CEIL_F32 : VOP1_Real_vi <0x1d>;
499 defm V_RNDNE_F32 : VOP1_Real_vi <0x1e>;
500 defm V_FLOOR_F32 : VOP1_Real_vi <0x1f>;
501 defm V_EXP_F32 : VOP1_Real_vi <0x20>;
502 defm V_LOG_F32 : VOP1_Real_vi <0x21>;
503 defm V_RCP_F32 : VOP1_Real_vi <0x22>;
504 defm V_RCP_IFLAG_F32 : VOP1_Real_vi <0x23>;
505 defm V_RSQ_F32 : VOP1_Real_vi <0x24>;
506 defm V_RCP_F64 : VOP1_Real_vi <0x25>;
507 defm V_RSQ_F64 : VOP1_Real_vi <0x26>;
508 defm V_SQRT_F32 : VOP1_Real_vi <0x27>;
509 defm V_SQRT_F64 : VOP1_Real_vi <0x28>;
510 defm V_SIN_F32 : VOP1_Real_vi <0x29>;
511 defm V_COS_F32 : VOP1_Real_vi <0x2a>;
512 defm V_NOT_B32 : VOP1_Real_vi <0x2b>;
513 defm V_BFREV_B32 : VOP1_Real_vi <0x2c>;
514 defm V_FFBH_U32 : VOP1_Real_vi <0x2d>;
515 defm V_FFBL_B32 : VOP1_Real_vi <0x2e>;
516 defm V_FFBH_I32 : VOP1_Real_vi <0x2f>;
517 defm V_FREXP_EXP_I32_F64 : VOP1_Real_vi <0x30>;
518 defm V_FREXP_MANT_F64 : VOP1_Real_vi <0x31>;
519 defm V_FRACT_F64 : VOP1_Real_vi <0x32>;
520 defm V_FREXP_EXP_I32_F32 : VOP1_Real_vi <0x33>;
521 defm V_FREXP_MANT_F32 : VOP1_Real_vi <0x34>;
522 defm V_CLREXCP : VOP1_Real_vi <0x35>;
523 defm V_MOVRELD_B32 : VOP1_Real_vi <0x36>;
524 defm V_MOVRELS_B32 : VOP1_Real_vi <0x37>;
525 defm V_MOVRELSD_B32 : VOP1_Real_vi <0x38>;
526 defm V_TRUNC_F64 : VOP1_Real_vi <0x17>;
527 defm V_CEIL_F64 : VOP1_Real_vi <0x18>;
528 defm V_FLOOR_F64 : VOP1_Real_vi <0x1A>;
529 defm V_RNDNE_F64 : VOP1_Real_vi <0x19>;
530 defm V_LOG_LEGACY_F32 : VOP1_Real_vi <0x4c>;
531 defm V_EXP_LEGACY_F32 : VOP1_Real_vi <0x4b>;
532 defm V_CVT_F16_U16 : VOP1_Real_vi <0x39>;
533 defm V_CVT_F16_I16 : VOP1_Real_vi <0x3a>;
534 defm V_CVT_U16_F16 : VOP1_Real_vi <0x3b>;
535 defm V_CVT_I16_F16 : VOP1_Real_vi <0x3c>;
536 defm V_RCP_F16 : VOP1_Real_vi <0x3d>;
537 defm V_SQRT_F16 : VOP1_Real_vi <0x3e>;
538 defm V_RSQ_F16 : VOP1_Real_vi <0x3f>;
539 defm V_LOG_F16 : VOP1_Real_vi <0x40>;
540 defm V_EXP_F16 : VOP1_Real_vi <0x41>;
541 defm V_FREXP_MANT_F16 : VOP1_Real_vi <0x42>;
542 defm V_FREXP_EXP_I16_F16 : VOP1_Real_vi <0x43>;
543 defm V_FLOOR_F16 : VOP1_Real_vi <0x44>;
544 defm V_CEIL_F16 : VOP1_Real_vi <0x45>;
545 defm V_TRUNC_F16 : VOP1_Real_vi <0x46>;
546 defm V_RNDNE_F16 : VOP1_Real_vi <0x47>;
547 defm V_FRACT_F16 : VOP1_Real_vi <0x48>;
548 defm V_SIN_F16 : VOP1_Real_vi <0x49>;
549 defm V_COS_F16 : VOP1_Real_vi <0x4a>;
552 // Copy of v_mov_b32 with $vdst as a use operand for use with VGPR
553 // indexing mode. vdst can't be treated as a def for codegen purposes,
554 // and an implicit use and def of the super register should be added.
555 def V_MOV_B32_indirect : VPseudoInstSI<(outs),
556 (ins getVALUDstForVT<i32>.ret:$vdst, getVOPSrc0ForVT<i32>.ret:$src0)>,
557 PseudoInstExpansion<(V_MOV_B32_e32_vi getVALUDstForVT<i32>.ret:$vdst,
558 getVOPSrc0ForVT<i32>.ret:$src0)> {
560 let SubtargetPredicate = isVI;
563 // This is a pseudo variant of the v_movreld_b32 instruction in which the
564 // vector operand appears only twice, once as def and once as use. Using this
565 // pseudo avoids problems with the Two Address instructions pass.
566 class V_MOVRELD_B32_pseudo<RegisterClass rc> : VPseudoInstSI <
568 (ins rc:$vsrc, VSrc_b32:$val, i32imm:$offset)> {
571 let Constraints = "$vsrc = $vdst";
572 let Uses = [M0, EXEC];
574 let SubtargetPredicate = HasMovrel;
577 def V_MOVRELD_B32_V1 : V_MOVRELD_B32_pseudo<VGPR_32>;
578 def V_MOVRELD_B32_V2 : V_MOVRELD_B32_pseudo<VReg_64>;
579 def V_MOVRELD_B32_V4 : V_MOVRELD_B32_pseudo<VReg_128>;
580 def V_MOVRELD_B32_V8 : V_MOVRELD_B32_pseudo<VReg_256>;
581 def V_MOVRELD_B32_V16 : V_MOVRELD_B32_pseudo<VReg_512>;
583 let Predicates = [isVI] in {
586 (i32 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
588 (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask),
589 (as_i32imm $bank_mask), (as_i1imm $bound_ctrl))
594 (i32 (anyext i16:$src)),
599 (i64 (anyext i16:$src)),
600 (REG_SEQUENCE VReg_64,
601 (i32 (COPY $src)), sub0,
602 (V_MOV_B32_e32 (i32 0)), sub1)
606 (i16 (trunc i32:$src)),
611 (i16 (trunc i64:$src)),
612 (EXTRACT_SUBREG $src, sub0)
615 } // End Predicates = [isVI]