1 //===-- VOP2Instructions.td - Vector Instruction Defintions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
19 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
20 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
21 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
23 let Inst{31} = 0x0; //encoding
26 class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
32 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
33 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
34 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
36 let Inst{31} = 0x0; // encoding
37 let Inst{63-32} = imm;
40 class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
44 let Inst{8-0} = 0xf9; // sdwa
45 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
46 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
48 let Inst{31} = 0x0; // encoding
51 class VOP2_SDWA9Ae <bits<6> op, VOPProfile P> : VOP_SDWA9Ae <P> {
55 let Inst{8-0} = 0xf9; // sdwa
56 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
57 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
59 let Inst{31} = 0x0; // encoding
60 let Inst{63} = !if(P.HasSrc1, src1{8}, 0); // src1_sgpr
63 class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
64 InstSI <P.Outs32, P.Ins32, "", pattern>,
66 SIMCInstr <opName#suffix, SIEncodingFamily.NONE>,
67 MnemonicAlias<opName#suffix, opName> {
70 let isCodeGenOnly = 1;
71 let UseNamedOperandTable = 1;
73 string Mnemonic = opName;
74 string AsmOperands = P.Asm32;
79 let hasSideEffects = 0;
80 let SubtargetPredicate = isGCN;
86 let AsmVariantName = AMDGPUAsmVariants.Default;
91 class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
92 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
93 SIMCInstr <ps.PseudoInstr, EncodingFamily> {
96 let isCodeGenOnly = 0;
98 let Constraints = ps.Constraints;
99 let DisableEncoding = ps.DisableEncoding;
101 // copy relevant pseudo op flags
102 let SubtargetPredicate = ps.SubtargetPredicate;
103 let AsmMatchConverter = ps.AsmMatchConverter;
104 let AsmVariantName = ps.AsmVariantName;
105 let Constraints = ps.Constraints;
106 let DisableEncoding = ps.DisableEncoding;
107 let TSFlags = ps.TSFlags;
108 let UseNamedOperandTable = ps.UseNamedOperandTable;
112 class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
113 VOP_SDWA_Pseudo <OpName, P, pattern> {
114 let AsmMatchConverter = "cvtSdwaVOP2";
117 class VOP2_SDWA9_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
118 VOP_SDWA9_Pseudo <OpName, P, pattern> {
119 let AsmMatchConverter = "cvtSdwaVOP2";
122 class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
123 list<dag> ret = !if(P.HasModifiers,
125 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
126 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
127 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
130 multiclass VOP2Inst <string opName,
132 SDPatternOperator node = null_frag,
133 string revOp = opName> {
135 def _e32 : VOP2_Pseudo <opName, P>,
136 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
138 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
139 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
141 def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
142 def _sdwa9 : VOP2_SDWA9_Pseudo <opName, P>;
145 multiclass VOP2bInst <string opName,
147 SDPatternOperator node = null_frag,
148 string revOp = opName,
149 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
151 let SchedRW = [Write32Bit, WriteSALU] in {
152 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
153 def _e32 : VOP2_Pseudo <opName, P>,
154 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
156 def _sdwa : VOP2_SDWA_Pseudo <opName, P> {
157 let AsmMatchConverter = "cvtSdwaVOP2b";
160 def _sdwa9 : VOP2_SDWA9_Pseudo <opName, P> {
161 let AsmMatchConverter = "cvtSdwaVOP2b";
165 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
166 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
170 multiclass VOP2eInst <string opName,
172 SDPatternOperator node = null_frag,
173 string revOp = opName,
174 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
176 let SchedRW = [Write32Bit] in {
177 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
178 def _e32 : VOP2_Pseudo <opName, P>,
179 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
182 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
183 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
187 class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
188 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
189 field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm);
190 field bit HasExt = 0;
192 // Hack to stop printing _e64
193 let DstRC = RegisterOperand<VGPR_32>;
194 field string Asm32 = " $vdst, $src0, $src1, $imm";
197 def VOP_MADAK_F16 : VOP_MADAK <f16>;
198 def VOP_MADAK_F32 : VOP_MADAK <f32>;
200 class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
201 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
202 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
203 field bit HasExt = 0;
205 // Hack to stop printing _e64
206 let DstRC = RegisterOperand<VGPR_32>;
207 field string Asm32 = " $vdst, $src0, $imm, $src1";
210 def VOP_MADMK_F16 : VOP_MADMK <f16>;
211 def VOP_MADMK_F32 : VOP_MADMK <f32>;
213 // FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
214 // and processing time but it makes it easier to convert to mad.
215 class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
216 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
217 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
218 HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
219 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
220 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
221 VGPR_32:$src2, // stub argument
222 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
223 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
224 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
225 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
226 VGPR_32:$src2, // stub argument
227 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
228 src0_sel:$src0_sel, src1_sel:$src1_sel);
229 let InsSDWA9 = (ins Src0ModSDWA9:$src0_modifiers, Src0SDWA9:$src0,
230 Src1ModSDWA9:$src1_modifiers, Src1SDWA9:$src1,
231 VGPR_32:$src2, // stub argument
232 clampmod:$clamp, omod:$omod,
233 dst_sel:$dst_sel, dst_unused:$dst_unused,
234 src0_sel:$src0_sel, src1_sel:$src1_sel);
235 let Asm32 = getAsm32<1, 2, vt>.ret;
236 let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, vt>.ret;
237 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret;
238 let AsmSDWA = getAsmSDWA<1, 2, vt>.ret;
239 let AsmSDWA9 = getAsmSDWA9<1, 1, 2, vt>.ret;
246 def VOP_MAC_F16 : VOP_MAC <f16> {
247 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
248 // 'not a string initializer' error.
249 let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, f16>.ret;
252 def VOP_MAC_F32 : VOP_MAC <f32> {
253 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
254 // 'not a string initializer' error.
255 let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, f32>.ret;
258 // Write out to vcc or arbitrary SGPR.
259 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
260 let Asm32 = "$vdst, vcc, $src0, $src1";
261 let Asm64 = "$vdst, $sdst, $src0, $src1";
262 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
263 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
264 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
265 let Outs32 = (outs DstRC:$vdst);
266 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
269 // Write out to vcc or arbitrary SGPR and read in from vcc or
271 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
272 // We use VCSrc_b32 to exclude literal constants, even though the
273 // encoding normally allows them since the implicit VCC use means
274 // using one would always violate the constant bus
275 // restriction. SGPRs are still allowed because it should
276 // technically be possible to use VCC again as src0.
277 let Src0RC32 = VCSrc_b32;
278 let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
279 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
280 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
281 let AsmSDWA9 = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
282 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
283 let Outs32 = (outs DstRC:$vdst);
284 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
286 // Suppress src2 implied by type since the 32-bit encoding uses an
288 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
290 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
291 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
292 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
293 src0_sel:$src0_sel, src1_sel:$src1_sel);
295 let InsSDWA9 = (ins Src0ModSDWA9:$src0_modifiers, Src0SDWA9:$src0,
296 Src1ModSDWA9:$src1_modifiers, Src1SDWA9:$src1,
297 clampmod:$clamp, omod:$omod,
298 dst_sel:$dst_sel, dst_unused:$dst_unused,
299 src0_sel:$src0_sel, src1_sel:$src1_sel);
301 let InsDPP = (ins Src0Mod:$src0_modifiers, Src0DPP:$src0,
302 Src1Mod:$src1_modifiers, Src1DPP:$src1,
303 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
304 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
309 // Read in from vcc or arbitrary SGPR
310 def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
311 let Src0RC32 = VCSrc_b32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above.
312 let Asm32 = "$vdst, $src0, $src1, vcc";
313 let Asm64 = "$vdst, $src0, $src1, $src2";
314 let Outs32 = (outs DstRC:$vdst);
315 let Outs64 = (outs DstRC:$vdst);
317 // Suppress src2 implied by type since the 32-bit encoding uses an
319 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
322 def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
323 let Outs32 = (outs SReg_32:$vdst);
325 let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1);
327 let Asm32 = " $vdst, $src0, $src1";
331 def VOP_WRITELANE : VOPProfile<[i32, i32, i32]> {
332 let Outs32 = (outs VGPR_32:$vdst);
334 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1);
336 let Asm32 = " $vdst, $src0, $src1";
340 //===----------------------------------------------------------------------===//
342 //===----------------------------------------------------------------------===//
344 let SubtargetPredicate = isGCN in {
346 defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
347 def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32, [], "">;
349 let isCommutable = 1 in {
350 defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>;
351 defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>;
352 defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
353 defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
354 defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>;
355 defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24>;
356 defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>;
357 defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>;
358 defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>;
359 defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum>;
360 defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum>;
361 defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_I32_I32_I32>;
362 defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_I32_I32_I32>;
363 defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_I32_I32_I32>;
364 defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_I32_I32_I32>;
365 defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">;
366 defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">;
367 defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">;
368 defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_I32_I32_I32>;
369 defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_I32_I32_I32>;
370 defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_I32_I32_I32>;
372 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
373 isConvertibleToThreeAddress = 1 in {
374 defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
377 def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32, [], "">;
379 // No patterns so that the scalar instructions are always selected.
380 // The scalar versions will be replaced with vector when needed later.
382 // V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
383 // but the VI instructions behave the same as the SI versions.
384 defm V_ADD_I32 : VOP2bInst <"v_add_i32", VOP2b_I32_I1_I32_I32>;
385 defm V_SUB_I32 : VOP2bInst <"v_sub_i32", VOP2b_I32_I1_I32_I32>;
386 defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32">;
387 defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1>;
388 defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1>;
389 defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
390 } // End isCommutable = 1
392 // These are special and do not read the exec mask.
393 let isConvergent = 1, Uses = []<Register> in {
394 def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
395 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))], "">;
397 def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, [], "">;
398 } // End isConvergent = 1
400 defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>;
401 defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32>;
402 defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>;
403 defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>;
404 defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp>;
405 defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_I32_F32_I32>; // TODO: set "Uses = dst"
406 defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_I32_F32_F32>;
407 defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_I32_F32_F32>;
408 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_I32_F32_F32, AMDGPUpkrtz_f16_f32>;
409 defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_I32_I32_I32>;
410 defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_I32_I32_I32>;
412 } // End SubtargetPredicate = isGCN
415 // These instructions only exist on SI and CI
416 let SubtargetPredicate = isSICI in {
418 defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
419 defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
421 let isCommutable = 1 in {
422 defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>;
423 defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_I32_I32_I32>;
424 defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_I32_I32_I32>;
425 defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_I32_I32_I32>;
426 } // End isCommutable = 1
428 } // End let SubtargetPredicate = SICI
430 let SubtargetPredicate = Has16BitInsts in {
432 def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16, [], "">;
433 defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>;
434 defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>;
435 defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>;
436 defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
438 let isCommutable = 1 in {
439 defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>;
440 defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>;
441 defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
442 defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>;
443 def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16, [], "">;
444 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>;
445 defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>;
446 defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">;
447 defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>;
448 defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum>;
449 defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum>;
450 defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16>;
451 defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16>;
452 defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16>;
453 defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16>;
455 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
456 isConvertibleToThreeAddress = 1 in {
457 defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
459 } // End isCommutable = 1
461 } // End SubtargetPredicate = Has16BitInsts
463 // Note: 16-bit instructions produce a 0 result in the high 16-bits.
464 multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst> {
467 (op i16:$src0, i16:$src1),
472 (i32 (zext (op i16:$src0, i16:$src1))),
477 (i64 (zext (op i16:$src0, i16:$src1))),
478 (REG_SEQUENCE VReg_64,
479 (inst $src0, $src1), sub0,
480 (V_MOV_B32_e32 (i32 0)), sub1)
485 multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> {
488 (op i16:$src0, i16:$src1),
493 (i32 (zext (op i16:$src0, i16:$src1))),
499 (i64 (zext (op i16:$src0, i16:$src1))),
500 (REG_SEQUENCE VReg_64,
501 (inst $src1, $src0), sub0,
502 (V_MOV_B32_e32 (i32 0)), sub1)
506 class ZExt_i16_i1_Pat <SDNode ext> : Pat <
508 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)
511 let Predicates = [Has16BitInsts] in {
513 defm : Arithmetic_i16_Pats<add, V_ADD_U16_e64>;
514 defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e64>;
515 defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e64>;
516 defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e64>;
517 defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e64>;
518 defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64>;
519 defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64>;
522 (and i16:$src0, i16:$src1),
523 (V_AND_B32_e64 $src0, $src1)
527 (or i16:$src0, i16:$src1),
528 (V_OR_B32_e64 $src0, $src1)
532 (xor i16:$src0, i16:$src1),
533 (V_XOR_B32_e64 $src0, $src1)
536 defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>;
537 defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>;
538 defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e64>;
540 def : ZExt_i16_i1_Pat<zext>;
541 def : ZExt_i16_i1_Pat<anyext>;
544 (i16 (sext i1:$src)),
545 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)
548 // Undo sub x, c -> add x, -c canonicalization since c is more likely
549 // an inline immediate than -c.
550 // TODO: Also do for 64-bit.
552 (add i16:$src0, (i16 NegSubInlineConst16:$src1)),
553 (V_SUB_U16_e64 $src0, NegSubInlineConst16:$src1)
556 } // End Predicates = [Has16BitInsts]
558 //===----------------------------------------------------------------------===//
560 //===----------------------------------------------------------------------===//
562 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
564 multiclass VOP2_Real_si <bits<6> op> {
566 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
567 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
570 multiclass VOP2_Real_MADK_si <bits<6> op> {
571 def _si : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
572 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
575 multiclass VOP2_Real_e32_si <bits<6> op> {
577 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
578 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
581 multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
583 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
584 VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
587 multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
589 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
590 VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
593 } // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
595 defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>;
596 defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>;
597 defm V_SUB_F32 : VOP2_Real_e32e64_si <0x4>;
598 defm V_SUBREV_F32 : VOP2_Real_e32e64_si <0x5>;
599 defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_si <0x7>;
600 defm V_MUL_F32 : VOP2_Real_e32e64_si <0x8>;
601 defm V_MUL_I32_I24 : VOP2_Real_e32e64_si <0x9>;
602 defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_si <0xa>;
603 defm V_MUL_U32_U24 : VOP2_Real_e32e64_si <0xb>;
604 defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_si <0xc>;
605 defm V_MIN_F32 : VOP2_Real_e32e64_si <0xf>;
606 defm V_MAX_F32 : VOP2_Real_e32e64_si <0x10>;
607 defm V_MIN_I32 : VOP2_Real_e32e64_si <0x11>;
608 defm V_MAX_I32 : VOP2_Real_e32e64_si <0x12>;
609 defm V_MIN_U32 : VOP2_Real_e32e64_si <0x13>;
610 defm V_MAX_U32 : VOP2_Real_e32e64_si <0x14>;
611 defm V_LSHRREV_B32 : VOP2_Real_e32e64_si <0x16>;
612 defm V_ASHRREV_I32 : VOP2_Real_e32e64_si <0x18>;
613 defm V_LSHLREV_B32 : VOP2_Real_e32e64_si <0x1a>;
614 defm V_AND_B32 : VOP2_Real_e32e64_si <0x1b>;
615 defm V_OR_B32 : VOP2_Real_e32e64_si <0x1c>;
616 defm V_XOR_B32 : VOP2_Real_e32e64_si <0x1d>;
617 defm V_MAC_F32 : VOP2_Real_e32e64_si <0x1f>;
618 defm V_MADMK_F32 : VOP2_Real_MADK_si <0x20>;
619 defm V_MADAK_F32 : VOP2_Real_MADK_si <0x21>;
620 defm V_ADD_I32 : VOP2be_Real_e32e64_si <0x25>;
621 defm V_SUB_I32 : VOP2be_Real_e32e64_si <0x26>;
622 defm V_SUBREV_I32 : VOP2be_Real_e32e64_si <0x27>;
623 defm V_ADDC_U32 : VOP2be_Real_e32e64_si <0x28>;
624 defm V_SUBB_U32 : VOP2be_Real_e32e64_si <0x29>;
625 defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>;
627 defm V_READLANE_B32 : VOP2_Real_si <0x01>;
629 let InOperandList = (ins SSrc_b32:$src0, SCSrc_b32:$src1) in {
630 defm V_WRITELANE_B32 : VOP2_Real_si <0x02>;
633 defm V_MAC_LEGACY_F32 : VOP2_Real_e32e64_si <0x6>;
634 defm V_MIN_LEGACY_F32 : VOP2_Real_e32e64_si <0xd>;
635 defm V_MAX_LEGACY_F32 : VOP2_Real_e32e64_si <0xe>;
636 defm V_LSHR_B32 : VOP2_Real_e32e64_si <0x15>;
637 defm V_ASHR_I32 : VOP2_Real_e32e64_si <0x17>;
638 defm V_LSHL_B32 : VOP2_Real_e32e64_si <0x19>;
640 defm V_BFM_B32 : VOP2_Real_e32e64_si <0x1e>;
641 defm V_BCNT_U32_B32 : VOP2_Real_e32e64_si <0x22>;
642 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e32e64_si <0x23>;
643 defm V_MBCNT_HI_U32_B32 : VOP2_Real_e32e64_si <0x24>;
644 defm V_LDEXP_F32 : VOP2_Real_e32e64_si <0x2b>;
645 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e32e64_si <0x2c>;
646 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e32e64_si <0x2d>;
647 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e32e64_si <0x2e>;
648 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e32e64_si <0x2f>;
649 defm V_CVT_PK_U16_U32 : VOP2_Real_e32e64_si <0x30>;
650 defm V_CVT_PK_I16_I32 : VOP2_Real_e32e64_si <0x31>;
653 //===----------------------------------------------------------------------===//
655 //===----------------------------------------------------------------------===//
657 class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> :
658 VOP_DPP <ps.OpName, P> {
661 let SchedRW = ps.SchedRW;
662 let hasSideEffects = ps.hasSideEffects;
663 let Constraints = ps.Constraints;
664 let DisableEncoding = ps.DisableEncoding;
668 let Inst{8-0} = 0xfa; //dpp
669 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
670 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
671 let Inst{30-25} = op;
672 let Inst{31} = 0x0; //encoding
675 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
677 multiclass VOP32_Real_vi <bits<10> op> {
679 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
680 VOP3e_vi<op, !cast<VOP2_Pseudo>(NAME).Pfl>;
683 multiclass VOP2_Real_MADK_vi <bits<6> op> {
684 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
685 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
688 multiclass VOP2_Real_e32_vi <bits<6> op> {
690 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
691 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
694 multiclass VOP2_Real_e64_vi <bits<10> op> {
696 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
697 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
700 multiclass VOP2_Real_e64only_vi <bits<10> op> {
702 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
703 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl> {
704 // Hack to stop printing _e64
705 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME#"_e64");
706 let OutOperandList = (outs VGPR_32:$vdst);
707 let AsmString = ps.Mnemonic # " " # ps.AsmOperands;
711 multiclass Base_VOP2be_Real_e32e64_vi <bits<6> op> : VOP2_Real_e32_vi<op> {
713 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
714 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
717 multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
718 VOP2_Real_e32_vi<op>,
719 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
721 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
723 multiclass VOP2_SDWA_Real <bits<6> op> {
725 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
726 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
729 multiclass VOP2_SDWA9_Real <bits<6> op> {
731 VOP_SDWA9_Real <!cast<VOP2_SDWA9_Pseudo>(NAME#"_sdwa9")>,
732 VOP2_SDWA9Ae <op{5-0}, !cast<VOP2_SDWA9_Pseudo>(NAME#"_sdwa9").Pfl>;
735 multiclass VOP2be_Real_e32e64_vi <bits<6> op> :
736 Base_VOP2be_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
737 // For now left dpp only for asm/dasm
738 // TODO: add corresponding pseudo
739 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
742 multiclass VOP2_Real_e32e64_vi <bits<6> op> :
743 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op>, VOP2_SDWA9_Real<op> {
744 // For now left dpp only for asm/dasm
745 // TODO: add corresponding pseudo
746 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
749 defm V_CNDMASK_B32 : Base_VOP2_Real_e32e64_vi <0x0>;
750 defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>;
751 defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>;
752 defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>;
753 defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>;
754 defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>;
755 defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>;
756 defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>;
757 defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>;
758 defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>;
759 defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>;
760 defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>;
761 defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>;
762 defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>;
763 defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>;
764 defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>;
765 defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>;
766 defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>;
767 defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>;
768 defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>;
769 defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>;
770 defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>;
771 defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>;
772 defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>;
773 defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>;
774 defm V_ADD_I32 : VOP2be_Real_e32e64_vi <0x19>;
775 defm V_SUB_I32 : VOP2be_Real_e32e64_vi <0x1a>;
776 defm V_SUBREV_I32 : VOP2be_Real_e32e64_vi <0x1b>;
777 defm V_ADDC_U32 : VOP2be_Real_e32e64_vi <0x1c>;
778 defm V_SUBB_U32 : VOP2be_Real_e32e64_vi <0x1d>;
779 defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi <0x1e>;
781 defm V_READLANE_B32 : VOP32_Real_vi <0x289>;
782 defm V_WRITELANE_B32 : VOP32_Real_vi <0x28a>;
784 defm V_BFM_B32 : VOP2_Real_e64only_vi <0x293>;
785 defm V_BCNT_U32_B32 : VOP2_Real_e64only_vi <0x28b>;
786 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64only_vi <0x28c>;
787 defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64only_vi <0x28d>;
788 defm V_LDEXP_F32 : VOP2_Real_e64only_vi <0x288>;
789 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64only_vi <0x1f0>;
790 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64only_vi <0x294>;
791 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64only_vi <0x295>;
792 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64only_vi <0x296>;
793 defm V_CVT_PK_U16_U32 : VOP2_Real_e64only_vi <0x297>;
794 defm V_CVT_PK_I16_I32 : VOP2_Real_e64only_vi <0x298>;
796 defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>;
797 defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>;
798 defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>;
799 defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>;
800 defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>;
801 defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>;
802 defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>;
803 defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>;
804 defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>;
805 defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>;
806 defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;
807 defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;
808 defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;
809 defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>;
810 defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;
811 defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;
812 defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;
813 defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>;
814 defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;
815 defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;
816 defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;
818 let SubtargetPredicate = isVI in {
820 // Aliases to simplify matching of floating-point instructions that
821 // are VOP2 on SI and VOP3 on VI.
822 class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
823 name#" $dst, $src0, $src1",
824 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0)
825 >, PredicateControl {
826 let UseInstAsmMatchConverter = 0;
827 let AsmVariantName = AMDGPUAsmVariants.VOP3;
830 def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
831 def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
832 def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
833 def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
834 def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
836 } // End SubtargetPredicate = isVI