1 //===-- VOP2Instructions.td - Vector Instruction Defintions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
19 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
20 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
21 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
23 let Inst{31} = 0x0; //encoding
26 class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
32 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
33 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
34 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
36 let Inst{31} = 0x0; // encoding
37 let Inst{63-32} = imm;
40 class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
44 let Inst{8-0} = 0xf9; // sdwa
45 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
46 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
48 let Inst{31} = 0x0; // encoding
51 class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
52 InstSI <P.Outs32, P.Ins32, "", pattern>,
54 SIMCInstr <opName#suffix, SIEncodingFamily.NONE>,
55 MnemonicAlias<opName#suffix, opName> {
58 let isCodeGenOnly = 1;
59 let UseNamedOperandTable = 1;
61 string Mnemonic = opName;
62 string AsmOperands = P.Asm32;
67 let hasSideEffects = 0;
68 let SubtargetPredicate = isGCN;
74 let AsmVariantName = AMDGPUAsmVariants.Default;
79 class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
80 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
81 SIMCInstr <ps.PseudoInstr, EncodingFamily> {
84 let isCodeGenOnly = 0;
86 let Constraints = ps.Constraints;
87 let DisableEncoding = ps.DisableEncoding;
89 // copy relevant pseudo op flags
90 let SubtargetPredicate = ps.SubtargetPredicate;
91 let AsmMatchConverter = ps.AsmMatchConverter;
92 let AsmVariantName = ps.AsmVariantName;
93 let Constraints = ps.Constraints;
94 let DisableEncoding = ps.DisableEncoding;
95 let TSFlags = ps.TSFlags;
96 let UseNamedOperandTable = ps.UseNamedOperandTable;
100 class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
101 VOP_SDWA_Pseudo <OpName, P, pattern> {
102 let AsmMatchConverter = "cvtSdwaVOP2";
105 class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
106 list<dag> ret = !if(P.HasModifiers,
108 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
109 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
110 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
113 multiclass VOP2Inst <string opName,
115 SDPatternOperator node = null_frag,
116 string revOp = opName> {
118 def _e32 : VOP2_Pseudo <opName, P>,
119 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
121 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
122 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
124 def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
127 // TODO: add SDWA pseudo instructions for VOP2bInst and VOP2eInst
128 multiclass VOP2bInst <string opName,
130 SDPatternOperator node = null_frag,
131 string revOp = opName,
132 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
134 let SchedRW = [Write32Bit, WriteSALU] in {
135 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
136 def _e32 : VOP2_Pseudo <opName, P>,
137 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
139 def _sdwa : VOP2_SDWA_Pseudo <opName, P>;
142 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
143 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
147 multiclass VOP2eInst <string opName,
149 SDPatternOperator node = null_frag,
150 string revOp = opName,
151 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
153 let SchedRW = [Write32Bit] in {
154 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
155 def _e32 : VOP2_Pseudo <opName, P>,
156 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
159 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
160 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
164 class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
165 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
166 field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm);
167 field string Asm32 = "$vdst, $src0, $src1, $imm";
168 field bit HasExt = 0;
171 def VOP_MADAK_F16 : VOP_MADAK <f16>;
172 def VOP_MADAK_F32 : VOP_MADAK <f32>;
174 class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
175 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
176 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
177 field string Asm32 = "$vdst, $src0, $imm, $src1";
178 field bit HasExt = 0;
181 def VOP_MADMK_F16 : VOP_MADMK <f16>;
182 def VOP_MADMK_F32 : VOP_MADMK <f32>;
184 // FIXME: Remove src2_modifiers. It isn't used, so is wasting memory
185 // and processing time but it makes it easier to convert to mad.
186 class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
187 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
188 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
189 HasModifiers, HasOMod, Src0Mod, Src1Mod, Src2Mod>.ret;
190 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
191 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
192 VGPR_32:$src2, // stub argument
193 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
194 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
195 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
196 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
197 VGPR_32:$src2, // stub argument
198 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
199 src0_sel:$src0_sel, src1_sel:$src1_sel);
200 let Asm32 = getAsm32<1, 2, vt>.ret;
201 let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, vt>.ret;
202 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret;
203 let AsmSDWA = getAsmSDWA<1, 2, HasModifiers, vt>.ret;
209 def VOP_MAC_F16 : VOP_MAC <f16> {
210 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
211 // 'not a string initializer' error.
212 let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, f16>.ret;
215 def VOP_MAC_F32 : VOP_MAC <f32> {
216 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
217 // 'not a string initializer' error.
218 let Asm64 = getAsm64<1, 2, HasModifiers, HasOMod, f32>.ret;
221 // Write out to vcc or arbitrary SGPR.
222 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
223 let Asm32 = "$vdst, vcc, $src0, $src1";
224 let Asm64 = "$vdst, $sdst, $src0, $src1";
225 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
226 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
227 let Outs32 = (outs DstRC:$vdst);
228 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
231 // Write out to vcc or arbitrary SGPR and read in from vcc or
233 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
234 // We use VCSrc_b32 to exclude literal constants, even though the
235 // encoding normally allows them since the implicit VCC use means
236 // using one would always violate the constant bus
237 // restriction. SGPRs are still allowed because it should
238 // technically be possible to use VCC again as src0.
239 let Src0RC32 = VCSrc_b32;
240 let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
241 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
242 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
243 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
244 let Outs32 = (outs DstRC:$vdst);
245 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
247 // Suppress src2 implied by type since the 32-bit encoding uses an
249 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
251 let InsSDWA = (ins Src0Mod:$src0_modifiers, Src0SDWA:$src0,
252 Src1Mod:$src1_modifiers, Src1SDWA:$src1,
253 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
254 src0_sel:$src0_sel, src1_sel:$src1_sel);
256 let InsDPP = (ins Src0Mod:$src0_modifiers, Src0DPP:$src0,
257 Src1Mod:$src1_modifiers, Src1DPP:$src1,
258 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
259 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
263 // Read in from vcc or arbitrary SGPR
264 def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
265 let Src0RC32 = VCSrc_b32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above.
266 let Asm32 = "$vdst, $src0, $src1, vcc";
267 let Asm64 = "$vdst, $src0, $src1, $src2";
268 let Outs32 = (outs DstRC:$vdst);
269 let Outs64 = (outs DstRC:$vdst);
271 // Suppress src2 implied by type since the 32-bit encoding uses an
273 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
276 def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
277 let Outs32 = (outs SReg_32:$vdst);
279 let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1);
281 let Asm32 = " $vdst, $src0, $src1";
285 def VOP_WRITELANE : VOPProfile<[i32, i32, i32]> {
286 let Outs32 = (outs VGPR_32:$vdst);
288 let Ins32 = (ins SCSrc_b32:$src0, SCSrc_b32:$src1);
290 let Asm32 = " $vdst, $src0, $src1";
294 //===----------------------------------------------------------------------===//
296 //===----------------------------------------------------------------------===//
298 let SubtargetPredicate = isGCN in {
300 defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
301 def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32>;
303 let isCommutable = 1 in {
304 defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>;
305 defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>;
306 defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
307 defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
308 defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>;
309 defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24>;
310 defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>;
311 defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>;
312 defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>;
313 defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum>;
314 defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum>;
315 defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_I32_I32_I32>;
316 defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_I32_I32_I32>;
317 defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_I32_I32_I32>;
318 defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_I32_I32_I32>;
319 defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">;
320 defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">;
321 defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">;
322 defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_I32_I32_I32>;
323 defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_I32_I32_I32>;
324 defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_I32_I32_I32>;
326 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
327 isConvertibleToThreeAddress = 1 in {
328 defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
331 def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32>;
333 // No patterns so that the scalar instructions are always selected.
334 // The scalar versions will be replaced with vector when needed later.
336 // V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
337 // but the VI instructions behave the same as the SI versions.
338 defm V_ADD_I32 : VOP2bInst <"v_add_i32", VOP2b_I32_I1_I32_I32>;
339 defm V_SUB_I32 : VOP2bInst <"v_sub_i32", VOP2b_I32_I1_I32_I32>;
340 defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32">;
341 defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1>;
342 defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1>;
343 defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
344 } // End isCommutable = 1
346 // These are special and do not read the exec mask.
347 let isConvergent = 1, Uses = []<Register> in {
348 def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
349 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))], "">;
351 def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, [], "">;
352 } // End isConvergent = 1
354 defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>;
355 defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32>;
356 defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>;
357 defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>;
358 defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp>;
359 defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_I32_F32_I32>; // TODO: set "Uses = dst"
360 defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_I32_F32_F32>;
361 defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_I32_F32_F32>;
362 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_I32_F32_F32, AMDGPUpkrtz_f16_f32>;
363 defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_I32_I32_I32>;
364 defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_I32_I32_I32>;
366 } // End SubtargetPredicate = isGCN
369 // These instructions only exist on SI and CI
370 let SubtargetPredicate = isSICI in {
372 defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
373 defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
375 let isCommutable = 1 in {
376 defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>;
377 defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_I32_I32_I32>;
378 defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_I32_I32_I32>;
379 defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_I32_I32_I32>;
380 } // End isCommutable = 1
382 } // End let SubtargetPredicate = SICI
384 let SubtargetPredicate = isVI in {
386 def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16>;
387 defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>;
388 defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>;
389 defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>;
390 defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
392 let isCommutable = 1 in {
393 defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>;
394 defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>;
395 defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
396 defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>;
397 def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16>;
398 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>;
399 defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>;
400 defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">;
401 defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>;
402 defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum>;
403 defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum>;
404 defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16>;
405 defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16>;
406 defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16>;
407 defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16>;
409 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
410 isConvertibleToThreeAddress = 1 in {
411 defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
413 } // End isCommutable = 1
415 } // End SubtargetPredicate = isVI
417 // Note: 16-bit instructions produce a 0 result in the high 16-bits.
418 multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst> {
421 (op i16:$src0, i16:$src1),
426 (i32 (zext (op i16:$src0, i16:$src1))),
431 (i64 (zext (op i16:$src0, i16:$src1))),
432 (REG_SEQUENCE VReg_64,
433 (inst $src0, $src1), sub0,
434 (V_MOV_B32_e32 (i32 0)), sub1)
439 multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> {
442 (op i16:$src0, i16:$src1),
447 (i32 (zext (op i16:$src0, i16:$src1))),
453 (i64 (zext (op i16:$src0, i16:$src1))),
454 (REG_SEQUENCE VReg_64,
455 (inst $src1, $src0), sub0,
456 (V_MOV_B32_e32 (i32 0)), sub1)
460 class ZExt_i16_i1_Pat <SDNode ext> : Pat <
462 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)
465 let Predicates = [isVI] in {
467 defm : Arithmetic_i16_Pats<add, V_ADD_U16_e64>;
468 defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e64>;
469 defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e64>;
470 defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e64>;
471 defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e64>;
472 defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64>;
473 defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64>;
476 (and i16:$src0, i16:$src1),
477 (V_AND_B32_e64 $src0, $src1)
481 (or i16:$src0, i16:$src1),
482 (V_OR_B32_e64 $src0, $src1)
486 (xor i16:$src0, i16:$src1),
487 (V_XOR_B32_e64 $src0, $src1)
490 defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>;
491 defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>;
492 defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e64>;
494 def : ZExt_i16_i1_Pat<zext>;
495 def : ZExt_i16_i1_Pat<anyext>;
498 (i16 (sext i1:$src)),
499 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)
502 // Undo sub x, c -> add x, -c canonicalization since c is more likely
503 // an inline immediate than -c.
504 // TODO: Also do for 64-bit.
506 (add i16:$src0, (i16 NegSubInlineConst16:$src1)),
507 (V_SUB_U16_e64 $src0, NegSubInlineConst16:$src1)
510 } // End Predicates = [isVI]
512 //===----------------------------------------------------------------------===//
514 //===----------------------------------------------------------------------===//
516 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
518 multiclass VOP2_Real_si <bits<6> op> {
520 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
521 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
524 multiclass VOP2_Real_MADK_si <bits<6> op> {
525 def _si : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
526 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
529 multiclass VOP2_Real_e32_si <bits<6> op> {
531 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
532 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
535 multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
537 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
538 VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
541 multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
543 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
544 VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
547 } // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
549 defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>;
550 defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>;
551 defm V_SUB_F32 : VOP2_Real_e32e64_si <0x4>;
552 defm V_SUBREV_F32 : VOP2_Real_e32e64_si <0x5>;
553 defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_si <0x7>;
554 defm V_MUL_F32 : VOP2_Real_e32e64_si <0x8>;
555 defm V_MUL_I32_I24 : VOP2_Real_e32e64_si <0x9>;
556 defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_si <0xa>;
557 defm V_MUL_U32_U24 : VOP2_Real_e32e64_si <0xb>;
558 defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_si <0xc>;
559 defm V_MIN_F32 : VOP2_Real_e32e64_si <0xf>;
560 defm V_MAX_F32 : VOP2_Real_e32e64_si <0x10>;
561 defm V_MIN_I32 : VOP2_Real_e32e64_si <0x11>;
562 defm V_MAX_I32 : VOP2_Real_e32e64_si <0x12>;
563 defm V_MIN_U32 : VOP2_Real_e32e64_si <0x13>;
564 defm V_MAX_U32 : VOP2_Real_e32e64_si <0x14>;
565 defm V_LSHRREV_B32 : VOP2_Real_e32e64_si <0x16>;
566 defm V_ASHRREV_I32 : VOP2_Real_e32e64_si <0x18>;
567 defm V_LSHLREV_B32 : VOP2_Real_e32e64_si <0x1a>;
568 defm V_AND_B32 : VOP2_Real_e32e64_si <0x1b>;
569 defm V_OR_B32 : VOP2_Real_e32e64_si <0x1c>;
570 defm V_XOR_B32 : VOP2_Real_e32e64_si <0x1d>;
571 defm V_MAC_F32 : VOP2_Real_e32e64_si <0x1f>;
572 defm V_MADMK_F32 : VOP2_Real_MADK_si <0x20>;
573 defm V_MADAK_F32 : VOP2_Real_MADK_si <0x21>;
574 defm V_ADD_I32 : VOP2be_Real_e32e64_si <0x25>;
575 defm V_SUB_I32 : VOP2be_Real_e32e64_si <0x26>;
576 defm V_SUBREV_I32 : VOP2be_Real_e32e64_si <0x27>;
577 defm V_ADDC_U32 : VOP2be_Real_e32e64_si <0x28>;
578 defm V_SUBB_U32 : VOP2be_Real_e32e64_si <0x29>;
579 defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>;
581 defm V_READLANE_B32 : VOP2_Real_si <0x01>;
583 let InOperandList = (ins SSrc_b32:$src0, SCSrc_b32:$src1) in {
584 defm V_WRITELANE_B32 : VOP2_Real_si <0x02>;
587 defm V_MAC_LEGACY_F32 : VOP2_Real_e32e64_si <0x6>;
588 defm V_MIN_LEGACY_F32 : VOP2_Real_e32e64_si <0xd>;
589 defm V_MAX_LEGACY_F32 : VOP2_Real_e32e64_si <0xe>;
590 defm V_LSHR_B32 : VOP2_Real_e32e64_si <0x15>;
591 defm V_ASHR_I32 : VOP2_Real_e32e64_si <0x17>;
592 defm V_LSHL_B32 : VOP2_Real_e32e64_si <0x19>;
594 defm V_BFM_B32 : VOP2_Real_e32e64_si <0x1e>;
595 defm V_BCNT_U32_B32 : VOP2_Real_e32e64_si <0x22>;
596 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e32e64_si <0x23>;
597 defm V_MBCNT_HI_U32_B32 : VOP2_Real_e32e64_si <0x24>;
598 defm V_LDEXP_F32 : VOP2_Real_e32e64_si <0x2b>;
599 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e32e64_si <0x2c>;
600 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e32e64_si <0x2d>;
601 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e32e64_si <0x2e>;
602 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e32e64_si <0x2f>;
603 defm V_CVT_PK_U16_U32 : VOP2_Real_e32e64_si <0x30>;
604 defm V_CVT_PK_I16_I32 : VOP2_Real_e32e64_si <0x31>;
607 //===----------------------------------------------------------------------===//
609 //===----------------------------------------------------------------------===//
611 class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> :
612 VOP_DPP <ps.OpName, P> {
615 let SchedRW = ps.SchedRW;
616 let hasSideEffects = ps.hasSideEffects;
617 let Constraints = ps.Constraints;
618 let DisableEncoding = ps.DisableEncoding;
622 let Inst{8-0} = 0xfa; //dpp
623 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
624 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
625 let Inst{30-25} = op;
626 let Inst{31} = 0x0; //encoding
629 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
631 multiclass VOP32_Real_vi <bits<10> op> {
633 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
634 VOP3e_vi<op, !cast<VOP2_Pseudo>(NAME).Pfl>;
637 multiclass VOP2_Real_MADK_vi <bits<6> op> {
638 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
639 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
642 multiclass VOP2_Real_e32_vi <bits<6> op> {
644 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
645 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
648 multiclass VOP2_Real_e64_vi <bits<10> op> {
650 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
651 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
654 multiclass Base_VOP2be_Real_e32e64_vi <bits<6> op> : VOP2_Real_e32_vi<op> {
656 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
657 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
660 multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
661 VOP2_Real_e32_vi<op>,
662 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
664 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
666 multiclass VOP2_SDWA_Real <bits<6> op> {
668 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
669 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
672 multiclass VOP2be_Real_e32e64_vi <bits<6> op> :
673 Base_VOP2be_Real_e32e64_vi<op>, VOP2_SDWA_Real<op> {
674 // For now left dpp only for asm/dasm
675 // TODO: add corresponding pseudo
676 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
679 multiclass VOP2_Real_e32e64_vi <bits<6> op> :
680 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op> {
681 // For now left dpp only for asm/dasm
682 // TODO: add corresponding pseudo
683 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
686 defm V_CNDMASK_B32 : Base_VOP2_Real_e32e64_vi <0x0>;
687 defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>;
688 defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>;
689 defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>;
690 defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>;
691 defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>;
692 defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>;
693 defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>;
694 defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>;
695 defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>;
696 defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>;
697 defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>;
698 defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>;
699 defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>;
700 defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>;
701 defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>;
702 defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>;
703 defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>;
704 defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>;
705 defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>;
706 defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>;
707 defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>;
708 defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>;
709 defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>;
710 defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>;
711 defm V_ADD_I32 : VOP2be_Real_e32e64_vi <0x19>;
712 defm V_SUB_I32 : VOP2be_Real_e32e64_vi <0x1a>;
713 defm V_SUBREV_I32 : VOP2be_Real_e32e64_vi <0x1b>;
714 defm V_ADDC_U32 : VOP2be_Real_e32e64_vi <0x1c>;
715 defm V_SUBB_U32 : VOP2be_Real_e32e64_vi <0x1d>;
716 defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi <0x1e>;
718 defm V_READLANE_B32 : VOP32_Real_vi <0x289>;
719 defm V_WRITELANE_B32 : VOP32_Real_vi <0x28a>;
721 defm V_BFM_B32 : VOP2_Real_e64_vi <0x293>;
722 defm V_BCNT_U32_B32 : VOP2_Real_e64_vi <0x28b>;
723 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64_vi <0x28c>;
724 defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64_vi <0x28d>;
725 defm V_LDEXP_F32 : VOP2_Real_e64_vi <0x288>;
726 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64_vi <0x1f0>;
727 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64_vi <0x294>;
728 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64_vi <0x295>;
729 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64_vi <0x296>;
730 defm V_CVT_PK_U16_U32 : VOP2_Real_e64_vi <0x297>;
731 defm V_CVT_PK_I16_I32 : VOP2_Real_e64_vi <0x298>;
733 defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>;
734 defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>;
735 defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>;
736 defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>;
737 defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>;
738 defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>;
739 defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>;
740 defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>;
741 defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>;
742 defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>;
743 defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;
744 defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;
745 defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;
746 defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>;
747 defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;
748 defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;
749 defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;
750 defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>;
751 defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;
752 defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;
753 defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;
755 let SubtargetPredicate = isVI in {
757 // Aliases to simplify matching of floating-point instructions that
758 // are VOP2 on SI and VOP3 on VI.
759 class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
760 name#" $dst, $src0, $src1",
761 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0)
762 >, PredicateControl {
763 let UseInstAsmMatchConverter = 0;
764 let AsmVariantName = AMDGPUAsmVariants.VOP3;
767 def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
768 def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
769 def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
770 def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
771 def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
773 } // End SubtargetPredicate = isVI