1 //===-- VOP2Instructions.td - Vector Instruction Defintions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class VOP2e <bits<6> op, VOPProfile P> : Enc32 {
19 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
20 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
21 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
23 let Inst{31} = 0x0; //encoding
26 class VOP2_MADKe <bits<6> op, VOPProfile P> : Enc64 {
32 let Inst{8-0} = !if(P.HasSrc0, src0, 0);
33 let Inst{16-9} = !if(P.HasSrc1, src1, 0);
34 let Inst{24-17} = !if(P.EmitDst, vdst, 0);
36 let Inst{31} = 0x0; // encoding
37 let Inst{63-32} = imm;
40 class VOP2_SDWAe <bits<6> op, VOPProfile P> : VOP_SDWAe <P> {
44 let Inst{8-0} = 0xf9; // sdwa
45 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
46 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
48 let Inst{31} = 0x0; // encoding
51 class VOP2_Pseudo <string opName, VOPProfile P, list<dag> pattern=[], string suffix = "_e32"> :
52 InstSI <P.Outs32, P.Ins32, "", pattern>,
54 SIMCInstr <opName#suffix, SIEncodingFamily.NONE>,
55 MnemonicAlias<opName#suffix, opName> {
58 let isCodeGenOnly = 1;
59 let UseNamedOperandTable = 1;
61 string Mnemonic = opName;
62 string AsmOperands = P.Asm32;
67 let hasSideEffects = 0;
68 let SubtargetPredicate = isGCN;
74 let AsmVariantName = AMDGPUAsmVariants.Default;
79 class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily> :
80 InstSI <ps.OutOperandList, ps.InOperandList, ps.Mnemonic # ps.AsmOperands, []>,
81 SIMCInstr <ps.PseudoInstr, EncodingFamily> {
84 let isCodeGenOnly = 0;
86 let Constraints = ps.Constraints;
87 let DisableEncoding = ps.DisableEncoding;
89 // copy relevant pseudo op flags
90 let SubtargetPredicate = ps.SubtargetPredicate;
91 let AsmMatchConverter = ps.AsmMatchConverter;
92 let AsmVariantName = ps.AsmVariantName;
93 let Constraints = ps.Constraints;
94 let DisableEncoding = ps.DisableEncoding;
95 let TSFlags = ps.TSFlags;
98 class VOP2_SDWA_Pseudo <string OpName, VOPProfile P, list<dag> pattern=[]> :
99 VOP_SDWA_Pseudo <OpName, P, pattern> {
100 let AsmMatchConverter = "cvtSdwaVOP2";
103 class getVOP2Pat64 <SDPatternOperator node, VOPProfile P> : LetDummies {
104 list<dag> ret = !if(P.HasModifiers,
106 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
107 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))],
108 [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))]);
111 multiclass VOP2Inst <string opName,
113 SDPatternOperator node = null_frag,
114 string revOp = opName> {
116 def _e32 : VOP2_Pseudo <opName, P>,
117 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
119 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
120 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
122 def _sdwa : VOP2_SDWA_Pseudo <opName, P>,
123 Commutable_REV<revOp#"_sdwa", !eq(revOp, opName)>;
126 // TODO: add SDWA pseudo instructions for VOP2bInst and VOP2eInst
127 multiclass VOP2bInst <string opName,
129 SDPatternOperator node = null_frag,
130 string revOp = opName,
131 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
133 let SchedRW = [Write32Bit, WriteSALU] in {
134 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]), Defs = [VCC] in {
135 def _e32 : VOP2_Pseudo <opName, P>,
136 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
138 def _sdwa : VOP2_SDWA_Pseudo <opName, P>,
139 Commutable_REV<revOp#"_sdwa", !eq(revOp, opName)>;
141 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
142 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
146 multiclass VOP2eInst <string opName,
148 SDPatternOperator node = null_frag,
149 string revOp = opName,
150 bit useSGPRInput = !eq(P.NumSrcArgs, 3)> {
152 let SchedRW = [Write32Bit] in {
153 let Uses = !if(useSGPRInput, [VCC, EXEC], [EXEC]) in {
154 def _e32 : VOP2_Pseudo <opName, P>,
155 Commutable_REV<revOp#"_e32", !eq(revOp, opName)>;
157 def _e64 : VOP3_Pseudo <opName, P, getVOP2Pat64<node, P>.ret>,
158 Commutable_REV<revOp#"_e64", !eq(revOp, opName)>;
162 class VOP_MADAK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
163 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
164 field dag Ins32 = (ins VCSrc_f32:$src0, VGPR_32:$src1, ImmOpType:$imm);
165 field string Asm32 = "$vdst, $src0, $src1, $imm";
166 field bit HasExt = 0;
169 def VOP_MADAK_F16 : VOP_MADAK <f16>;
170 def VOP_MADAK_F32 : VOP_MADAK <f32>;
172 class VOP_MADMK <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
173 field Operand ImmOpType = !if(!eq(vt.Size, 32), f32kimm, f16kimm);
174 field dag Ins32 = (ins VCSrc_f32:$src0, ImmOpType:$imm, VGPR_32:$src1);
175 field string Asm32 = "$vdst, $src0, $imm, $src1";
176 field bit HasExt = 0;
179 def VOP_MADMK_F16 : VOP_MADMK <f16>;
180 def VOP_MADMK_F32 : VOP_MADMK <f32>;
182 class VOP_MAC <ValueType vt> : VOPProfile <[vt, vt, vt, vt]> {
183 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1, VGPR_32:$src2);
184 let Ins64 = getIns64<Src0RC64, Src1RC64, RegisterOperand<VGPR_32>, 3,
185 HasModifiers, Src0Mod, Src1Mod, Src2Mod>.ret;
186 let InsDPP = (ins Src0ModDPP:$src0_modifiers, Src0DPP:$src0,
187 Src1ModDPP:$src1_modifiers, Src1DPP:$src1,
188 VGPR_32:$src2, // stub argument
189 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
190 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
191 let InsSDWA = (ins Src0ModSDWA:$src0_modifiers, Src0SDWA:$src0,
192 Src1ModSDWA:$src1_modifiers, Src1SDWA:$src1,
193 VGPR_32:$src2, // stub argument
194 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
195 src0_sel:$src0_sel, src1_sel:$src1_sel);
196 let Asm32 = getAsm32<1, 2, vt>.ret;
197 let AsmDPP = getAsmDPP<1, 2, HasModifiers, vt>.ret;
198 let AsmSDWA = getAsmSDWA<1, 2, HasModifiers, vt>.ret;
204 def VOP_MAC_F16 : VOP_MAC <f16> {
205 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
206 // 'not a string initializer' error.
207 let Asm64 = getAsm64<1, 2, HasModifiers, f16>.ret;
210 def VOP_MAC_F32 : VOP_MAC <f32> {
211 // FIXME: Move 'Asm64' definition to VOP_MAC, and use 'vt'. Currently it gives
212 // 'not a string initializer' error.
213 let Asm64 = getAsm64<1, 2, HasModifiers, f32>.ret;
216 // Write out to vcc or arbitrary SGPR.
217 def VOP2b_I32_I1_I32_I32 : VOPProfile<[i32, i32, i32, untyped]> {
218 let Asm32 = "$vdst, vcc, $src0, $src1";
219 let Asm64 = "$vdst, $sdst, $src0, $src1";
220 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers$clamp $dst_sel $dst_unused $src0_sel $src1_sel";
221 let AsmDPP = "$vdst, vcc, $src0, $src1 $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
222 let Outs32 = (outs DstRC:$vdst);
223 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
226 // Write out to vcc or arbitrary SGPR and read in from vcc or
228 def VOP2b_I32_I1_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
229 // We use VCSrc_b32 to exclude literal constants, even though the
230 // encoding normally allows them since the implicit VCC use means
231 // using one would always violate the constant bus
232 // restriction. SGPRs are still allowed because it should
233 // technically be possible to use VCC again as src0.
234 let Src0RC32 = VCSrc_b32;
235 let Asm32 = "$vdst, vcc, $src0, $src1, vcc";
236 let Asm64 = "$vdst, $sdst, $src0, $src1, $src2";
237 let AsmSDWA = "$vdst, vcc, $src0_modifiers, $src1_modifiers, vcc $clamp $dst_sel $dst_unused $src0_sel $src1_sel";
238 let AsmDPP = "$vdst, vcc, $src0, $src1, vcc $dpp_ctrl$row_mask$bank_mask$bound_ctrl";
239 let Outs32 = (outs DstRC:$vdst);
240 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
242 // Suppress src2 implied by type since the 32-bit encoding uses an
244 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
246 let InsSDWA = (ins Src0Mod:$src0_modifiers, Src0SDWA:$src0,
247 Src1Mod:$src1_modifiers, Src1SDWA:$src1,
248 clampmod:$clamp, dst_sel:$dst_sel, dst_unused:$dst_unused,
249 src0_sel:$src0_sel, src1_sel:$src1_sel);
251 let InsDPP = (ins Src0Mod:$src0_modifiers, Src0DPP:$src0,
252 Src1Mod:$src1_modifiers, Src1DPP:$src1,
253 dpp_ctrl:$dpp_ctrl, row_mask:$row_mask,
254 bank_mask:$bank_mask, bound_ctrl:$bound_ctrl);
258 // Read in from vcc or arbitrary SGPR
259 def VOP2e_I32_I32_I32_I1 : VOPProfile<[i32, i32, i32, i1]> {
260 let Src0RC32 = VCSrc_b32; // See comment in def VOP2b_I32_I1_I32_I32_I1 above.
261 let Asm32 = "$vdst, $src0, $src1, vcc";
262 let Asm64 = "$vdst, $src0, $src1, $src2";
263 let Outs32 = (outs DstRC:$vdst);
264 let Outs64 = (outs DstRC:$vdst);
266 // Suppress src2 implied by type since the 32-bit encoding uses an
268 let Ins32 = (ins Src0RC32:$src0, Src1RC32:$src1);
271 def VOP_READLANE : VOPProfile<[i32, i32, i32]> {
272 let Outs32 = (outs SReg_32:$vdst);
274 let Ins32 = (ins VGPR_32:$src0, SCSrc_b32:$src1);
276 let Asm32 = " $vdst, $src0, $src1";
280 def VOP_WRITELANE : VOPProfile<[i32, i32, i32]> {
281 let Outs32 = (outs VGPR_32:$vdst);
283 let Ins32 = (ins SReg_32:$src0, SCSrc_b32:$src1);
285 let Asm32 = " $vdst, $src0, $src1";
289 //===----------------------------------------------------------------------===//
291 //===----------------------------------------------------------------------===//
293 let SubtargetPredicate = isGCN in {
295 defm V_CNDMASK_B32 : VOP2eInst <"v_cndmask_b32", VOP2e_I32_I32_I32_I1>;
296 def V_MADMK_F32 : VOP2_Pseudo <"v_madmk_f32", VOP_MADMK_F32>;
298 let isCommutable = 1 in {
299 defm V_ADD_F32 : VOP2Inst <"v_add_f32", VOP_F32_F32_F32, fadd>;
300 defm V_SUB_F32 : VOP2Inst <"v_sub_f32", VOP_F32_F32_F32, fsub>;
301 defm V_SUBREV_F32 : VOP2Inst <"v_subrev_f32", VOP_F32_F32_F32, null_frag, "v_sub_f32">;
302 defm V_MUL_LEGACY_F32 : VOP2Inst <"v_mul_legacy_f32", VOP_F32_F32_F32, AMDGPUfmul_legacy>;
303 defm V_MUL_F32 : VOP2Inst <"v_mul_f32", VOP_F32_F32_F32, fmul>;
304 defm V_MUL_I32_I24 : VOP2Inst <"v_mul_i32_i24", VOP_I32_I32_I32, AMDGPUmul_i24>;
305 defm V_MUL_HI_I32_I24 : VOP2Inst <"v_mul_hi_i32_i24", VOP_I32_I32_I32, AMDGPUmulhi_i24>;
306 defm V_MUL_U32_U24 : VOP2Inst <"v_mul_u32_u24", VOP_I32_I32_I32, AMDGPUmul_u24>;
307 defm V_MUL_HI_U32_U24 : VOP2Inst <"v_mul_hi_u32_u24", VOP_I32_I32_I32, AMDGPUmulhi_u24>;
308 defm V_MIN_F32 : VOP2Inst <"v_min_f32", VOP_F32_F32_F32, fminnum>;
309 defm V_MAX_F32 : VOP2Inst <"v_max_f32", VOP_F32_F32_F32, fmaxnum>;
310 defm V_MIN_I32 : VOP2Inst <"v_min_i32", VOP_I32_I32_I32>;
311 defm V_MAX_I32 : VOP2Inst <"v_max_i32", VOP_I32_I32_I32>;
312 defm V_MIN_U32 : VOP2Inst <"v_min_u32", VOP_I32_I32_I32>;
313 defm V_MAX_U32 : VOP2Inst <"v_max_u32", VOP_I32_I32_I32>;
314 defm V_LSHRREV_B32 : VOP2Inst <"v_lshrrev_b32", VOP_I32_I32_I32, null_frag, "v_lshr_b32">;
315 defm V_ASHRREV_I32 : VOP2Inst <"v_ashrrev_i32", VOP_I32_I32_I32, null_frag, "v_ashr_i32">;
316 defm V_LSHLREV_B32 : VOP2Inst <"v_lshlrev_b32", VOP_I32_I32_I32, null_frag, "v_lshl_b32">;
317 defm V_AND_B32 : VOP2Inst <"v_and_b32", VOP_I32_I32_I32>;
318 defm V_OR_B32 : VOP2Inst <"v_or_b32", VOP_I32_I32_I32>;
319 defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_I32_I32_I32>;
321 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
322 isConvertibleToThreeAddress = 1 in {
323 defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
326 def V_MADAK_F32 : VOP2_Pseudo <"v_madak_f32", VOP_MADAK_F32>;
328 // No patterns so that the scalar instructions are always selected.
329 // The scalar versions will be replaced with vector when needed later.
331 // V_ADD_I32, V_SUB_I32, and V_SUBREV_I32 where renamed to *_U32 in VI,
332 // but the VI instructions behave the same as the SI versions.
333 defm V_ADD_I32 : VOP2bInst <"v_add_i32", VOP2b_I32_I1_I32_I32>;
334 defm V_SUB_I32 : VOP2bInst <"v_sub_i32", VOP2b_I32_I1_I32_I32>;
335 defm V_SUBREV_I32 : VOP2bInst <"v_subrev_i32", VOP2b_I32_I1_I32_I32, null_frag, "v_sub_i32">;
336 defm V_ADDC_U32 : VOP2bInst <"v_addc_u32", VOP2b_I32_I1_I32_I32_I1>;
337 defm V_SUBB_U32 : VOP2bInst <"v_subb_u32", VOP2b_I32_I1_I32_I32_I1>;
338 defm V_SUBBREV_U32 : VOP2bInst <"v_subbrev_u32", VOP2b_I32_I1_I32_I32_I1, null_frag, "v_subb_u32">;
339 } // End isCommutable = 1
341 // These are special and do not read the exec mask.
342 let isConvergent = 1, Uses = []<Register> in {
343 def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE,
344 [(set i32:$vdst, (int_amdgcn_readlane i32:$src0, i32:$src1))], "">;
346 def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, [], "">;
347 } // End isConvergent = 1
349 defm V_BFM_B32 : VOP2Inst <"v_bfm_b32", VOP_I32_I32_I32>;
350 defm V_BCNT_U32_B32 : VOP2Inst <"v_bcnt_u32_b32", VOP_I32_I32_I32>;
351 defm V_MBCNT_LO_U32_B32 : VOP2Inst <"v_mbcnt_lo_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_lo>;
352 defm V_MBCNT_HI_U32_B32 : VOP2Inst <"v_mbcnt_hi_u32_b32", VOP_I32_I32_I32, int_amdgcn_mbcnt_hi>;
353 defm V_LDEXP_F32 : VOP2Inst <"v_ldexp_f32", VOP_F32_F32_I32, AMDGPUldexp>;
354 defm V_CVT_PKACCUM_U8_F32 : VOP2Inst <"v_cvt_pkaccum_u8_f32", VOP_I32_F32_I32>; // TODO: set "Uses = dst"
355 defm V_CVT_PKNORM_I16_F32 : VOP2Inst <"v_cvt_pknorm_i16_f32", VOP_I32_F32_F32>;
356 defm V_CVT_PKNORM_U16_F32 : VOP2Inst <"v_cvt_pknorm_u16_f32", VOP_I32_F32_F32>;
357 defm V_CVT_PKRTZ_F16_F32 : VOP2Inst <"v_cvt_pkrtz_f16_f32", VOP_I32_F32_F32, int_SI_packf16>;
358 defm V_CVT_PK_U16_U32 : VOP2Inst <"v_cvt_pk_u16_u32", VOP_I32_I32_I32>;
359 defm V_CVT_PK_I16_I32 : VOP2Inst <"v_cvt_pk_i16_i32", VOP_I32_I32_I32>;
361 } // End SubtargetPredicate = isGCN
364 // These instructions only exist on SI and CI
365 let SubtargetPredicate = isSICI in {
367 defm V_MIN_LEGACY_F32 : VOP2Inst <"v_min_legacy_f32", VOP_F32_F32_F32, AMDGPUfmin_legacy>;
368 defm V_MAX_LEGACY_F32 : VOP2Inst <"v_max_legacy_f32", VOP_F32_F32_F32, AMDGPUfmax_legacy>;
370 let isCommutable = 1 in {
371 defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_F32_F32_F32>;
372 defm V_LSHR_B32 : VOP2Inst <"v_lshr_b32", VOP_I32_I32_I32>;
373 defm V_ASHR_I32 : VOP2Inst <"v_ashr_i32", VOP_I32_I32_I32>;
374 defm V_LSHL_B32 : VOP2Inst <"v_lshl_b32", VOP_I32_I32_I32>;
375 } // End isCommutable = 1
377 } // End let SubtargetPredicate = SICI
379 let SubtargetPredicate = isVI in {
381 def V_MADMK_F16 : VOP2_Pseudo <"v_madmk_f16", VOP_MADMK_F16>;
382 defm V_LSHLREV_B16 : VOP2Inst <"v_lshlrev_b16", VOP_I16_I16_I16>;
383 defm V_LSHRREV_B16 : VOP2Inst <"v_lshrrev_b16", VOP_I16_I16_I16>;
384 defm V_ASHRREV_I16 : VOP2Inst <"v_ashrrev_i16", VOP_I16_I16_I16>;
385 defm V_LDEXP_F16 : VOP2Inst <"v_ldexp_f16", VOP_F16_F16_I32, AMDGPUldexp>;
387 let isCommutable = 1 in {
388 defm V_ADD_F16 : VOP2Inst <"v_add_f16", VOP_F16_F16_F16, fadd>;
389 defm V_SUB_F16 : VOP2Inst <"v_sub_f16", VOP_F16_F16_F16, fsub>;
390 defm V_SUBREV_F16 : VOP2Inst <"v_subrev_f16", VOP_F16_F16_F16, null_frag, "v_sub_f16">;
391 defm V_MUL_F16 : VOP2Inst <"v_mul_f16", VOP_F16_F16_F16, fmul>;
392 def V_MADAK_F16 : VOP2_Pseudo <"v_madak_f16", VOP_MADAK_F16>;
393 defm V_ADD_U16 : VOP2Inst <"v_add_u16", VOP_I16_I16_I16>;
394 defm V_SUB_U16 : VOP2Inst <"v_sub_u16" , VOP_I16_I16_I16>;
395 defm V_SUBREV_U16 : VOP2Inst <"v_subrev_u16", VOP_I16_I16_I16, null_frag, "v_sub_u16">;
396 defm V_MUL_LO_U16 : VOP2Inst <"v_mul_lo_u16", VOP_I16_I16_I16>;
397 defm V_MAX_F16 : VOP2Inst <"v_max_f16", VOP_F16_F16_F16, fmaxnum>;
398 defm V_MIN_F16 : VOP2Inst <"v_min_f16", VOP_F16_F16_F16, fminnum>;
399 defm V_MAX_U16 : VOP2Inst <"v_max_u16", VOP_I16_I16_I16>;
400 defm V_MAX_I16 : VOP2Inst <"v_max_i16", VOP_I16_I16_I16>;
401 defm V_MIN_U16 : VOP2Inst <"v_min_u16", VOP_I16_I16_I16>;
402 defm V_MIN_I16 : VOP2Inst <"v_min_i16", VOP_I16_I16_I16>;
404 let Constraints = "$vdst = $src2", DisableEncoding="$src2",
405 isConvertibleToThreeAddress = 1 in {
406 defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
408 } // End isCommutable = 1
410 } // End SubtargetPredicate = isVI
412 // Note: 16-bit instructions produce a 0 result in the high 16-bits.
413 multiclass Arithmetic_i16_Pats <SDPatternOperator op, Instruction inst> {
416 (op i16:$src0, i16:$src1),
421 (i32 (zext (op i16:$src0, i16:$src1))),
426 (i64 (zext (op i16:$src0, i16:$src1))),
427 (REG_SEQUENCE VReg_64,
428 (inst $src0, $src1), sub0,
429 (V_MOV_B32_e32 (i32 0)), sub1)
434 multiclass Bits_OpsRev_i16_Pats <SDPatternOperator op, Instruction inst> {
437 (op i16:$src0, i16:$src1),
442 (i32 (zext (op i16:$src0, i16:$src1))),
448 (i64 (zext (op i16:$src0, i16:$src1))),
449 (REG_SEQUENCE VReg_64,
450 (inst $src1, $src0), sub0,
451 (V_MOV_B32_e32 (i32 0)), sub1)
455 class ZExt_i16_i1_Pat <SDNode ext> : Pat <
457 (V_CNDMASK_B32_e64 (i32 0), (i32 1), $src)
460 let Predicates = [isVI] in {
462 defm : Arithmetic_i16_Pats<add, V_ADD_U16_e64>;
463 defm : Arithmetic_i16_Pats<mul, V_MUL_LO_U16_e64>;
464 defm : Arithmetic_i16_Pats<sub, V_SUB_U16_e64>;
465 defm : Arithmetic_i16_Pats<smin, V_MIN_I16_e64>;
466 defm : Arithmetic_i16_Pats<smax, V_MAX_I16_e64>;
467 defm : Arithmetic_i16_Pats<umin, V_MIN_U16_e64>;
468 defm : Arithmetic_i16_Pats<umax, V_MAX_U16_e64>;
471 (and i16:$src0, i16:$src1),
472 (V_AND_B32_e64 $src0, $src1)
476 (or i16:$src0, i16:$src1),
477 (V_OR_B32_e64 $src0, $src1)
481 (xor i16:$src0, i16:$src1),
482 (V_XOR_B32_e64 $src0, $src1)
485 defm : Bits_OpsRev_i16_Pats<shl, V_LSHLREV_B16_e64>;
486 defm : Bits_OpsRev_i16_Pats<srl, V_LSHRREV_B16_e64>;
487 defm : Bits_OpsRev_i16_Pats<sra, V_ASHRREV_I16_e64>;
489 def : ZExt_i16_i1_Pat<zext>;
490 def : ZExt_i16_i1_Pat<anyext>;
493 (i16 (sext i1:$src)),
494 (V_CNDMASK_B32_e64 (i32 0), (i32 -1), $src)
497 } // End Predicates = [isVI]
499 //===----------------------------------------------------------------------===//
501 //===----------------------------------------------------------------------===//
503 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
505 multiclass VOP2_Real_si <bits<6> op> {
507 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
508 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
511 multiclass VOP2_Real_MADK_si <bits<6> op> {
512 def _si : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
513 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
516 multiclass VOP2_Real_e32_si <bits<6> op> {
518 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
519 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
522 multiclass VOP2_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
524 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
525 VOP3e_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
528 multiclass VOP2be_Real_e32e64_si <bits<6> op> : VOP2_Real_e32_si<op> {
530 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
531 VOP3be_si <{1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
534 } // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
536 defm V_CNDMASK_B32 : VOP2_Real_e32e64_si <0x0>;
537 defm V_ADD_F32 : VOP2_Real_e32e64_si <0x3>;
538 defm V_SUB_F32 : VOP2_Real_e32e64_si <0x4>;
539 defm V_SUBREV_F32 : VOP2_Real_e32e64_si <0x5>;
540 defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_si <0x7>;
541 defm V_MUL_F32 : VOP2_Real_e32e64_si <0x8>;
542 defm V_MUL_I32_I24 : VOP2_Real_e32e64_si <0x9>;
543 defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_si <0xa>;
544 defm V_MUL_U32_U24 : VOP2_Real_e32e64_si <0xb>;
545 defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_si <0xc>;
546 defm V_MIN_F32 : VOP2_Real_e32e64_si <0xf>;
547 defm V_MAX_F32 : VOP2_Real_e32e64_si <0x10>;
548 defm V_MIN_I32 : VOP2_Real_e32e64_si <0x11>;
549 defm V_MAX_I32 : VOP2_Real_e32e64_si <0x12>;
550 defm V_MIN_U32 : VOP2_Real_e32e64_si <0x13>;
551 defm V_MAX_U32 : VOP2_Real_e32e64_si <0x14>;
552 defm V_LSHRREV_B32 : VOP2_Real_e32e64_si <0x16>;
553 defm V_ASHRREV_I32 : VOP2_Real_e32e64_si <0x18>;
554 defm V_LSHLREV_B32 : VOP2_Real_e32e64_si <0x1a>;
555 defm V_AND_B32 : VOP2_Real_e32e64_si <0x1b>;
556 defm V_OR_B32 : VOP2_Real_e32e64_si <0x1c>;
557 defm V_XOR_B32 : VOP2_Real_e32e64_si <0x1d>;
558 defm V_MAC_F32 : VOP2_Real_e32e64_si <0x1f>;
559 defm V_MADMK_F32 : VOP2_Real_MADK_si <0x20>;
560 defm V_MADAK_F32 : VOP2_Real_MADK_si <0x21>;
561 defm V_ADD_I32 : VOP2be_Real_e32e64_si <0x25>;
562 defm V_SUB_I32 : VOP2be_Real_e32e64_si <0x26>;
563 defm V_SUBREV_I32 : VOP2be_Real_e32e64_si <0x27>;
564 defm V_ADDC_U32 : VOP2be_Real_e32e64_si <0x28>;
565 defm V_SUBB_U32 : VOP2be_Real_e32e64_si <0x29>;
566 defm V_SUBBREV_U32 : VOP2be_Real_e32e64_si <0x2a>;
568 defm V_READLANE_B32 : VOP2_Real_si <0x01>;
569 defm V_WRITELANE_B32 : VOP2_Real_si <0x02>;
571 defm V_MAC_LEGACY_F32 : VOP2_Real_e32e64_si <0x6>;
572 defm V_MIN_LEGACY_F32 : VOP2_Real_e32e64_si <0xd>;
573 defm V_MAX_LEGACY_F32 : VOP2_Real_e32e64_si <0xe>;
574 defm V_LSHR_B32 : VOP2_Real_e32e64_si <0x15>;
575 defm V_ASHR_I32 : VOP2_Real_e32e64_si <0x17>;
576 defm V_LSHL_B32 : VOP2_Real_e32e64_si <0x19>;
578 defm V_BFM_B32 : VOP2_Real_e32e64_si <0x1e>;
579 defm V_BCNT_U32_B32 : VOP2_Real_e32e64_si <0x22>;
580 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e32e64_si <0x23>;
581 defm V_MBCNT_HI_U32_B32 : VOP2_Real_e32e64_si <0x24>;
582 defm V_LDEXP_F32 : VOP2_Real_e32e64_si <0x2b>;
583 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e32e64_si <0x2c>;
584 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e32e64_si <0x2d>;
585 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e32e64_si <0x2e>;
586 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e32e64_si <0x2f>;
587 defm V_CVT_PK_U16_U32 : VOP2_Real_e32e64_si <0x30>;
588 defm V_CVT_PK_I16_I32 : VOP2_Real_e32e64_si <0x31>;
591 //===----------------------------------------------------------------------===//
593 //===----------------------------------------------------------------------===//
595 class VOP2_DPP <bits<6> op, VOP2_Pseudo ps, VOPProfile P = ps.Pfl> :
596 VOP_DPP <ps.OpName, P> {
599 let SchedRW = ps.SchedRW;
600 let hasSideEffects = ps.hasSideEffects;
601 let Constraints = ps.Constraints;
602 let DisableEncoding = ps.DisableEncoding;
606 let Inst{8-0} = 0xfa; //dpp
607 let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
608 let Inst{24-17} = !if(P.EmitDst, vdst{7-0}, 0);
609 let Inst{30-25} = op;
610 let Inst{31} = 0x0; //encoding
613 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
615 multiclass VOP32_Real_vi <bits<10> op> {
617 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
618 VOP3e_vi<op, !cast<VOP2_Pseudo>(NAME).Pfl>;
621 multiclass VOP2_Real_MADK_vi <bits<6> op> {
622 def _vi : VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.VI>,
623 VOP2_MADKe<op{5-0}, !cast<VOP2_Pseudo>(NAME).Pfl>;
626 multiclass VOP2_Real_e32_vi <bits<6> op> {
628 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
629 VOP2e<op{5-0}, !cast<VOP2_Pseudo>(NAME#"_e32").Pfl>;
632 multiclass VOP2_Real_e64_vi <bits<10> op> {
634 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
635 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
638 multiclass Base_VOP2be_Real_e32e64_vi <bits<6> op> : VOP2_Real_e32_vi<op> {
640 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
641 VOP3be_vi <{0, 1, 0, 0, op{5-0}}, !cast<VOP3_Pseudo>(NAME#"_e64").Pfl>;
644 multiclass Base_VOP2_Real_e32e64_vi <bits<6> op> :
645 VOP2_Real_e32_vi<op>,
646 VOP2_Real_e64_vi<{0, 1, 0, 0, op{5-0}}>;
648 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
650 multiclass VOP2_SDWA_Real <bits<6> op> {
652 VOP_SDWA_Real <!cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa")>,
653 VOP2_SDWAe <op{5-0}, !cast<VOP2_SDWA_Pseudo>(NAME#"_sdwa").Pfl>;
656 multiclass VOP2be_Real_e32e64_vi <bits<6> op> :
657 Base_VOP2be_Real_e32e64_vi<op>, VOP2_SDWA_Real<op> {
658 // For now left dpp only for asm/dasm
659 // TODO: add corresponding pseudo
660 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
663 multiclass VOP2_Real_e32e64_vi <bits<6> op> :
664 Base_VOP2_Real_e32e64_vi<op>, VOP2_SDWA_Real<op> {
665 // For now left dpp only for asm/dasm
666 // TODO: add corresponding pseudo
667 def _dpp : VOP2_DPP<op, !cast<VOP2_Pseudo>(NAME#"_e32")>;
670 defm V_CNDMASK_B32 : Base_VOP2_Real_e32e64_vi <0x0>;
671 defm V_ADD_F32 : VOP2_Real_e32e64_vi <0x1>;
672 defm V_SUB_F32 : VOP2_Real_e32e64_vi <0x2>;
673 defm V_SUBREV_F32 : VOP2_Real_e32e64_vi <0x3>;
674 defm V_MUL_LEGACY_F32 : VOP2_Real_e32e64_vi <0x4>;
675 defm V_MUL_F32 : VOP2_Real_e32e64_vi <0x5>;
676 defm V_MUL_I32_I24 : VOP2_Real_e32e64_vi <0x6>;
677 defm V_MUL_HI_I32_I24 : VOP2_Real_e32e64_vi <0x7>;
678 defm V_MUL_U32_U24 : VOP2_Real_e32e64_vi <0x8>;
679 defm V_MUL_HI_U32_U24 : VOP2_Real_e32e64_vi <0x9>;
680 defm V_MIN_F32 : VOP2_Real_e32e64_vi <0xa>;
681 defm V_MAX_F32 : VOP2_Real_e32e64_vi <0xb>;
682 defm V_MIN_I32 : VOP2_Real_e32e64_vi <0xc>;
683 defm V_MAX_I32 : VOP2_Real_e32e64_vi <0xd>;
684 defm V_MIN_U32 : VOP2_Real_e32e64_vi <0xe>;
685 defm V_MAX_U32 : VOP2_Real_e32e64_vi <0xf>;
686 defm V_LSHRREV_B32 : VOP2_Real_e32e64_vi <0x10>;
687 defm V_ASHRREV_I32 : VOP2_Real_e32e64_vi <0x11>;
688 defm V_LSHLREV_B32 : VOP2_Real_e32e64_vi <0x12>;
689 defm V_AND_B32 : VOP2_Real_e32e64_vi <0x13>;
690 defm V_OR_B32 : VOP2_Real_e32e64_vi <0x14>;
691 defm V_XOR_B32 : VOP2_Real_e32e64_vi <0x15>;
692 defm V_MAC_F32 : VOP2_Real_e32e64_vi <0x16>;
693 defm V_MADMK_F32 : VOP2_Real_MADK_vi <0x17>;
694 defm V_MADAK_F32 : VOP2_Real_MADK_vi <0x18>;
695 defm V_ADD_I32 : VOP2be_Real_e32e64_vi <0x19>;
696 defm V_SUB_I32 : VOP2be_Real_e32e64_vi <0x1a>;
697 defm V_SUBREV_I32 : VOP2be_Real_e32e64_vi <0x1b>;
698 defm V_ADDC_U32 : VOP2be_Real_e32e64_vi <0x1c>;
699 defm V_SUBB_U32 : VOP2be_Real_e32e64_vi <0x1d>;
700 defm V_SUBBREV_U32 : VOP2be_Real_e32e64_vi <0x1e>;
702 defm V_READLANE_B32 : VOP32_Real_vi <0x289>;
703 defm V_WRITELANE_B32 : VOP32_Real_vi <0x28a>;
705 defm V_BFM_B32 : VOP2_Real_e64_vi <0x293>;
706 defm V_BCNT_U32_B32 : VOP2_Real_e64_vi <0x28b>;
707 defm V_MBCNT_LO_U32_B32 : VOP2_Real_e64_vi <0x28c>;
708 defm V_MBCNT_HI_U32_B32 : VOP2_Real_e64_vi <0x28d>;
709 defm V_LDEXP_F32 : VOP2_Real_e64_vi <0x288>;
710 defm V_CVT_PKACCUM_U8_F32 : VOP2_Real_e64_vi <0x1f0>;
711 defm V_CVT_PKNORM_I16_F32 : VOP2_Real_e64_vi <0x294>;
712 defm V_CVT_PKNORM_U16_F32 : VOP2_Real_e64_vi <0x295>;
713 defm V_CVT_PKRTZ_F16_F32 : VOP2_Real_e64_vi <0x296>;
714 defm V_CVT_PK_U16_U32 : VOP2_Real_e64_vi <0x297>;
715 defm V_CVT_PK_I16_I32 : VOP2_Real_e64_vi <0x298>;
717 defm V_ADD_F16 : VOP2_Real_e32e64_vi <0x1f>;
718 defm V_SUB_F16 : VOP2_Real_e32e64_vi <0x20>;
719 defm V_SUBREV_F16 : VOP2_Real_e32e64_vi <0x21>;
720 defm V_MUL_F16 : VOP2_Real_e32e64_vi <0x22>;
721 defm V_MAC_F16 : VOP2_Real_e32e64_vi <0x23>;
722 defm V_MADMK_F16 : VOP2_Real_MADK_vi <0x24>;
723 defm V_MADAK_F16 : VOP2_Real_MADK_vi <0x25>;
724 defm V_ADD_U16 : VOP2_Real_e32e64_vi <0x26>;
725 defm V_SUB_U16 : VOP2_Real_e32e64_vi <0x27>;
726 defm V_SUBREV_U16 : VOP2_Real_e32e64_vi <0x28>;
727 defm V_MUL_LO_U16 : VOP2_Real_e32e64_vi <0x29>;
728 defm V_LSHLREV_B16 : VOP2_Real_e32e64_vi <0x2a>;
729 defm V_LSHRREV_B16 : VOP2_Real_e32e64_vi <0x2b>;
730 defm V_ASHRREV_I16 : VOP2_Real_e32e64_vi <0x2c>;
731 defm V_MAX_F16 : VOP2_Real_e32e64_vi <0x2d>;
732 defm V_MIN_F16 : VOP2_Real_e32e64_vi <0x2e>;
733 defm V_MAX_U16 : VOP2_Real_e32e64_vi <0x2f>;
734 defm V_MAX_I16 : VOP2_Real_e32e64_vi <0x30>;
735 defm V_MIN_U16 : VOP2_Real_e32e64_vi <0x31>;
736 defm V_MIN_I16 : VOP2_Real_e32e64_vi <0x32>;
737 defm V_LDEXP_F16 : VOP2_Real_e32e64_vi <0x33>;
739 let SubtargetPredicate = isVI in {
741 // Aliases to simplify matching of floating-point instructions that
742 // are VOP2 on SI and VOP3 on VI.
743 class SI2_VI3Alias <string name, Instruction inst> : InstAlias <
744 name#" $dst, $src0, $src1",
745 (inst VGPR_32:$dst, 0, VCSrc_f32:$src0, 0, VCSrc_f32:$src1, 0, 0)
746 >, PredicateControl {
747 let UseInstAsmMatchConverter = 0;
748 let AsmVariantName = AMDGPUAsmVariants.VOP3;
751 def : SI2_VI3Alias <"v_ldexp_f32", V_LDEXP_F32_e64_vi>;
752 def : SI2_VI3Alias <"v_cvt_pkaccum_u8_f32", V_CVT_PKACCUM_U8_F32_e64_vi>;
753 def : SI2_VI3Alias <"v_cvt_pknorm_i16_f32", V_CVT_PKNORM_I16_F32_e64_vi>;
754 def : SI2_VI3Alias <"v_cvt_pknorm_u16_f32", V_CVT_PKNORM_U16_F32_e64_vi>;
755 def : SI2_VI3Alias <"v_cvt_pkrtz_f16_f32", V_CVT_PKRTZ_F16_F32_e64_vi>;
757 } // End SubtargetPredicate = isVI