1 //===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
15 dag src0 = !if(P.HasOMod,
16 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod),
17 (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp));
19 list<dag> ret3 = [(set P.DstVT:$vdst,
20 (node (P.Src0VT src0),
21 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
22 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
24 list<dag> ret2 = [(set P.DstVT:$vdst,
25 (node (P.Src0VT src0),
26 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
28 list<dag> ret1 = [(set P.DstVT:$vdst,
29 (node (P.Src0VT src0)))];
31 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
32 !if(!eq(P.NumSrcArgs, 2), ret2,
36 class getVOP3PModPat<VOPProfile P, SDPatternOperator node> {
37 list<dag> ret3 = [(set P.DstVT:$vdst,
38 (node (P.Src0VT !if(P.HasClamp, (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
39 (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
40 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers)),
41 (P.Src2VT (VOP3PMods P.Src2VT:$src2, i32:$src2_modifiers))))];
43 list<dag> ret2 = [(set P.DstVT:$vdst,
44 (node !if(P.HasClamp, (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
45 (P.Src0VT (VOP3PMods P.Src0VT:$src0, i32:$src0_modifiers))),
46 (P.Src1VT (VOP3PMods P.Src1VT:$src1, i32:$src1_modifiers))))];
48 list<dag> ret1 = [(set P.DstVT:$vdst,
49 (node (P.Src0VT (VOP3PMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
51 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
52 !if(!eq(P.NumSrcArgs, 2), ret2,
56 class getVOP3OpSelPat<VOPProfile P, SDPatternOperator node> {
57 list<dag> ret3 = [(set P.DstVT:$vdst,
58 (node (P.Src0VT !if(P.HasClamp, (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
59 (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
60 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers)),
61 (P.Src2VT (VOP3OpSel P.Src2VT:$src2, i32:$src2_modifiers))))];
63 list<dag> ret2 = [(set P.DstVT:$vdst,
64 (node !if(P.HasClamp, (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
65 (P.Src0VT (VOP3OpSel P.Src0VT:$src0, i32:$src0_modifiers))),
66 (P.Src1VT (VOP3OpSel P.Src1VT:$src1, i32:$src1_modifiers))))];
68 list<dag> ret1 = [(set P.DstVT:$vdst,
69 (node (P.Src0VT (VOP3OpSel0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
71 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
72 !if(!eq(P.NumSrcArgs, 2), ret2,
76 class getVOP3OpSelModPat<VOPProfile P, SDPatternOperator node> {
77 list<dag> ret3 = [(set P.DstVT:$vdst,
78 (node (P.Src0VT !if(P.HasClamp, (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp),
79 (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
80 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers)),
81 (P.Src2VT (VOP3OpSelMods P.Src2VT:$src2, i32:$src2_modifiers))))];
83 list<dag> ret2 = [(set P.DstVT:$vdst,
84 (node !if(P.HasClamp, (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp)),
85 (P.Src0VT (VOP3OpSelMods P.Src0VT:$src0, i32:$src0_modifiers))),
86 (P.Src1VT (VOP3OpSelMods P.Src1VT:$src1, i32:$src1_modifiers))))];
88 list<dag> ret1 = [(set P.DstVT:$vdst,
89 (node (P.Src0VT (VOP3OpSelMods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp))))];
91 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
92 !if(!eq(P.NumSrcArgs, 2), ret2,
96 class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
97 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
98 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
99 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
100 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
101 !if(!eq(P.NumSrcArgs, 2), ret2,
105 class getVOP3ClampPat<VOPProfile P, SDPatternOperator node> {
106 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, i1:$clamp))];
107 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, i1:$clamp))];
108 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, i1:$clamp))];
109 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
110 !if(!eq(P.NumSrcArgs, 2), ret2,
114 class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
115 VOP3_Pseudo<OpName, P,
118 getVOP3OpSelModPat<P, node>.ret,
119 getVOP3OpSelPat<P, node>.ret),
121 getVOP3ModPat<P, node>.ret,
123 getVOP3ClampPat<P, node>.ret,
124 getVOP3Pat<P, node>.ret))),
125 VOP3Only, 0, P.HasOpSel> {
127 let IntClamp = P.HasIntClamp;
128 let AsmMatchConverter =
131 !if(!or(P.HasModifiers, !or(P.HasOMod, P.HasIntClamp)),
136 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
137 // only VOP instruction that implicitly reads VCC.
138 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
139 def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
140 let Outs64 = (outs DstRC.RegClass:$vdst);
142 def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
143 let Outs64 = (outs DstRC.RegClass:$vdst);
147 class getVOP3VCC<VOPProfile P, SDPatternOperator node> {
150 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
151 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
152 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
156 class VOP3Features<bit Clamp, bit OpSel, bit Packed> {
157 bit HasClamp = Clamp;
158 bit HasOpSel = OpSel;
159 bit IsPacked = Packed;
162 def VOP3_REGULAR : VOP3Features<0, 0, 0>;
163 def VOP3_CLAMP : VOP3Features<1, 0, 0>;
164 def VOP3_OPSEL : VOP3Features<1, 1, 0>;
165 def VOP3_PACKED : VOP3Features<1, 1, 1>;
167 class VOP3_Profile<VOPProfile P, VOP3Features Features = VOP3_REGULAR> : VOPProfile<P.ArgVT> {
169 let HasClamp = !if(Features.HasClamp, 1, P.HasClamp);
170 let HasOpSel = !if(Features.HasOpSel, 1, P.HasOpSel);
171 let IsPacked = !if(Features.IsPacked, 1, P.IsPacked);
173 let HasModifiers = !if(Features.IsPacked, 1, P.HasModifiers);
175 // FIXME: Hack to stop printing _e64
176 let Outs64 = (outs DstRC.RegClass:$vdst);
178 " " # !if(Features.HasOpSel,
179 getAsmVOP3OpSel<NumSrcArgs,
183 HasSrc2FloatMods>.ret,
184 !if(Features.HasClamp,
185 getAsm64<HasDst, NumSrcArgs, HasIntClamp,
186 HasModifiers, HasOMod, DstVT>.ret,
190 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
191 // v_div_scale_{f32|f64} do not support input modifiers.
192 let HasModifiers = 0;
194 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
195 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
198 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
199 // FIXME: Hack to stop printing _e64
200 let DstRC = RegisterOperand<VGPR_32>;
203 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
204 // FIXME: Hack to stop printing _e64
205 let DstRC = RegisterOperand<VReg_64>;
208 def VOP3b_I64_I1_I32_I32_I64 : VOPProfile<[i64, i32, i32, i64]> {
211 // FIXME: Hack to stop printing _e64
212 let DstRC = RegisterOperand<VReg_64>;
214 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
215 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2$clamp";
218 //===----------------------------------------------------------------------===//
220 //===----------------------------------------------------------------------===//
222 class VOP3Interp<string OpName, VOPProfile P> : VOP3_Pseudo<OpName, P> {
223 let AsmMatchConverter = "cvtVOP3Interp";
226 def VOP3_INTERP : VOPProfile<[f32, f32, i32, untyped]> {
227 let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
228 Attr:$attr, AttrChan:$attrchan,
229 clampmod:$clamp, omod:$omod);
231 let Asm64 = "$vdst, $src0_modifiers, $attr$attrchan$clamp$omod";
234 def VOP3_INTERP_MOV : VOPProfile<[f32, i32, i32, untyped]> {
235 let Ins64 = (ins InterpSlot:$src0,
236 Attr:$attr, AttrChan:$attrchan,
237 clampmod:$clamp, omod:$omod);
239 let Asm64 = "$vdst, $src0, $attr$attrchan$clamp$omod";
244 class getInterp16Asm <bit HasSrc2, bit HasOMod> {
245 string src2 = !if(HasSrc2, ", $src2_modifiers", "");
246 string omod = !if(HasOMod, "$omod", "");
248 " $vdst, $src0_modifiers, $attr$attrchan"#src2#"$high$clamp"#omod;
251 class getInterp16Ins <bit HasSrc2, bit HasOMod,
252 Operand Src0Mod, Operand Src2Mod> {
253 dag ret = !if(HasSrc2,
255 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
256 Attr:$attr, AttrChan:$attrchan,
257 Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
258 highmod:$high, clampmod:$clamp, omod:$omod),
259 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
260 Attr:$attr, AttrChan:$attrchan,
261 Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
262 highmod:$high, clampmod:$clamp)
264 (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
265 Attr:$attr, AttrChan:$attrchan,
266 highmod:$high, clampmod:$clamp, omod:$omod)
270 class VOP3_INTERP16 <list<ValueType> ArgVT> : VOPProfile<ArgVT> {
272 let HasOMod = !if(!eq(DstVT.Value, f16.Value), 0, 1);
275 let Outs64 = (outs VGPR_32:$vdst);
276 let Ins64 = getInterp16Ins<HasSrc2, HasOMod, Src0Mod, Src2Mod>.ret;
277 let Asm64 = getInterp16Asm<HasSrc2, HasOMod>.ret;
280 //===----------------------------------------------------------------------===//
282 //===----------------------------------------------------------------------===//
284 let isCommutable = 1 in {
286 def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
287 def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
288 def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
289 def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
290 def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
291 def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
293 let SchedRW = [WriteDoubleAdd] in {
294 def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
295 def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
296 def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
297 def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum, 1>;
298 def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum, 1>;
299 } // End SchedRW = [WriteDoubleAdd]
301 let SchedRW = [WriteQuarterRate32] in {
302 def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>>;
303 def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
304 def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
305 def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
306 } // End SchedRW = [WriteQuarterRate32]
308 let Uses = [VCC, EXEC] in {
310 // result = src0 * src1 + src2
314 def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC,
315 getVOP3VCC<VOP_F32_F32_F32_F32_VCC, AMDGPUdiv_fmas>.ret> {
316 let SchedRW = [WriteFloatFMA];
319 // result = src0 * src1 + src2
323 def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC,
324 getVOP3VCC<VOP_F64_F64_F64_F64_VCC, AMDGPUdiv_fmas>.ret> {
325 let SchedRW = [WriteDouble];
327 } // End Uses = [VCC, EXEC]
329 } // End isCommutable = 1
331 def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
332 def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
333 def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
334 def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
335 def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
336 def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
337 def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
338 def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbit>;
339 def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_alignbyte>;
340 def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
341 def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
342 def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
343 def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
344 def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
345 def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
346 def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
347 def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
348 def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
349 def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
350 def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
351 def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
352 def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
353 def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
354 def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
356 let SchedRW = [WriteDoubleAdd] in {
357 def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
358 def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
359 } // End SchedRW = [WriteDoubleAdd]
361 def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
362 let SchedRW = [WriteFloatFMA, WriteSALU];
363 let AsmMatchConverter = "";
366 // Double precision division pre-scale.
367 def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
368 let SchedRW = [WriteDouble, WriteSALU];
369 let AsmMatchConverter = "";
372 def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32, VOP3_CLAMP>>;
374 let Constraints = "@earlyclobber $vdst" in {
375 def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
376 } // End Constraints = "@earlyclobber $vdst"
378 def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
379 let SchedRW = [WriteDouble];
382 let SchedRW = [Write64Bit] in {
383 // These instructions only exist on SI and CI
384 let SubtargetPredicate = isSICI in {
385 def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>;
386 def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>;
387 def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>;
388 def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
389 } // End SubtargetPredicate = isSICI
391 let SubtargetPredicate = isVI in {
392 def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
393 def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
394 def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
395 } // End SubtargetPredicate = isVI
396 } // End SchedRW = [Write64Bit]
398 let SubtargetPredicate = isCIVI in {
400 let Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32] in {
401 def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64, VOP3_CLAMP>>;
402 def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32, VOP3_CLAMP>>;
403 } // End Constraints = "@earlyclobber $vdst", SchedRW = [WriteQuarterRate32]
405 let isCommutable = 1 in {
406 let SchedRW = [WriteQuarterRate32, WriteSALU] in {
407 def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3b_I64_I1_I32_I32_I64>;
408 def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3b_I64_I1_I32_I32_I64>;
409 } // End SchedRW = [WriteDouble, WriteSALU]
410 } // End isCommutable = 1
412 } // End SubtargetPredicate = isCIVI
415 def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup> {
416 let Predicates = [Has16BitInsts, isVIOnly];
418 def V_DIV_FIXUP_F16_gfx9 : VOP3Inst <"v_div_fixup_f16_gfx9",
419 VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUdiv_fixup> {
420 let renamedInGFX9 = 1;
421 let Predicates = [Has16BitInsts, isGFX9];
424 let SubtargetPredicate = Has16BitInsts, isCommutable = 1 in {
426 let renamedInGFX9 = 1 in {
427 def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
428 def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
429 def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_CLAMP>>;
430 def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
431 def V_INTERP_P2_F16 : VOP3Interp <"v_interp_p2_f16", VOP3_INTERP16<[f16, f32, i32, f32]>>;
434 let SubtargetPredicate = isGFX9 in {
435 def V_MAD_F16_gfx9 : VOP3Inst <"v_mad_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
436 def V_MAD_U16_gfx9 : VOP3Inst <"v_mad_u16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
437 def V_MAD_I16_gfx9 : VOP3Inst <"v_mad_i16_gfx9", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>>;
438 def V_FMA_F16_gfx9 : VOP3Inst <"v_fma_f16_gfx9", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>>;
439 def V_INTERP_P2_F16_gfx9 : VOP3Interp <"v_interp_p2_f16_gfx9", VOP3_INTERP16<[f16, f32, i32, f32]>>;
440 } // End SubtargetPredicate = isGFX9
442 def V_INTERP_P1LL_F16 : VOP3Interp <"v_interp_p1ll_f16", VOP3_INTERP16<[f32, f32, i32, untyped]>>;
443 def V_INTERP_P1LV_F16 : VOP3Interp <"v_interp_p1lv_f16", VOP3_INTERP16<[f32, f32, i32, f16]>>;
445 } // End SubtargetPredicate = Has16BitInsts, isCommutable = 1
447 let SubtargetPredicate = isVI in {
448 def V_INTERP_P1_F32_e64 : VOP3Interp <"v_interp_p1_f32", VOP3_INTERP>;
449 def V_INTERP_P2_F32_e64 : VOP3Interp <"v_interp_p2_f32", VOP3_INTERP>;
450 def V_INTERP_MOV_F32_e64 : VOP3Interp <"v_interp_mov_f32", VOP3_INTERP_MOV>;
452 def V_PERM_B32 : VOP3Inst <"v_perm_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUperm>;
453 } // End SubtargetPredicate = isVI
455 let Predicates = [Has16BitInsts] in {
457 multiclass Ternary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
458 Instruction inst, SDPatternOperator op3> {
460 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
461 (inst i16:$src0, i16:$src1, i16:$src2, (i1 0))
466 defm: Ternary_i16_Pats<mul, add, V_MAD_U16, zext>;
467 defm: Ternary_i16_Pats<mul, add, V_MAD_I16, sext>;
469 } // End Predicates = [Has16BitInsts]
471 let SubtargetPredicate = isGFX9 in {
472 def V_PACK_B32_F16 : VOP3Inst <"v_pack_b32_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
473 def V_LSHL_ADD_U32 : VOP3Inst <"v_lshl_add_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
474 def V_ADD_LSHL_U32 : VOP3Inst <"v_add_lshl_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
475 def V_ADD3_U32 : VOP3Inst <"v_add3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
476 def V_LSHL_OR_B32 : VOP3Inst <"v_lshl_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
477 def V_AND_OR_B32 : VOP3Inst <"v_and_or_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
478 def V_OR3_B32 : VOP3Inst <"v_or3_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
480 def V_XAD_U32 : VOP3Inst <"v_xad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
482 def V_MED3_F16 : VOP3Inst <"v_med3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmed3>;
483 def V_MED3_I16 : VOP3Inst <"v_med3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmed3>;
484 def V_MED3_U16 : VOP3Inst <"v_med3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumed3>;
486 def V_MIN3_F16 : VOP3Inst <"v_min3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmin3>;
487 def V_MIN3_I16 : VOP3Inst <"v_min3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmin3>;
488 def V_MIN3_U16 : VOP3Inst <"v_min3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumin3>;
490 def V_MAX3_F16 : VOP3Inst <"v_max3_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSEL>, AMDGPUfmax3>;
491 def V_MAX3_I16 : VOP3Inst <"v_max3_i16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUsmax3>;
492 def V_MAX3_U16 : VOP3Inst <"v_max3_u16", VOP3_Profile<VOP_I16_I16_I16_I16, VOP3_OPSEL>, AMDGPUumax3>;
494 def V_ADD_I16 : VOP3Inst <"v_add_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
495 def V_SUB_I16 : VOP3Inst <"v_sub_i16", VOP3_Profile<VOP_I16_I16_I16, VOP3_OPSEL>>;
497 def V_MAD_U32_U16 : VOP3Inst <"v_mad_u32_u16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
498 def V_MAD_I32_I16 : VOP3Inst <"v_mad_i32_i16", VOP3_Profile<VOP_I32_I16_I16_I32, VOP3_OPSEL>>;
500 def V_CVT_PKNORM_I16_F16 : VOP3Inst <"v_cvt_pknorm_i16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
501 def V_CVT_PKNORM_U16_F16 : VOP3Inst <"v_cvt_pknorm_u16_f16", VOP3_Profile<VOP_B32_F16_F16, VOP3_OPSEL>>;
503 def V_ADD_I32_gfx9 : VOP3Inst <"v_add_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
504 def V_SUB_I32_gfx9 : VOP3Inst <"v_sub_i32_gfx9", VOP3_Profile<VOP_I32_I32_I32>>;
505 } // End SubtargetPredicate = isGFX9
507 //===----------------------------------------------------------------------===//
508 // Integer Clamp Patterns
509 //===----------------------------------------------------------------------===//
511 class getClampPat<VOPProfile P, SDPatternOperator node> {
512 dag ret3 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2));
513 dag ret2 = (P.DstVT (node P.Src0VT:$src0, P.Src1VT:$src1));
514 dag ret1 = (P.DstVT (node P.Src0VT:$src0));
515 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
516 !if(!eq(P.NumSrcArgs, 2), ret2,
520 class getClampRes<VOPProfile P, Instruction inst> {
521 dag ret3 = (inst P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2, (i1 0));
522 dag ret2 = (inst P.Src0VT:$src0, P.Src1VT:$src1, (i1 0));
523 dag ret1 = (inst P.Src0VT:$src0, (i1 0));
524 dag ret = !if(!eq(P.NumSrcArgs, 3), ret3,
525 !if(!eq(P.NumSrcArgs, 2), ret2,
529 class IntClampPat<VOP3Inst inst, SDPatternOperator node> : GCNPat<
530 getClampPat<inst.Pfl, node>.ret,
531 getClampRes<inst.Pfl, inst>.ret
534 def : IntClampPat<V_MAD_I32_I24, AMDGPUmad_i24>;
535 def : IntClampPat<V_MAD_U32_U24, AMDGPUmad_u24>;
537 def : IntClampPat<V_SAD_U8, int_amdgcn_sad_u8>;
538 def : IntClampPat<V_SAD_HI_U8, int_amdgcn_sad_hi_u8>;
539 def : IntClampPat<V_SAD_U16, int_amdgcn_sad_u16>;
541 def : IntClampPat<V_MSAD_U8, int_amdgcn_msad_u8>;
542 def : IntClampPat<V_MQSAD_PK_U16_U8, int_amdgcn_mqsad_pk_u16_u8>;
544 def : IntClampPat<V_QSAD_PK_U16_U8, int_amdgcn_qsad_pk_u16_u8>;
545 def : IntClampPat<V_MQSAD_U32_U8, int_amdgcn_mqsad_u32_u8>;
547 //===----------------------------------------------------------------------===//
549 //===----------------------------------------------------------------------===//
551 //===----------------------------------------------------------------------===//
553 //===----------------------------------------------------------------------===//
555 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
557 multiclass VOP3_Real_si<bits<9> op> {
558 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
559 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
562 multiclass VOP3be_Real_si<bits<9> op> {
563 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
564 VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
567 } // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
569 defm V_MAD_LEGACY_F32 : VOP3_Real_si <0x140>;
570 defm V_MAD_F32 : VOP3_Real_si <0x141>;
571 defm V_MAD_I32_I24 : VOP3_Real_si <0x142>;
572 defm V_MAD_U32_U24 : VOP3_Real_si <0x143>;
573 defm V_CUBEID_F32 : VOP3_Real_si <0x144>;
574 defm V_CUBESC_F32 : VOP3_Real_si <0x145>;
575 defm V_CUBETC_F32 : VOP3_Real_si <0x146>;
576 defm V_CUBEMA_F32 : VOP3_Real_si <0x147>;
577 defm V_BFE_U32 : VOP3_Real_si <0x148>;
578 defm V_BFE_I32 : VOP3_Real_si <0x149>;
579 defm V_BFI_B32 : VOP3_Real_si <0x14a>;
580 defm V_FMA_F32 : VOP3_Real_si <0x14b>;
581 defm V_FMA_F64 : VOP3_Real_si <0x14c>;
582 defm V_LERP_U8 : VOP3_Real_si <0x14d>;
583 defm V_ALIGNBIT_B32 : VOP3_Real_si <0x14e>;
584 defm V_ALIGNBYTE_B32 : VOP3_Real_si <0x14f>;
585 defm V_MULLIT_F32 : VOP3_Real_si <0x150>;
586 defm V_MIN3_F32 : VOP3_Real_si <0x151>;
587 defm V_MIN3_I32 : VOP3_Real_si <0x152>;
588 defm V_MIN3_U32 : VOP3_Real_si <0x153>;
589 defm V_MAX3_F32 : VOP3_Real_si <0x154>;
590 defm V_MAX3_I32 : VOP3_Real_si <0x155>;
591 defm V_MAX3_U32 : VOP3_Real_si <0x156>;
592 defm V_MED3_F32 : VOP3_Real_si <0x157>;
593 defm V_MED3_I32 : VOP3_Real_si <0x158>;
594 defm V_MED3_U32 : VOP3_Real_si <0x159>;
595 defm V_SAD_U8 : VOP3_Real_si <0x15a>;
596 defm V_SAD_HI_U8 : VOP3_Real_si <0x15b>;
597 defm V_SAD_U16 : VOP3_Real_si <0x15c>;
598 defm V_SAD_U32 : VOP3_Real_si <0x15d>;
599 defm V_CVT_PK_U8_F32 : VOP3_Real_si <0x15e>;
600 defm V_DIV_FIXUP_F32 : VOP3_Real_si <0x15f>;
601 defm V_DIV_FIXUP_F64 : VOP3_Real_si <0x160>;
602 defm V_LSHL_B64 : VOP3_Real_si <0x161>;
603 defm V_LSHR_B64 : VOP3_Real_si <0x162>;
604 defm V_ASHR_I64 : VOP3_Real_si <0x163>;
605 defm V_ADD_F64 : VOP3_Real_si <0x164>;
606 defm V_MUL_F64 : VOP3_Real_si <0x165>;
607 defm V_MIN_F64 : VOP3_Real_si <0x166>;
608 defm V_MAX_F64 : VOP3_Real_si <0x167>;
609 defm V_LDEXP_F64 : VOP3_Real_si <0x168>;
610 defm V_MUL_LO_U32 : VOP3_Real_si <0x169>;
611 defm V_MUL_HI_U32 : VOP3_Real_si <0x16a>;
612 defm V_MUL_LO_I32 : VOP3_Real_si <0x16b>;
613 defm V_MUL_HI_I32 : VOP3_Real_si <0x16c>;
614 defm V_DIV_SCALE_F32 : VOP3be_Real_si <0x16d>;
615 defm V_DIV_SCALE_F64 : VOP3be_Real_si <0x16e>;
616 defm V_DIV_FMAS_F32 : VOP3_Real_si <0x16f>;
617 defm V_DIV_FMAS_F64 : VOP3_Real_si <0x170>;
618 defm V_MSAD_U8 : VOP3_Real_si <0x171>;
619 defm V_MQSAD_PK_U16_U8 : VOP3_Real_si <0x173>;
620 defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>;
622 //===----------------------------------------------------------------------===//
624 //===----------------------------------------------------------------------===//
626 multiclass VOP3_Real_ci<bits<9> op> {
627 def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
628 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
629 let AssemblerPredicates = [isCIOnly];
630 let DecoderNamespace = "CI";
634 multiclass VOP3be_Real_ci<bits<9> op> {
635 def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
636 VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
637 let AssemblerPredicates = [isCIOnly];
638 let DecoderNamespace = "CI";
642 defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>;
643 defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x175>;
644 defm V_MAD_U64_U32 : VOP3be_Real_ci <0x176>;
645 defm V_MAD_I64_I32 : VOP3be_Real_ci <0x177>;
647 //===----------------------------------------------------------------------===//
649 //===----------------------------------------------------------------------===//
651 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
653 multiclass VOP3_Real_vi<bits<10> op> {
654 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
655 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
658 multiclass VOP3be_Real_vi<bits<10> op> {
659 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
660 VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
663 multiclass VOP3OpSel_Real_gfx9<bits<10> op> {
664 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
665 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
668 multiclass VOP3Interp_Real_vi<bits<10> op> {
669 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
670 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
673 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
675 let AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI" in {
677 multiclass VOP3_F16_Real_vi<bits<10> op> {
678 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
679 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
682 multiclass VOP3Interp_F16_Real_vi<bits<10> op> {
683 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
684 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
687 } // End AssemblerPredicates = [isVIOnly], DecoderNamespace = "VI"
689 let AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9" in {
691 multiclass VOP3_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
692 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
693 VOP3e_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
694 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
695 let AsmString = AsmName # ps.AsmOperands;
699 multiclass VOP3OpSel_F16_Real_gfx9<bits<10> op, string AsmName> {
700 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX9>,
701 VOP3OpSel_gfx9 <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
702 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(NAME);
703 let AsmString = AsmName # ps.AsmOperands;
707 multiclass VOP3Interp_F16_Real_gfx9<bits<10> op, string OpName, string AsmName> {
708 def _gfx9 : VOP3_Real<!cast<VOP3_Pseudo>(OpName), SIEncodingFamily.GFX9>,
709 VOP3Interp_vi <op, !cast<VOP3_Pseudo>(OpName).Pfl> {
710 VOP3_Pseudo ps = !cast<VOP3_Pseudo>(OpName);
711 let AsmString = AsmName # ps.AsmOperands;
715 multiclass VOP3_Real_gfx9<bits<10> op, string AsmName> {
716 def _gfx9 : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX9>,
717 VOP3e_vi <op, !cast<VOP_Pseudo>(NAME).Pfl> {
718 VOP_Pseudo ps = !cast<VOP_Pseudo>(NAME);
719 let AsmString = AsmName # ps.AsmOperands;
723 } // End AssemblerPredicates = [isGFX9], DecoderNamespace = "GFX9"
725 defm V_MAD_U64_U32 : VOP3be_Real_vi <0x1E8>;
726 defm V_MAD_I64_I32 : VOP3be_Real_vi <0x1E9>;
728 defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>;
729 defm V_MAD_F32 : VOP3_Real_vi <0x1c1>;
730 defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>;
731 defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>;
732 defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>;
733 defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>;
734 defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>;
735 defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>;
736 defm V_BFE_U32 : VOP3_Real_vi <0x1c8>;
737 defm V_BFE_I32 : VOP3_Real_vi <0x1c9>;
738 defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
739 defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
740 defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
741 defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
742 defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
743 defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
744 defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
745 defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
746 defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
747 defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>;
748 defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>;
749 defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>;
750 defm V_MED3_F32 : VOP3_Real_vi <0x1d6>;
751 defm V_MED3_I32 : VOP3_Real_vi <0x1d7>;
752 defm V_MED3_U32 : VOP3_Real_vi <0x1d8>;
753 defm V_SAD_U8 : VOP3_Real_vi <0x1d9>;
754 defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>;
755 defm V_SAD_U16 : VOP3_Real_vi <0x1db>;
756 defm V_SAD_U32 : VOP3_Real_vi <0x1dc>;
757 defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>;
758 defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>;
759 defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>;
760 defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>;
761 defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>;
762 defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>;
763 defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>;
764 defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>;
765 defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
766 defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
767 defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
769 defm V_PERM_B32 : VOP3_Real_vi <0x1ed>;
771 defm V_MAD_F16 : VOP3_F16_Real_vi <0x1ea>;
772 defm V_MAD_U16 : VOP3_F16_Real_vi <0x1eb>;
773 defm V_MAD_I16 : VOP3_F16_Real_vi <0x1ec>;
774 defm V_FMA_F16 : VOP3_F16_Real_vi <0x1ee>;
775 defm V_DIV_FIXUP_F16 : VOP3_F16_Real_vi <0x1ef>;
776 defm V_INTERP_P2_F16 : VOP3Interp_F16_Real_vi <0x276>;
778 defm V_MAD_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ea, "V_MAD_F16", "v_mad_legacy_f16">;
779 defm V_MAD_LEGACY_U16 : VOP3_F16_Real_gfx9 <0x1eb, "V_MAD_U16", "v_mad_legacy_u16">;
780 defm V_MAD_LEGACY_I16 : VOP3_F16_Real_gfx9 <0x1ec, "V_MAD_I16", "v_mad_legacy_i16">;
781 defm V_FMA_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ee, "V_FMA_F16", "v_fma_legacy_f16">;
782 defm V_DIV_FIXUP_LEGACY_F16 : VOP3_F16_Real_gfx9 <0x1ef, "V_DIV_FIXUP_F16", "v_div_fixup_legacy_f16">;
783 defm V_INTERP_P2_LEGACY_F16 : VOP3Interp_F16_Real_gfx9 <0x276, "V_INTERP_P2_F16", "v_interp_p2_legacy_f16">;
785 defm V_MAD_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x203, "v_mad_f16">;
786 defm V_MAD_U16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x204, "v_mad_u16">;
787 defm V_MAD_I16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x205, "v_mad_i16">;
788 defm V_FMA_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x206, "v_fma_f16">;
789 defm V_DIV_FIXUP_F16_gfx9 : VOP3OpSel_F16_Real_gfx9 <0x207, "v_div_fixup_f16">;
790 defm V_INTERP_P2_F16_gfx9 : VOP3Interp_F16_Real_gfx9 <0x277, "V_INTERP_P2_F16_gfx9", "v_interp_p2_f16">;
792 defm V_ADD_I32_gfx9 : VOP3_Real_gfx9 <0x29c, "v_add_i32">;
793 defm V_SUB_I32_gfx9 : VOP3_Real_gfx9 <0x29d, "v_sub_i32">;
795 defm V_INTERP_P1_F32_e64 : VOP3Interp_Real_vi <0x270>;
796 defm V_INTERP_P2_F32_e64 : VOP3Interp_Real_vi <0x271>;
797 defm V_INTERP_MOV_F32_e64 : VOP3Interp_Real_vi <0x272>;
799 defm V_INTERP_P1LL_F16 : VOP3Interp_Real_vi <0x274>;
800 defm V_INTERP_P1LV_F16 : VOP3Interp_Real_vi <0x275>;
801 defm V_ADD_F64 : VOP3_Real_vi <0x280>;
802 defm V_MUL_F64 : VOP3_Real_vi <0x281>;
803 defm V_MIN_F64 : VOP3_Real_vi <0x282>;
804 defm V_MAX_F64 : VOP3_Real_vi <0x283>;
805 defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
806 defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
808 // removed from VI as identical to V_MUL_LO_U32
809 let isAsmParserOnly = 1 in {
810 defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>;
813 defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
814 defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
816 defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
817 defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
818 defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
819 defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>;
821 defm V_LSHL_ADD_U32 : VOP3_Real_vi <0x1fd>;
822 defm V_ADD_LSHL_U32 : VOP3_Real_vi <0x1fe>;
823 defm V_ADD3_U32 : VOP3_Real_vi <0x1ff>;
824 defm V_LSHL_OR_B32 : VOP3_Real_vi <0x200>;
825 defm V_AND_OR_B32 : VOP3_Real_vi <0x201>;
826 defm V_OR3_B32 : VOP3_Real_vi <0x202>;
827 defm V_PACK_B32_F16 : VOP3OpSel_Real_gfx9 <0x2a0>;
829 defm V_XAD_U32 : VOP3_Real_vi <0x1f3>;
831 defm V_MIN3_F16 : VOP3OpSel_Real_gfx9 <0x1f4>;
832 defm V_MIN3_I16 : VOP3OpSel_Real_gfx9 <0x1f5>;
833 defm V_MIN3_U16 : VOP3OpSel_Real_gfx9 <0x1f6>;
835 defm V_MAX3_F16 : VOP3OpSel_Real_gfx9 <0x1f7>;
836 defm V_MAX3_I16 : VOP3OpSel_Real_gfx9 <0x1f8>;
837 defm V_MAX3_U16 : VOP3OpSel_Real_gfx9 <0x1f9>;
839 defm V_MED3_F16 : VOP3OpSel_Real_gfx9 <0x1fa>;
840 defm V_MED3_I16 : VOP3OpSel_Real_gfx9 <0x1fb>;
841 defm V_MED3_U16 : VOP3OpSel_Real_gfx9 <0x1fc>;
843 defm V_ADD_I16 : VOP3OpSel_Real_gfx9 <0x29e>;
844 defm V_SUB_I16 : VOP3OpSel_Real_gfx9 <0x29f>;
846 defm V_MAD_U32_U16 : VOP3OpSel_Real_gfx9 <0x1f1>;
847 defm V_MAD_I32_I16 : VOP3OpSel_Real_gfx9 <0x1f2>;
849 defm V_CVT_PKNORM_I16_F16 : VOP3OpSel_Real_gfx9 <0x299>;
850 defm V_CVT_PKNORM_U16_F16 : VOP3OpSel_Real_gfx9 <0x29a>;