1 //===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
15 list<dag> ret3 = [(set P.DstVT:$vdst,
16 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
17 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
18 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
20 list<dag> ret2 = [(set P.DstVT:$vdst,
21 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
22 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
24 list<dag> ret1 = [(set P.DstVT:$vdst,
25 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))];
27 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
28 !if(!eq(P.NumSrcArgs, 2), ret2,
32 class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
33 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
34 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
35 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
36 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
37 !if(!eq(P.NumSrcArgs, 2), ret2,
41 class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
42 VOP3_Pseudo<OpName, P,
43 !if(P.HasModifiers, getVOP3ModPat<P, node>.ret, getVOP3Pat<P, node>.ret),
46 // Special case for v_div_fmas_{f32|f64}, since it seems to be the
47 // only VOP instruction that implicitly reads VCC.
48 let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
49 def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
50 let Outs64 = (outs DstRC.RegClass:$vdst);
52 def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
53 let Outs64 = (outs DstRC.RegClass:$vdst);
57 class getVOP3VCC<VOPProfile P, SDPatternOperator node> {
60 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
61 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
62 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
66 class VOP3_Profile<VOPProfile P> : VOPProfile<P.ArgVT> {
67 // FIXME: Hack to stop printing _e64
68 let Outs64 = (outs DstRC.RegClass:$vdst);
69 let Asm64 = " " # P.Asm64;
72 class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
73 // v_div_scale_{f32|f64} do not support input modifiers.
75 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
76 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
79 def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
80 // FIXME: Hack to stop printing _e64
81 let DstRC = RegisterOperand<VGPR_32>;
84 def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
85 // FIXME: Hack to stop printing _e64
86 let DstRC = RegisterOperand<VReg_64>;
89 //===----------------------------------------------------------------------===//
91 //===----------------------------------------------------------------------===//
93 let isCommutable = 1 in {
95 def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
96 def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
97 def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_i24>;
98 def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_u24>;
99 def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
100 def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
101 def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
103 let SchedRW = [WriteDoubleAdd] in {
104 def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
105 def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
106 def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum, 1>;
107 def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum, 1>;
108 } // End SchedRW = [WriteDoubleAdd]
110 let SchedRW = [WriteQuarterRate32] in {
111 def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>>;
112 def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
113 def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
114 def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
115 } // End SchedRW = [WriteQuarterRate32]
117 let Uses = [VCC, EXEC] in {
119 // result = src0 * src1 + src2
123 def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC,
124 getVOP3VCC<VOP_F32_F32_F32_F32_VCC, AMDGPUdiv_fmas>.ret> {
125 let SchedRW = [WriteFloatFMA];
128 // result = src0 * src1 + src2
132 def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC,
133 getVOP3VCC<VOP_F64_F64_F64_F64_VCC, AMDGPUdiv_fmas>.ret> {
134 let SchedRW = [WriteDouble];
136 } // End Uses = [VCC, EXEC]
138 } // End isCommutable = 1
140 def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
141 def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
142 def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
143 def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
144 def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
145 def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
146 def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
147 def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
148 def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
149 def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
150 def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
151 def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
152 def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
153 def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
154 def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
155 def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
156 def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
157 def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
158 def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u8>;
159 def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_hi_u8>;
160 def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u16>;
161 def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
162 def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
163 def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
165 let SchedRW = [WriteDoubleAdd] in {
166 def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
167 def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
168 } // End SchedRW = [WriteDoubleAdd]
170 def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
171 let SchedRW = [WriteFloatFMA, WriteSALU];
172 let hasExtraSrcRegAllocReq = 1;
173 let AsmMatchConverter = "";
176 // Double precision division pre-scale.
177 def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
178 let SchedRW = [WriteDouble, WriteSALU];
179 let hasExtraSrcRegAllocReq = 1;
180 let AsmMatchConverter = "";
183 def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_msad_u8>;
184 def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_mqsad_pk_u16_u8>;
186 def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
187 let SchedRW = [WriteDouble];
190 // These instructions only exist on SI and CI
191 let SubtargetPredicate = isSICI in {
192 def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>;
193 def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>;
194 def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>;
195 def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
196 } // End SubtargetPredicate = isSICI
198 let SubtargetPredicate = isVI in {
199 def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
200 def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
201 def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
202 } // End SubtargetPredicate = isVI
205 let SubtargetPredicate = isCIVI in {
207 def V_MQSAD_U16_U8 : VOP3Inst <"v_mqsad_u16_u8", VOP3_Profile<VOP_I32_I32_I32>>;
208 def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_qsad_pk_u16_u8>;
209 def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32>, int_amdgcn_mqsad_u32_u8>;
211 let isCommutable = 1 in {
212 def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3_Profile<VOP_I64_I32_I32_I64>>;
214 // XXX - Does this set VCC?
215 def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3_Profile<VOP_I64_I32_I32_I64>>;
216 } // End isCommutable = 1
218 } // End SubtargetPredicate = isCIVI
221 let SubtargetPredicate = isVI in {
223 let isCommutable = 1 in {
225 def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
226 def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
227 def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>;
228 def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>;
229 def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>;
230 def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
232 def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
233 def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
235 } // End isCommutable = 1
237 } // End SubtargetPredicate = isVI
239 let Predicates = [isVI] in {
241 multiclass Tenary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
242 Instruction inst, SDPatternOperator op3> {
244 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
245 (inst i16:$src0, i16:$src1, i16:$src2)
249 (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
250 (inst i16:$src0, i16:$src1, i16:$src2)
254 (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
255 (REG_SEQUENCE VReg_64,
256 (inst i16:$src0, i16:$src1, i16:$src2), sub0,
257 (V_MOV_B32_e32 (i32 0)), sub1)
261 defm: Tenary_i16_Pats<mul, add, V_MAD_U16, zext>;
262 defm: Tenary_i16_Pats<mul, add, V_MAD_I16, sext>;
264 } // End Predicates = [isVI]
267 //===----------------------------------------------------------------------===//
269 //===----------------------------------------------------------------------===//
271 //===----------------------------------------------------------------------===//
273 //===----------------------------------------------------------------------===//
275 let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
277 multiclass VOP3_Real_si<bits<9> op> {
278 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
279 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
282 multiclass VOP3be_Real_si<bits<9> op> {
283 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
284 VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
287 } // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
289 defm V_MAD_LEGACY_F32 : VOP3_Real_si <0x140>;
290 defm V_MAD_F32 : VOP3_Real_si <0x141>;
291 defm V_MAD_I32_I24 : VOP3_Real_si <0x142>;
292 defm V_MAD_U32_U24 : VOP3_Real_si <0x143>;
293 defm V_CUBEID_F32 : VOP3_Real_si <0x144>;
294 defm V_CUBESC_F32 : VOP3_Real_si <0x145>;
295 defm V_CUBETC_F32 : VOP3_Real_si <0x146>;
296 defm V_CUBEMA_F32 : VOP3_Real_si <0x147>;
297 defm V_BFE_U32 : VOP3_Real_si <0x148>;
298 defm V_BFE_I32 : VOP3_Real_si <0x149>;
299 defm V_BFI_B32 : VOP3_Real_si <0x14a>;
300 defm V_FMA_F32 : VOP3_Real_si <0x14b>;
301 defm V_FMA_F64 : VOP3_Real_si <0x14c>;
302 defm V_LERP_U8 : VOP3_Real_si <0x14d>;
303 defm V_ALIGNBIT_B32 : VOP3_Real_si <0x14e>;
304 defm V_ALIGNBYTE_B32 : VOP3_Real_si <0x14f>;
305 defm V_MULLIT_F32 : VOP3_Real_si <0x150>;
306 defm V_MIN3_F32 : VOP3_Real_si <0x151>;
307 defm V_MIN3_I32 : VOP3_Real_si <0x152>;
308 defm V_MIN3_U32 : VOP3_Real_si <0x153>;
309 defm V_MAX3_F32 : VOP3_Real_si <0x154>;
310 defm V_MAX3_I32 : VOP3_Real_si <0x155>;
311 defm V_MAX3_U32 : VOP3_Real_si <0x156>;
312 defm V_MED3_F32 : VOP3_Real_si <0x157>;
313 defm V_MED3_I32 : VOP3_Real_si <0x158>;
314 defm V_MED3_U32 : VOP3_Real_si <0x159>;
315 defm V_SAD_U8 : VOP3_Real_si <0x15a>;
316 defm V_SAD_HI_U8 : VOP3_Real_si <0x15b>;
317 defm V_SAD_U16 : VOP3_Real_si <0x15c>;
318 defm V_SAD_U32 : VOP3_Real_si <0x15d>;
319 defm V_CVT_PK_U8_F32 : VOP3_Real_si <0x15e>;
320 defm V_DIV_FIXUP_F32 : VOP3_Real_si <0x15f>;
321 defm V_DIV_FIXUP_F64 : VOP3_Real_si <0x160>;
322 defm V_LSHL_B64 : VOP3_Real_si <0x161>;
323 defm V_LSHR_B64 : VOP3_Real_si <0x162>;
324 defm V_ASHR_I64 : VOP3_Real_si <0x163>;
325 defm V_ADD_F64 : VOP3_Real_si <0x164>;
326 defm V_MUL_F64 : VOP3_Real_si <0x165>;
327 defm V_MIN_F64 : VOP3_Real_si <0x166>;
328 defm V_MAX_F64 : VOP3_Real_si <0x167>;
329 defm V_LDEXP_F64 : VOP3_Real_si <0x168>;
330 defm V_MUL_LO_U32 : VOP3_Real_si <0x169>;
331 defm V_MUL_HI_U32 : VOP3_Real_si <0x16a>;
332 defm V_MUL_LO_I32 : VOP3_Real_si <0x16b>;
333 defm V_MUL_HI_I32 : VOP3_Real_si <0x16c>;
334 defm V_DIV_SCALE_F32 : VOP3be_Real_si <0x16d>;
335 defm V_DIV_SCALE_F64 : VOP3be_Real_si <0x16e>;
336 defm V_DIV_FMAS_F32 : VOP3_Real_si <0x16f>;
337 defm V_DIV_FMAS_F64 : VOP3_Real_si <0x170>;
338 defm V_MSAD_U8 : VOP3_Real_si <0x171>;
339 defm V_MQSAD_PK_U16_U8 : VOP3_Real_si <0x173>;
340 defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>;
342 //===----------------------------------------------------------------------===//
344 //===----------------------------------------------------------------------===//
346 multiclass VOP3_Real_ci<bits<9> op> {
347 def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
348 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
349 let AssemblerPredicates = [isCIOnly];
350 let DecoderNamespace = "CI";
354 defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>;
355 defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>;
356 defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x174>;
357 defm V_MAD_U64_U32 : VOP3_Real_ci <0x176>;
358 defm V_MAD_I64_I32 : VOP3_Real_ci <0x177>;
360 //===----------------------------------------------------------------------===//
362 //===----------------------------------------------------------------------===//
364 let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
366 multiclass VOP3_Real_vi<bits<10> op> {
367 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
368 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
371 multiclass VOP3be_Real_vi<bits<10> op> {
372 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
373 VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
376 } // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
378 defm V_MQSAD_U16_U8 : VOP3_Real_vi <0x172>;
379 defm V_MAD_U64_U32 : VOP3_Real_vi <0x176>;
380 defm V_MAD_I64_I32 : VOP3_Real_vi <0x177>;
382 defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>;
383 defm V_MAD_F32 : VOP3_Real_vi <0x1c1>;
384 defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>;
385 defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>;
386 defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>;
387 defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>;
388 defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>;
389 defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>;
390 defm V_BFE_U32 : VOP3_Real_vi <0x1c8>;
391 defm V_BFE_I32 : VOP3_Real_vi <0x1c9>;
392 defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
393 defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
394 defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
395 defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
396 defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
397 defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
398 defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
399 defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
400 defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
401 defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>;
402 defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>;
403 defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>;
404 defm V_MED3_F32 : VOP3_Real_vi <0x1d6>;
405 defm V_MED3_I32 : VOP3_Real_vi <0x1d7>;
406 defm V_MED3_U32 : VOP3_Real_vi <0x1d8>;
407 defm V_SAD_U8 : VOP3_Real_vi <0x1d9>;
408 defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>;
409 defm V_SAD_U16 : VOP3_Real_vi <0x1db>;
410 defm V_SAD_U32 : VOP3_Real_vi <0x1dc>;
411 defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>;
412 defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>;
413 defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>;
414 defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>;
415 defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>;
416 defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>;
417 defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>;
418 defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>;
419 defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
420 defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
421 defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
423 defm V_MAD_F16 : VOP3_Real_vi <0x1ea>;
424 defm V_MAD_U16 : VOP3_Real_vi <0x1eb>;
425 defm V_MAD_I16 : VOP3_Real_vi <0x1ec>;
427 defm V_FMA_F16 : VOP3_Real_vi <0x1ee>;
428 defm V_DIV_FIXUP_F16 : VOP3_Real_vi <0x1ef>;
430 defm V_INTERP_P1LL_F16 : VOP3_Real_vi <0x274>;
431 defm V_INTERP_P1LV_F16 : VOP3_Real_vi <0x275>;
432 defm V_INTERP_P2_F16 : VOP3_Real_vi <0x276>;
433 defm V_ADD_F64 : VOP3_Real_vi <0x280>;
434 defm V_MUL_F64 : VOP3_Real_vi <0x281>;
435 defm V_MIN_F64 : VOP3_Real_vi <0x282>;
436 defm V_MAX_F64 : VOP3_Real_vi <0x283>;
437 defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
438 defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
440 // removed from VI as identical to V_MUL_LO_U32
441 let isAsmParserOnly = 1 in {
442 defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>;
445 defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
446 defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
448 defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
449 defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
450 defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
451 defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>;