contrib/llvm/lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  24                                              "true", "Thumb mode">;
  25
  26 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  27                                              "true", "Use software floating "
  28                                              "point features.">;
  29
  30
  31 //===----------------------------------------------------------------------===//
  32 // ARM Subtarget features.
  33 //
  34
  35 // Floating Point, HW Division and Neon Support
  36 def FeatureVFP2           : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  37                                              "Enable VFP2 instructions">;
  38
  39 def FeatureVFP3           : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  40                                              "Enable VFP3 instructions",
  41                                              [FeatureVFP2]>;
  42
  43 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
  44                                              "Enable NEON instructions",
  45                                              [FeatureVFP3]>;
  46
  47 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
  48                                              "Enable half-precision "
  49                                              "floating point">;
  50
  51 def FeatureVFP4           : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  52                                              "Enable VFP4 instructions",
  53                                              [FeatureVFP3, FeatureFP16]>;
  54
  55 def FeatureFPARMv8        : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  56                                              "true", "Enable ARMv8 FP",
  57                                              [FeatureVFP4]>;
  58
  59 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  60                                              "Enable full half-precision "
  61                                              "floating point",
  62                                              [FeatureFPARMv8]>;
  63
  64 def FeatureVFPOnlySP      : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  65                                              "Floating point unit supports "
  66                                              "single precision only">;
  67
  68 def FeatureD16            : SubtargetFeature<"d16", "HasD16", "true",
  69                                              "Restrict FP to 16 double registers">;
  70
  71 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
  72                                              "HasHardwareDivideInThumb", "true",
  73                                              "Enable divide instructions in Thumb">;
  74
  75 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
  76                                              "HasHardwareDivideInARM", "true",
  77                                              "Enable divide instructions in ARM mode">;
  78
  79 // Atomic Support
  80 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
  81                                              "Has data barrier (dmb/dsb) instructions">;
  82
  83 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
  84                                              "Has v7 clrex instruction">;
  85
  86 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
  87                                    "Has full data barrier (dfb) instruction">;
  88
  89 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
  90                                              "HasAcquireRelease", "true",
  91                                              "Has v8 acquire/release (lda/ldaex "
  92                                              " etc) instructions">;
  93
  94
  95 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  96                                              "FP compare + branch is slow">;
  97
  98 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  99                                              "Enable support for Performance "
 100                                              "Monitor extensions">;
 101
 102
 103 // TrustZone Security Extensions
 104 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 105                                              "Enable support for TrustZone "
 106                                              "security extensions">;
 107
 108 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 109                                              "Enable support for ARMv8-M "
 110                                              "Security Extensions">;
 111
 112 def FeatureSHA2           : SubtargetFeature<"sha2", "HasSHA2", "true",
 113                                              "Enable SHA1 and SHA256 support", [FeatureNEON]>;
 114
 115 def FeatureAES            : SubtargetFeature<"aes", "HasAES", "true",
 116                                              "Enable AES support", [FeatureNEON]>;
 117
 118 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 119                                              "Enable support for "
 120                                              "Cryptography extensions",
 121                                              [FeatureNEON, FeatureSHA2, FeatureAES]>;
 122
 123 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 124                                              "Enable support for CRC instructions">;
 125
 126 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 127                                              "Enable support for dot product instructions",
 128                                              [FeatureNEON]>;
 129
 130 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 131 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 132                                              "Enable Reliability, Availability "
 133                                              "and Serviceability extensions">;
 134
 135 // Fast computation of non-negative address offsets
 136 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 137                                              "Enable fast computation of "
 138                                              "positive address offsets">;
 139
 140 // Fast execution of AES crypto operations
 141 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 142                                              "CPU fuses AES crypto operations">;
 143
 144 // Fast execution of bottom and top halves of literal generation
 145 def FeatureFuseLiterals   : SubtargetFeature<"fuse-literals", "HasFuseLiterals", "true",
 146                                              "CPU fuses literal generation operations">;
 147
 148 // The way of reading thread pointer
 149 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 150                                       "Reading thread pointer from register">;
 151
 152 // Cyclone can zero VFP registers in 0 cycles.
 153 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 154                                              "Has zero-cycle zeroing instructions">;
 155
 156 // Whether it is profitable to unpredicate certain instructions during if-conversion
 157 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 158                                               "IsProfitableToUnpredicate", "true",
 159                                               "Is profitable to unpredicate">;
 160
 161 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 162 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 163                                              "HasSlowVGETLNi32", "true",
 164                                              "Has slow VGETLNi32 - prefer VMOV">;
 165
 166 // Some targets (e.g. Swift) have microcoded VDUP32.
 167 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 168                                              "true",
 169                                              "Has slow VDUP32 - prefer VMOV">;
 170
 171 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 172 // for scalar FP, as this allows more effective execution domain optimization.
 173 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 174                                              "true", "Prefer VMOVSR">;
 175
 176 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 177 // than ISH
 178 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 179                                                "true", "Prefer ISHST barriers">;
 180
 181 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 182 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 183                                              "true",
 184                                              "Has muxed AGU and NEON/FPU">;
 185
 186 // Whether VLDM/VSTM starting with odd register number need more microops
 187 // than single VLDRS
 188 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 189                                               "true", "VLDM/VSTM starting "
 190                                               "with an odd register is slow">;
 191
 192 // Some targets have a renaming dependency when loading into D subregisters.
 193 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 194                                               "SlowLoadDSubregister", "true",
 195                                               "Loading into D subregs is slow">;
 196
 197 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 198 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 199                                              "DontWidenVMOVS", "true",
 200                                              "Don't widen VMOVS to VMOVD">;
 201
 202 // Some targets (e.g. Cortex-A15) prefer to avoid mixing operations on different
 203 // VFP register widths.
 204 def FeatureSplatVFPToNeon : SubtargetFeature<"splat-vfp-neon",
 205                                              "SplatVFPToNeon", "true",
 206                                              "Splat register from VFP to NEON",
 207                                              [FeatureDontWidenVMOVS]>;
 208
 209 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 210 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 211                                              "ExpandMLx", "true",
 212                                              "Expand VFP/NEON MLA/MLS instructions">;
 213
 214 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 215 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 216                                              "true", "Has VMLx hazards">;
 217
 218 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 219 // VFP to NEON, as an execution domain optimization.
 220 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 221                                              "UseNEONForFPMovs", "true",
 222                                              "Convert VMOVSR, VMOVRS, "
 223                                              "VMOVS to NEON">;
 224
 225 // Some processors benefit from using NEON instructions for scalar
 226 // single-precision FP operations. This affects instruction selection and should
 227 // only be enabled if the handling of denormals is not important.
 228 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 229                                              "UseNEONForSinglePrecisionFP",
 230                                              "true",
 231                                              "Use NEON for single precision FP">;
 232
 233 // On some processors, VLDn instructions that access unaligned data take one
 234 // extra cycle. Take that into account when computing operand latencies.
 235 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 236                                              "true",
 237                                              "Check for VLDn unaligned access">;
 238
 239 // Some processors have a nonpipelined VFP coprocessor.
 240 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 241                                               "NonpipelinedVFP", "true",
 242                                               "VFP instructions are not pipelined">;
 243
 244 // Some processors have FP multiply-accumulate instructions that don't
 245 // play nicely with other VFP / NEON instructions, and it's generally better
 246 // to just not use them.
 247 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 248                                              "Disable VFP / NEON MAC instructions">;
 249
 250 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 251 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 252                                              "HasVMLxForwarding", "true",
 253                                              "Has multiplier accumulator forwarding">;
 254
 255 // Disable 32-bit to 16-bit narrowing for experimentation.
 256 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 257                                              "Prefer 32-bit Thumb instrs">;
 258
 259 /// Some instructions update CPSR partially, which can add false dependency for
 260 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 261 /// mapped to a separate physical register. Avoid partial CPSR update for these
 262 /// processors.
 263 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 264                                                "AvoidCPSRPartialUpdate", "true",
 265                                  "Avoid CPSR partial update for OOO execution">;
 266
 267 /// Disable +1 predication cost for instructions updating CPSR.
 268 /// Enabled for Cortex-A57.
 269 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 270                                                   "CheapPredicableCPSRDef",
 271                                                   "true",
 272                   "Disable +1 predication cost for instructions updating CPSR">;
 273
 274 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 275                                              "AvoidMOVsShifterOperand", "true",
 276                                              "Avoid movs instructions with "
 277                                              "shifter operand">;
 278
 279 // Some processors perform return stack prediction. CodeGen should avoid issue
 280 // "normal" call instructions to callees which do not return.
 281 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 282                                               "HasRetAddrStack", "true",
 283                                               "Has return address stack">;
 284
 285 // Some processors have no branch predictor, which changes the expected cost of
 286 // taking a branch which affects the choice of whether to use predicated
 287 // instructions.
 288 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 289                                                    "HasBranchPredictor", "false",
 290                                                    "Has no branch predictor">;
 291
 292 /// DSP extension.
 293 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 294                                              "Supports DSP instructions in "
 295                                              "ARM and/or Thumb2">;
 296
 297 // Multiprocessing extension.
 298 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 299                                         "Supports Multiprocessing extension">;
 300
 301 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 302 def FeatureVirtualization : SubtargetFeature<"virtualization",
 303                                              "HasVirtualization", "true",
 304                                              "Supports Virtualization extension",
 305                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 306
 307 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 308 // See ARMInstrInfo.td for details.
 309 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 310                                              "NaCl trap">;
 311
 312 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 313                                              "StrictAlign", "true",
 314                                              "Disallow all unaligned memory "
 315                                              "access">;
 316
 317 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 318                                              "Generate calls via indirect call "
 319                                              "instructions">;
 320
 321 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 322                                              "GenExecuteOnly", "true",
 323                                              "Enable the generation of "
 324                                              "execute only code.">;
 325
 326 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 327                                              "Reserve R9, making it unavailable"
 328                                              " as GPR">;
 329
 330 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 331                                              "Don't use movt/movw pairs for "
 332                                              "32-bit imms">;
 333
 334 def FeatureNoNegativeImmediates
 335                           : SubtargetFeature<"no-neg-immediates",
 336                                              "NegativeImmediates", "false",
 337                                              "Convert immediates and instructions "
 338                                              "to their negated or complemented "
 339                                              "equivalent when the immediate does "
 340                                              "not fit in the encoding.">;
 341
 342 // Use the MachineScheduler for instruction scheduling for the subtarget.
 343 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 344                                         "Use the MachineScheduler">;
 345
 346 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 347     "DisablePostRAScheduler", "true",
 348     "Don't schedule again after register allocation">;
 349
 350 // Enable use of alias analysis during code generation
 351 def FeatureUseAA : SubtargetFeature<"use-aa", "UseAA", "true",
 352                                     "Use alias analysis during codegen">;
 353
 354 //===----------------------------------------------------------------------===//
 355 // ARM architecture class
 356 //
 357
 358 // A-series ISA
 359 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 360                                      "Is application profile ('A' series)">;
 361
 362 // R-series ISA
 363 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 364                                      "Is realtime profile ('R' series)">;
 365
 366 // M-series ISA
 367 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 368                                      "Is microcontroller profile ('M' series)">;
 369
 370
 371 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 372                                      "Enable Thumb2 instructions">;
 373
 374 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 375                                      "Does not support ARM mode execution">;
 376
 377 //===----------------------------------------------------------------------===//
 378 // ARM ISAa.
 379 //
 380
 381 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 382                                    "Support ARM v4T instructions">;
 383
 384 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 385                                    "Support ARM v5T instructions",
 386                                    [HasV4TOps]>;
 387
 388 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 389                                    "Support ARM v5TE, v5TEj, and "
 390                                    "v5TExp instructions",
 391                                    [HasV5TOps]>;
 392
 393 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 394                                    "Support ARM v6 instructions",
 395                                    [HasV5TEOps]>;
 396
 397 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 398                                    "Support ARM v6M instructions",
 399                                    [HasV6Ops]>;
 400
 401 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 402                                          "Support ARM v8M Baseline instructions",
 403                                          [HasV6MOps]>;
 404
 405 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 406                                    "Support ARM v6k instructions",
 407                                    [HasV6Ops]>;
 408
 409 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 410                                    "Support ARM v6t2 instructions",
 411                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 412
 413 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 414                                    "Support ARM v7 instructions",
 415                                    [HasV6T2Ops, FeaturePerfMon,
 416                                     FeatureV7Clrex]>;
 417
 418 def HasV8MMainlineOps :
 419                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 420                                    "Support ARM v8M Mainline instructions",
 421                                    [HasV7Ops]>;
 422
 423 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 424                                    "Support ARM v8 instructions",
 425                                    [HasV7Ops, FeatureAcquireRelease]>;
 426
 427 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 428                                    "Support ARM v8.1a instructions",
 429                                    [HasV8Ops]>;
 430
 431 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 432                                    "Support ARM v8.2a instructions",
 433                                    [HasV8_1aOps]>;
 434
 435 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 436                                    "Support ARM v8.3a instructions",
 437                                    [HasV8_2aOps]>;
 438
 439 def HasV8_4aOps   : SubtargetFeature<"v8.4a", "HasV8_4aOps", "true",
 440                                    "Support ARM v8.4a instructions",
 441                                    [HasV8_3aOps, FeatureDotProd]>;
 442
 443 //===----------------------------------------------------------------------===//
 444 // ARM Processor subtarget features.
 445 //
 446
 447 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 448                                    "Cortex-A5 ARM processors", []>;
 449 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 450                                    "Cortex-A7 ARM processors", []>;
 451 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 452                                    "Cortex-A8 ARM processors", []>;
 453 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 454                                    "Cortex-A9 ARM processors", []>;
 455 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 456                                    "Cortex-A12 ARM processors", []>;
 457 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 458                                    "Cortex-A15 ARM processors", []>;
 459 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 460                                    "Cortex-A17 ARM processors", []>;
 461 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 462                                    "Cortex-A32 ARM processors", []>;
 463 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 464                                    "Cortex-A35 ARM processors", []>;
 465 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 466                                    "Cortex-A53 ARM processors", []>;
 467 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 468                                    "Cortex-A55 ARM processors", []>;
 469 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 470                                    "Cortex-A57 ARM processors", []>;
 471 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 472                                    "Cortex-A72 ARM processors", []>;
 473 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 474                                    "Cortex-A73 ARM processors", []>;
 475 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 476                                    "Cortex-A75 ARM processors", []>;
 477
 478 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 479                                    "Qualcomm Krait processors", []>;
 480 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 481                                    "Qualcomm Kryo processors", []>;
 482 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 483                                    "Swift ARM processors", []>;
 484
 485 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 486                                     "Samsung Exynos-Mx processors", []>;
 487
 488 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 489                                    "Cortex-R4 ARM processors", []>;
 490 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 491                                    "Cortex-R5 ARM processors", []>;
 492 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 493                                    "Cortex-R7 ARM processors", []>;
 494 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 495                                    "Cortex-R52 ARM processors", []>;
 496
 497 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 498                                    "Cortex-M3 ARM processors", []>;
 499
 500
 501 //===----------------------------------------------------------------------===//
 502 // ARM Helper classes.
 503 //
 504
 505 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 506   : SubtargetFeature<fname, "ARMArch", aname,
 507                      !strconcat(aname, " architecture"), features>;
 508
 509 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 510   : Processor<Name, NoItineraries, Features>;
 511
 512
 513 //===----------------------------------------------------------------------===//
 514 // ARM architectures
 515 //
 516
 517 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 518
 519 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 520
 521 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 522
 523 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 524
 525 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 526
 527 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 528
 529 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 530
 531 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 532
 533 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 534
 535 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops,
 536                                                        FeatureDSP]>;
 537
 538 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 539                                                        FeatureDSP]>;
 540
 541 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 542
 543 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 544                                                        FeatureTrustZone]>;
 545
 546 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 547                                                        FeatureNoARM,
 548                                                        ModeThumb,
 549                                                        FeatureDB,
 550                                                        FeatureMClass,
 551                                                        FeatureStrictAlign]>;
 552
 553 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 554                                                        FeatureNoARM,
 555                                                        ModeThumb,
 556                                                        FeatureDB,
 557                                                        FeatureMClass,
 558                                                        FeatureStrictAlign]>;
 559
 560 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 561                                                        FeatureNEON,
 562                                                        FeatureDB,
 563                                                        FeatureDSP,
 564                                                        FeatureAClass]>;
 565
 566 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 567                                                        FeatureNEON,
 568                                                        FeatureDB,
 569                                                        FeatureDSP,
 570                                                        FeatureTrustZone,
 571                                                        FeatureMP,
 572                                                        FeatureVirtualization,
 573                                                        FeatureAClass]>;
 574
 575 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 576                                                        FeatureDB,
 577                                                        FeatureDSP,
 578                                                        FeatureHWDivThumb,
 579                                                        FeatureRClass]>;
 580
 581 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 582                                                        FeatureThumb2,
 583                                                        FeatureNoARM,
 584                                                        ModeThumb,
 585                                                        FeatureDB,
 586                                                        FeatureHWDivThumb,
 587                                                        FeatureMClass]>;
 588
 589 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 590                                                        FeatureThumb2,
 591                                                        FeatureNoARM,
 592                                                        ModeThumb,
 593                                                        FeatureDB,
 594                                                        FeatureHWDivThumb,
 595                                                        FeatureMClass,
 596                                                        FeatureDSP]>;
 597
 598 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 599                                                        FeatureAClass,
 600                                                        FeatureDB,
 601                                                        FeatureFPARMv8,
 602                                                        FeatureNEON,
 603                                                        FeatureDSP,
 604                                                        FeatureTrustZone,
 605                                                        FeatureMP,
 606                                                        FeatureVirtualization,
 607                                                        FeatureCrypto,
 608                                                        FeatureCRC]>;
 609
 610 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 611                                                        FeatureAClass,
 612                                                        FeatureDB,
 613                                                        FeatureFPARMv8,
 614                                                        FeatureNEON,
 615                                                        FeatureDSP,
 616                                                        FeatureTrustZone,
 617                                                        FeatureMP,
 618                                                        FeatureVirtualization,
 619                                                        FeatureCrypto,
 620                                                        FeatureCRC]>;
 621
 622 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 623                                                        FeatureAClass,
 624                                                        FeatureDB,
 625                                                        FeatureFPARMv8,
 626                                                        FeatureNEON,
 627                                                        FeatureDSP,
 628                                                        FeatureTrustZone,
 629                                                        FeatureMP,
 630                                                        FeatureVirtualization,
 631                                                        FeatureCrypto,
 632                                                        FeatureCRC,
 633                                                        FeatureRAS]>;
 634
 635 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 636                                                        FeatureAClass,
 637                                                        FeatureDB,
 638                                                        FeatureFPARMv8,
 639                                                        FeatureNEON,
 640                                                        FeatureDSP,
 641                                                        FeatureTrustZone,
 642                                                        FeatureMP,
 643                                                        FeatureVirtualization,
 644                                                        FeatureCrypto,
 645                                                        FeatureCRC,
 646                                                        FeatureRAS]>;
 647
 648 def ARMv84a   : Architecture<"armv8.4-a", "ARMv84a",  [HasV8_4aOps,
 649                                                        FeatureAClass,
 650                                                        FeatureDB,
 651                                                        FeatureFPARMv8,
 652                                                        FeatureNEON,
 653                                                        FeatureDSP,
 654                                                        FeatureTrustZone,
 655                                                        FeatureMP,
 656                                                        FeatureVirtualization,
 657                                                        FeatureCrypto,
 658                                                        FeatureCRC,
 659                                                        FeatureRAS,
 660                                                        FeatureDotProd]>;
 661
 662 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 663                                                        FeatureRClass,
 664                                                        FeatureDB,
 665                                                        FeatureDFB,
 666                                                        FeatureDSP,
 667                                                        FeatureCRC,
 668                                                        FeatureMP,
 669                                                        FeatureVirtualization,
 670                                                        FeatureFPARMv8,
 671                                                        FeatureNEON]>;
 672
 673 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 674                                                       [HasV8MBaselineOps,
 675                                                        FeatureNoARM,
 676                                                        ModeThumb,
 677                                                        FeatureDB,
 678                                                        FeatureHWDivThumb,
 679                                                        FeatureV7Clrex,
 680                                                        Feature8MSecExt,
 681                                                        FeatureAcquireRelease,
 682                                                        FeatureMClass,
 683                                                        FeatureStrictAlign]>;
 684
 685 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 686                                                       [HasV8MMainlineOps,
 687                                                        FeatureNoARM,
 688                                                        ModeThumb,
 689                                                        FeatureDB,
 690                                                        FeatureHWDivThumb,
 691                                                        Feature8MSecExt,
 692                                                        FeatureAcquireRelease,
 693                                                        FeatureMClass]>;
 694
 695 // Aliases
 696 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 697 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 698 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 699 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 700 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 701 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 702
 703
 704 //===----------------------------------------------------------------------===//
 705 // ARM schedules.
 706 //===----------------------------------------------------------------------===//
 707 //
 708 include "ARMSchedule.td"
 709
 710 //===----------------------------------------------------------------------===//
 711 // ARM processors
 712 //
 713
 714 // Dummy CPU, used to target architectures
 715 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 716
 717 // FIXME: Several processors below are not using their own scheduler
 718 // model, but one of similar/previous processor. These should be fixed.
 719
 720 def : ProcNoItin<"arm8",                                [ARMv4]>;
 721 def : ProcNoItin<"arm810",                              [ARMv4]>;
 722 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 723 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 724 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 725 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 726
 727 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 728 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 729 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 730 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 731 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 732 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 733 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 734 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 735 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 736 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 737 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 738
 739 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 740 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 741
 742 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 743 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 744 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 745 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 746 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 747 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 748 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 749 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 750 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 751 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 752
 753 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 754 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 755                                                          FeatureVFP2,
 756                                                          FeatureHasSlowFPVMLx]>;
 757
 758 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 759 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 760 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 761 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 762
 763 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 764 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 765 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 766                                                          FeatureVFP2,
 767                                                          FeatureHasSlowFPVMLx]>;
 768
 769 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 770 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 771                                                          FeatureVFP2,
 772                                                          FeatureHasSlowFPVMLx]>;
 773
 774 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 775 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 776                                                          FeatureVFP2,
 777                                                          FeatureHasSlowFPVMLx]>;
 778
 779 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 780                                                          FeatureHasRetAddrStack,
 781                                                          FeatureTrustZone,
 782                                                          FeatureSlowFPBrcc,
 783                                                          FeatureHasSlowFPVMLx,
 784                                                          FeatureVMLxForwarding,
 785                                                          FeatureMP,
 786                                                          FeatureVFP4]>;
 787
 788 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 789                                                          FeatureHasRetAddrStack,
 790                                                          FeatureTrustZone,
 791                                                          FeatureSlowFPBrcc,
 792                                                          FeatureHasVMLxHazards,
 793                                                          FeatureHasSlowFPVMLx,
 794                                                          FeatureVMLxForwarding,
 795                                                          FeatureMP,
 796                                                          FeatureVFP4,
 797                                                          FeatureVirtualization]>;
 798
 799 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 800                                                          FeatureHasRetAddrStack,
 801                                                          FeatureNonpipelinedVFP,
 802                                                          FeatureTrustZone,
 803                                                          FeatureSlowFPBrcc,
 804                                                          FeatureHasVMLxHazards,
 805                                                          FeatureHasSlowFPVMLx,
 806                                                          FeatureVMLxForwarding]>;
 807
 808 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 809                                                          FeatureHasRetAddrStack,
 810                                                          FeatureTrustZone,
 811                                                          FeatureHasVMLxHazards,
 812                                                          FeatureVMLxForwarding,
 813                                                          FeatureFP16,
 814                                                          FeatureAvoidPartialCPSR,
 815                                                          FeatureExpandMLx,
 816                                                          FeaturePreferVMOVSR,
 817                                                          FeatureMuxedUnits,
 818                                                          FeatureNEONForFPMovs,
 819                                                          FeatureCheckVLDnAlign,
 820                                                          FeatureMP]>;
 821
 822 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 823                                                          FeatureHasRetAddrStack,
 824                                                          FeatureTrustZone,
 825                                                          FeatureVMLxForwarding,
 826                                                          FeatureVFP4,
 827                                                          FeatureAvoidPartialCPSR,
 828                                                          FeatureVirtualization,
 829                                                          FeatureMP]>;
 830
 831 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 832                                                          FeatureDontWidenVMOVS,
 833                                                          FeatureSplatVFPToNeon,
 834                                                          FeatureHasRetAddrStack,
 835                                                          FeatureMuxedUnits,
 836                                                          FeatureTrustZone,
 837                                                          FeatureVFP4,
 838                                                          FeatureMP,
 839                                                          FeatureCheckVLDnAlign,
 840                                                          FeatureAvoidPartialCPSR,
 841                                                          FeatureVirtualization]>;
 842
 843 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 844                                                          FeatureHasRetAddrStack,
 845                                                          FeatureTrustZone,
 846                                                          FeatureMP,
 847                                                          FeatureVMLxForwarding,
 848                                                          FeatureVFP4,
 849                                                          FeatureAvoidPartialCPSR,
 850                                                          FeatureVirtualization]>;
 851
 852 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 853 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 854                                                          FeatureHasRetAddrStack,
 855                                                          FeatureMuxedUnits,
 856                                                          FeatureCheckVLDnAlign,
 857                                                          FeatureVMLxForwarding,
 858                                                          FeatureFP16,
 859                                                          FeatureAvoidPartialCPSR,
 860                                                          FeatureVFP4,
 861                                                          FeatureHWDivThumb,
 862                                                          FeatureHWDivARM]>;
 863
 864 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 865                                                          FeatureHasRetAddrStack,
 866                                                          FeatureNEONForFP,
 867                                                          FeatureVFP4,
 868                                                          FeatureMP,
 869                                                          FeatureHWDivThumb,
 870                                                          FeatureHWDivARM,
 871                                                          FeatureAvoidPartialCPSR,
 872                                                          FeatureAvoidMOVsShOp,
 873                                                          FeatureHasSlowFPVMLx,
 874                                                          FeatureHasVMLxHazards,
 875                                                          FeatureProfUnpredicate,
 876                                                          FeaturePrefISHSTBarrier,
 877                                                          FeatureSlowOddRegister,
 878                                                          FeatureSlowLoadDSubreg,
 879                                                          FeatureSlowVGETLNi32,
 880                                                          FeatureSlowVDUP32,
 881                                                          FeatureUseMISched,
 882                                                          FeatureNoPostRASched]>;
 883
 884 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 885                                                          FeatureHasRetAddrStack,
 886                                                          FeatureAvoidPartialCPSR]>;
 887
 888 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 889                                                          FeatureHasRetAddrStack,
 890                                                          FeatureSlowFPBrcc,
 891                                                          FeatureHasSlowFPVMLx,
 892                                                          FeatureVFP3,
 893                                                          FeatureD16,
 894                                                          FeatureAvoidPartialCPSR]>;
 895
 896 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 897                                                          FeatureHasRetAddrStack,
 898                                                          FeatureVFP3,
 899                                                          FeatureD16,
 900                                                          FeatureSlowFPBrcc,
 901                                                          FeatureHWDivARM,
 902                                                          FeatureHasSlowFPVMLx,
 903                                                          FeatureAvoidPartialCPSR]>;
 904
 905 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 906                                                          FeatureHasRetAddrStack,
 907                                                          FeatureVFP3,
 908                                                          FeatureD16,
 909                                                          FeatureFP16,
 910                                                          FeatureMP,
 911                                                          FeatureSlowFPBrcc,
 912                                                          FeatureHWDivARM,
 913                                                          FeatureHasSlowFPVMLx,
 914                                                          FeatureAvoidPartialCPSR]>;
 915
 916 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
 917                                                          FeatureHasRetAddrStack,
 918                                                          FeatureVFP3,
 919                                                          FeatureD16,
 920                                                          FeatureFP16,
 921                                                          FeatureMP,
 922                                                          FeatureSlowFPBrcc,
 923                                                          FeatureHWDivARM,
 924                                                          FeatureHasSlowFPVMLx,
 925                                                          FeatureAvoidPartialCPSR]>;
 926
 927 def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
 928                                                          ProcM3,
 929                                                          FeatureHasNoBranchPredictor]>;
 930
 931 def : ProcessorModel<"sc300",     CortexM3Model,        [ARMv7m,
 932                                                          ProcM3,
 933                                                          FeatureHasNoBranchPredictor]>;
 934
 935 def : ProcessorModel<"cortex-m4", CortexM3Model,        [ARMv7em,
 936                                                          FeatureVFP4,
 937                                                          FeatureVFPOnlySP,
 938                                                          FeatureD16,
 939                                                          FeatureHasNoBranchPredictor]>;
 940
 941 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 942                                                          FeatureFPARMv8,
 943                                                          FeatureD16]>;
 944
 945 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
 946                                                          FeatureNoMovt]>;
 947
 948 def : ProcessorModel<"cortex-m33", CortexM3Model,       [ARMv8mMainline,
 949                                                          FeatureDSP,
 950                                                          FeatureFPARMv8,
 951                                                          FeatureD16,
 952                                                          FeatureVFPOnlySP,
 953                                                          FeatureHasNoBranchPredictor]>;
 954
 955 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
 956                                                          FeatureHWDivThumb,
 957                                                          FeatureHWDivARM,
 958                                                          FeatureCrypto,
 959                                                          FeatureCRC]>;
 960
 961 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
 962                                                          FeatureHWDivThumb,
 963                                                          FeatureHWDivARM,
 964                                                          FeatureCrypto,
 965                                                          FeatureCRC]>;
 966
 967 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
 968                                                          FeatureHWDivThumb,
 969                                                          FeatureHWDivARM,
 970                                                          FeatureCrypto,
 971                                                          FeatureCRC,
 972                                                          FeatureFPAO]>;
 973
 974 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
 975                                                          FeatureHWDivThumb,
 976                                                          FeatureHWDivARM,
 977                                                          FeatureDotProd]>;
 978
 979 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
 980                                                          FeatureHWDivThumb,
 981                                                          FeatureHWDivARM,
 982                                                          FeatureCrypto,
 983                                                          FeatureCRC,
 984                                                          FeatureFPAO,
 985                                                          FeatureAvoidPartialCPSR,
 986                                                          FeatureCheapPredicableCPSR]>;
 987
 988 def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
 989                                                          FeatureHWDivThumb,
 990                                                          FeatureHWDivARM,
 991                                                          FeatureCrypto,
 992                                                          FeatureCRC]>;
 993
 994 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
 995                                                          FeatureHWDivThumb,
 996                                                          FeatureHWDivARM,
 997                                                          FeatureCrypto,
 998                                                          FeatureCRC]>;
 999
1000 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
1001                                                          FeatureHWDivThumb,
1002                                                          FeatureHWDivARM,
1003                                                          FeatureDotProd]>;
1004
1005 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
1006                                                          FeatureHasRetAddrStack,
1007                                                          FeatureNEONForFP,
1008                                                          FeatureVFP4,
1009                                                          FeatureMP,
1010                                                          FeatureHWDivThumb,
1011                                                          FeatureHWDivARM,
1012                                                          FeatureAvoidPartialCPSR,
1013                                                          FeatureAvoidMOVsShOp,
1014                                                          FeatureHasSlowFPVMLx,
1015                                                          FeatureCrypto,
1016                                                          FeatureUseMISched,
1017                                                          FeatureZCZeroing,
1018                                                          FeatureNoPostRASched]>;
1019
1020 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
1021                                                          FeatureHWDivThumb,
1022                                                          FeatureHWDivARM,
1023                                                          FeatureCrypto,
1024                                                          FeatureCRC]>;
1025
1026 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
1027                                                          FeatureHWDivThumb,
1028                                                          FeatureHWDivARM,
1029                                                          FeatureCrypto,
1030                                                          FeatureCRC]>;
1031
1032 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynosM1,
1033                                                          FeatureHWDivThumb,
1034                                                          FeatureHWDivARM,
1035                                                          FeatureCrypto,
1036                                                          FeatureCRC]>;
1037
1038 def : ProcNoItin<"exynos-m4",                           [ARMv8a, ProcExynosM1,
1039                                                          FeatureHWDivThumb,
1040                                                          FeatureHWDivARM,
1041                                                          FeatureCrypto,
1042                                                          FeatureCRC]>;
1043
1044 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
1045                                                          FeatureHWDivThumb,
1046                                                          FeatureHWDivARM,
1047                                                          FeatureCrypto,
1048                                                          FeatureCRC]>;
1049
1050 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1051                                                          FeatureUseMISched,
1052                                                          FeatureFPAO,
1053                                                          FeatureUseAA]>;
1054
1055 //===----------------------------------------------------------------------===//
1056 // Register File Description
1057 //===----------------------------------------------------------------------===//
1058
1059 include "ARMRegisterInfo.td"
1060 include "ARMRegisterBanks.td"
1061 include "ARMCallingConv.td"
1062
1063 //===----------------------------------------------------------------------===//
1064 // Instruction Descriptions
1065 //===----------------------------------------------------------------------===//
1066
1067 include "ARMInstrInfo.td"
1068 def ARMInstrInfo : InstrInfo;
1069
1070 //===----------------------------------------------------------------------===//
1071 // Declare the target which we are implementing
1072 //===----------------------------------------------------------------------===//
1073
1074 def ARMAsmWriter : AsmWriter {
1075   string AsmWriterClassName  = "InstPrinter";
1076   int PassSubtarget = 1;
1077   int Variant = 0;
1078   bit isMCAsmWriter = 1;
1079 }
1080
1081 def ARMAsmParser : AsmParser {
1082   bit ReportMultipleNearMisses = 1;
1083 }
1084
1085 def ARMAsmParserVariant : AsmParserVariant {
1086   int Variant = 0;
1087   string Name = "ARM";
1088   string BreakCharacters = ".";
1089 }
1090
1091 def ARM : Target {
1092   // Pull in Instruction Info.
1093   let InstructionSet = ARMInstrInfo;
1094   let AssemblyWriters = [ARMAsmWriter];
1095   let AssemblyParsers = [ARMAsmParser];
1096   let AssemblyParserVariants = [ARMAsmParserVariant];
1097   let AllowRegisterRenaming = 1;
1098 }