contrib/llvm/lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Helper classes.
  21 //
  22
  23 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  24  : Processor<Name, NoItineraries, Features>;
  25
  26 class Architecture<string fname, string aname, list<SubtargetFeature> features >
  27   : SubtargetFeature<fname, "ARMArch", aname,
  28                      !strconcat(aname, " architecture"), features>;
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget state.
  32 //
  33
  34 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  35                                   "Thumb mode">;
  36
  37 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
  38                                      "Use software floating point features.">;
  39
  40 //===----------------------------------------------------------------------===//
  41 // ARM Subtarget features.
  42 //
  43
  44 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  45                                    "Enable VFP2 instructions">;
  46 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  47                                    "Enable VFP3 instructions",
  48                                    [FeatureVFP2]>;
  49 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  50                                    "Enable NEON instructions",
  51                                    [FeatureVFP3]>;
  52 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  53                                      "Enable Thumb2 instructions">;
  54 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  55                                      "Does not support ARM mode execution",
  56                                      [ModeThumb]>;
  57 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  58                                      "Enable half-precision floating point">;
  59 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  60                                      "Enable VFP4 instructions",
  61                                      [FeatureVFP3, FeatureFP16]>;
  62 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  63                                    "true", "Enable ARMv8 FP",
  64                                    [FeatureVFP4]>;
  65 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  66                                        "Enable full half-precision floating point",
  67                                        [FeatureFPARMv8]>;
  68 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  69                                      "Restrict FP to 16 double registers">;
  70 def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb",
  71                                          "true",
  72                                          "Enable divide instructions in Thumb">;
  73 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  74                                         "HasHardwareDivideInARM", "true",
  75                                       "Enable divide instructions in ARM mode">;
  76 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  77                                    "Has data barrier (dmb / dsb) instructions">;
  78 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
  79                                       "Has v7 clrex instruction">;
  80 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
  81                                              "HasAcquireRelease", "true",
  82                          "Has v8 acquire/release (lda/ldaex etc) instructions">;
  83 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  84                                          "FP compare + branch is slow">;
  85 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  86                           "Floating point unit supports single precision only">;
  87 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  88                            "Enable support for Performance Monitor extensions">;
  89 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  90                           "Enable support for TrustZone security extensions">;
  91 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
  92                           "Enable support for ARMv8-M Security Extensions">;
  93 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  94                           "Enable support for Cryptography extensions",
  95                           [FeatureNEON]>;
  96 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  97                           "Enable support for CRC instructions">;
  98 // Not to be confused with FeatureHasRetAddrStack (return address stack)
  99 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
 100                 "Enable Reliability, Availability and Serviceability extensions">;
 101 def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
 102                 "Enable fast computation of positive address offsets">;
 103 def FeatureFuseAES : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 104                                       "CPU fuses AES crypto operations">;
 105
 106 // Cyclone has preferred instructions for zeroing VFP registers, which can
 107 // execute in 0 cycles.
 108 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 109                                         "Has zero-cycle zeroing instructions">;
 110
 111 // Whether or not it may be profitable to unpredicate certain instructions
 112 // during if conversion.
 113 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 114                                               "IsProfitableToUnpredicate",
 115                                               "true",
 116                                               "Is profitable to unpredicate">;
 117
 118 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 119 def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
 120                                             "HasSlowVGETLNi32", "true",
 121                                             "Has slow VGETLNi32 - prefer VMOV">;
 122
 123 // Some targets (e.g. Swift) have microcoded VDUP32.
 124 def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
 125                                          "Has slow VDUP32 - prefer VMOV">;
 126
 127 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 128 // for scalar FP, as this allows more effective execution domain optimization.
 129 def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 130                                            "true", "Prefer VMOVSR">;
 131
 132 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 133 // than ISH
 134 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 135                                            "true", "Prefer ISHST barriers">;
 136
 137 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 138 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
 139                                          "Has muxed AGU and NEON/FPU">;
 140
 141 // On some targets, a VLDM/VSTM starting with an odd register number needs more
 142 // microops than single VLDRS.
 143 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 144                      "true", "VLDM/VSTM starting with an odd register is slow">;
 145
 146 // Some targets have a renaming dependency when loading into D subregisters.
 147 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 148                                               "SlowLoadDSubregister", "true",
 149                                               "Loading into D subregs is slow">;
 150 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 151 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 152                                              "DontWidenVMOVS", "true",
 153                                              "Don't widen VMOVS to VMOVD">;
 154
 155 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 156 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
 157                                         "Expand VFP/NEON MLA/MLS instructions">;
 158
 159 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 160 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 161                                              "true", "Has VMLx hazards">;
 162
 163 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 164 // VFP to NEON, as an execution domain optimization.
 165 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
 166                               "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
 167
 168 // Some processors benefit from using NEON instructions for scalar
 169 // single-precision FP operations. This affects instruction selection and should
 170 // only be enabled if the handling of denormals is not important.
 171 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
 172                                         "true",
 173                                         "Use NEON for single precision FP">;
 174
 175 // On some processors, VLDn instructions that access unaligned data take one
 176 // extra cycle. Take that into account when computing operand latencies.
 177 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 178                                              "true",
 179                                              "Check for VLDn unaligned access">;
 180
 181 // Some processors have a nonpipelined VFP coprocessor.
 182 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 183                                               "NonpipelinedVFP", "true",
 184                                           "VFP instructions are not pipelined">;
 185
 186 // Some processors have FP multiply-accumulate instructions that don't
 187 // play nicely with other VFP / NEON instructions, and it's generally better
 188 // to just not use them.
 189 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 190                                          "Disable VFP / NEON MAC instructions">;
 191
 192 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 193 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 194                                        "HasVMLxForwarding", "true",
 195                                        "Has multiplier accumulator forwarding">;
 196
 197 // Disable 32-bit to 16-bit narrowing for experimentation.
 198 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 199                                              "Prefer 32-bit Thumb instrs">;
 200
 201 /// Some instructions update CPSR partially, which can add false dependency for
 202 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 203 /// mapped to a separate physical register. Avoid partial CPSR update for these
 204 /// processors.
 205 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 206                                                "AvoidCPSRPartialUpdate", "true",
 207                                  "Avoid CPSR partial update for OOO execution">;
 208
 209 /// Disable +1 predication cost for instructions updating CPSR.
 210 /// Enabled for Cortex-A57.
 211 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 212                                                   "CheapPredicableCPSRDef",
 213                                                   "true",
 214                   "Disable +1 predication cost for instructions updating CPSR">;
 215
 216 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
 217                                             "AvoidMOVsShifterOperand", "true",
 218                                 "Avoid movs instructions with shifter operand">;
 219
 220 // Some processors perform return stack prediction. CodeGen should avoid issue
 221 // "normal" call instructions to callees which do not return.
 222 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
 223                                      "Has return address stack">;
 224
 225 /// DSP extension.
 226 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
 227                               "Supports DSP instructions in ARM and/or Thumb2">;
 228
 229 // Multiprocessing extension.
 230 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 231                                  "Supports Multiprocessing extension">;
 232
 233 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 234 def FeatureVirtualization : SubtargetFeature<"virtualization",
 235                                  "HasVirtualization", "true",
 236                                  "Supports Virtualization extension",
 237                                  [FeatureHWDivThumb, FeatureHWDivARM]>;
 238
 239 // M-series ISA
 240 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 241                                      "Is microcontroller profile ('M' series)">;
 242
 243 // R-series ISA
 244 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 245                                      "Is realtime profile ('R' series)">;
 246
 247 // A-series ISA
 248 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 249                                      "Is application profile ('A' series)">;
 250
 251 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 252 // See ARMInstrInfo.td for details.
 253 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 254                                        "NaCl trap">;
 255
 256 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 257                                           "StrictAlign", "true",
 258                                           "Disallow all unaligned memory "
 259                                           "access">;
 260
 261 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 262                                         "Generate calls via indirect call "
 263                                         "instructions">;
 264
 265 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 266                                         "Reserve R9, making it unavailable as "
 267                                         "GPR">;
 268
 269 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
 270                                      "Don't use movt/movw pairs for 32-bit "
 271                                      "imms">;
 272
 273 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 274                                         "NegativeImmediates", "false",
 275                                         "Convert immediates and instructions "
 276                                         "to their negated or complemented "
 277                                         "equivalent when the immediate does "
 278                                         "not fit in the encoding.">;
 279
 280 //===----------------------------------------------------------------------===//
 281 // ARM ISAa.
 282 //
 283
 284 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 285                                    "Support ARM v4T instructions">;
 286 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 287                                    "Support ARM v5T instructions",
 288                                    [HasV4TOps]>;
 289 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 290                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 291                                    [HasV5TOps]>;
 292 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 293                                    "Support ARM v6 instructions",
 294                                    [HasV5TEOps]>;
 295 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 296                                    "Support ARM v6M instructions",
 297                                    [HasV6Ops]>;
 298 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 299                                          "Support ARM v8M Baseline instructions",
 300                                          [HasV6MOps]>;
 301 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 302                                    "Support ARM v6k instructions",
 303                                    [HasV6Ops]>;
 304 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 305                                    "Support ARM v6t2 instructions",
 306                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 307 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 308                                    "Support ARM v7 instructions",
 309                                    [HasV6T2Ops, FeaturePerfMon,
 310                                     FeatureV7Clrex]>;
 311 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 312                                    "Support ARM v8 instructions",
 313                                    [HasV7Ops, FeatureAcquireRelease]>;
 314 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 315                                    "Support ARM v8.1a instructions",
 316                                    [HasV8Ops]>;
 317 def HasV8_2aOps   : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 318                                    "Support ARM v8.2a instructions",
 319                                    [HasV8_1aOps]>;
 320 def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 321                                          "Support ARM v8M Mainline instructions",
 322                                          [HasV7Ops]>;
 323
 324
 325 //===----------------------------------------------------------------------===//
 326 // ARM Processor subtarget features.
 327 //
 328
 329 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 330                                    "Cortex-A5 ARM processors", []>;
 331 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 332                                    "Cortex-A7 ARM processors", []>;
 333 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 334                                    "Cortex-A8 ARM processors", []>;
 335 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 336                                    "Cortex-A9 ARM processors", []>;
 337 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 338                                    "Cortex-A12 ARM processors", []>;
 339 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 340                                    "Cortex-A15 ARM processors", []>;
 341 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 342                                    "Cortex-A17 ARM processors", []>;
 343 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 344                                    "Cortex-A32 ARM processors", []>;
 345 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 346                                    "Cortex-A35 ARM processors", []>;
 347 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 348                                    "Cortex-A53 ARM processors", []>;
 349 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 350                                    "Cortex-A57 ARM processors", []>;
 351 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 352                                    "Cortex-A72 ARM processors", []>;
 353 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 354                                    "Cortex-A73 ARM processors", []>;
 355
 356 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 357                                    "Qualcomm Krait processors", []>;
 358 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 359                                    "Qualcomm Kryo processors", []>;
 360 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 361                                    "Swift ARM processors", []>;
 362
 363 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 364                                     "Samsung Exynos-M1 processors", []>;
 365
 366 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 367                                    "Cortex-R4 ARM processors", []>;
 368 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 369                                    "Cortex-R5 ARM processors", []>;
 370 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 371                                    "Cortex-R7 ARM processors", []>;
 372 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 373                                    "Cortex-R52 ARM processors", []>;
 374
 375 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 376                                    "Cortex-M3 ARM processors", []>;
 377
 378 //===----------------------------------------------------------------------===//
 379 // ARM schedules.
 380 //
 381
 382 include "ARMSchedule.td"
 383
 384
 385 //===----------------------------------------------------------------------===//
 386 // ARM architectures
 387 //
 388
 389 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 390
 391 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 392
 393 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 394
 395 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 396
 397 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 398
 399 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 400
 401 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 402
 403 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 404
 405 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 406
 407 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops]>;
 408
 409 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 410                                                        FeatureDSP]>;
 411
 412 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 413
 414 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 415                                                        FeatureTrustZone]>;
 416
 417 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 418                                                        FeatureNoARM,
 419                                                        FeatureDB,
 420                                                        FeatureMClass]>;
 421
 422 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 423                                                        FeatureNoARM,
 424                                                        FeatureDB,
 425                                                        FeatureMClass]>;
 426
 427 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 428                                                        FeatureNEON,
 429                                                        FeatureDB,
 430                                                        FeatureDSP,
 431                                                        FeatureAClass]>;
 432
 433 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 434                                                        FeatureNEON,
 435                                                        FeatureDB,
 436                                                        FeatureDSP,
 437                                                        FeatureTrustZone,
 438                                                        FeatureMP,
 439                                                        FeatureVirtualization,
 440                                                        FeatureAClass]>;
 441
 442 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 443                                                        FeatureDB,
 444                                                        FeatureDSP,
 445                                                        FeatureHWDivThumb,
 446                                                        FeatureRClass]>;
 447
 448 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 449                                                        FeatureThumb2,
 450                                                        FeatureNoARM,
 451                                                        FeatureDB,
 452                                                        FeatureHWDivThumb,
 453                                                        FeatureMClass]>;
 454
 455 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 456                                                        FeatureThumb2,
 457                                                        FeatureNoARM,
 458                                                        FeatureDB,
 459                                                        FeatureHWDivThumb,
 460                                                        FeatureMClass,
 461                                                        FeatureDSP]>;
 462
 463 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 464                                                        FeatureAClass,
 465                                                        FeatureDB,
 466                                                        FeatureFPARMv8,
 467                                                        FeatureNEON,
 468                                                        FeatureDSP,
 469                                                        FeatureTrustZone,
 470                                                        FeatureMP,
 471                                                        FeatureVirtualization,
 472                                                        FeatureCrypto,
 473                                                        FeatureCRC]>;
 474
 475 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 476                                                        FeatureAClass,
 477                                                        FeatureDB,
 478                                                        FeatureFPARMv8,
 479                                                        FeatureNEON,
 480                                                        FeatureDSP,
 481                                                        FeatureTrustZone,
 482                                                        FeatureMP,
 483                                                        FeatureVirtualization,
 484                                                        FeatureCrypto,
 485                                                        FeatureCRC]>;
 486
 487 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 488                                                        FeatureAClass,
 489                                                        FeatureDB,
 490                                                        FeatureFPARMv8,
 491                                                        FeatureNEON,
 492                                                        FeatureDSP,
 493                                                        FeatureTrustZone,
 494                                                        FeatureMP,
 495                                                        FeatureVirtualization,
 496                                                        FeatureCrypto,
 497                                                        FeatureCRC,
 498                                                        FeatureRAS]>;
 499
 500 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 501                                                        FeatureRClass,
 502                                                        FeatureDB,
 503                                                        FeatureDSP,
 504                                                        FeatureCRC,
 505                                                        FeatureMP,
 506                                                        FeatureVirtualization,
 507                                                        FeatureFPARMv8,
 508                                                        FeatureNEON]>;
 509
 510 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 511                                                       [HasV8MBaselineOps,
 512                                                        FeatureNoARM,
 513                                                        FeatureDB,
 514                                                        FeatureHWDivThumb,
 515                                                        FeatureV7Clrex,
 516                                                        Feature8MSecExt,
 517                                                        FeatureAcquireRelease,
 518                                                        FeatureMClass]>;
 519
 520 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 521                                                       [HasV8MMainlineOps,
 522                                                        FeatureNoARM,
 523                                                        FeatureDB,
 524                                                        FeatureHWDivThumb,
 525                                                        Feature8MSecExt,
 526                                                        FeatureAcquireRelease,
 527                                                        FeatureMClass]>;
 528
 529 // Aliases
 530 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 531 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 532 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 533 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 534 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 535 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 536
 537
 538 //===----------------------------------------------------------------------===//
 539 // ARM processors
 540 //
 541
 542 // Dummy CPU, used to target architectures
 543 def : ProcNoItin<"generic",                             []>;
 544
 545 def : ProcNoItin<"arm8",                                [ARMv4]>;
 546 def : ProcNoItin<"arm810",                              [ARMv4]>;
 547 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 548 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 549 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 550 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 551
 552 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 553 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 554 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 555 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 556 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 557 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 558 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 559 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 560 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 561 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 562 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 563
 564 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 565 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 566
 567 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 568 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 569 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 570 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 571 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 572 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 573 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 574 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 575 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 576 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 577
 578 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 579 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 580                                                          FeatureVFP2,
 581                                                          FeatureHasSlowFPVMLx]>;
 582
 583 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 584 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 585 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 586 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 587
 588 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 589 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 590 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 591                                                          FeatureVFP2,
 592                                                          FeatureHasSlowFPVMLx]>;
 593
 594 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 595 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 596                                                          FeatureVFP2,
 597                                                          FeatureHasSlowFPVMLx]>;
 598
 599 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 600 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 601                                                          FeatureVFP2,
 602                                                          FeatureHasSlowFPVMLx]>;
 603
 604 // FIXME: A5 has currently the same Schedule model as A8
 605 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 606                                                          FeatureHasRetAddrStack,
 607                                                          FeatureTrustZone,
 608                                                          FeatureSlowFPBrcc,
 609                                                          FeatureHasSlowFPVMLx,
 610                                                          FeatureVMLxForwarding,
 611                                                          FeatureMP,
 612                                                          FeatureVFP4]>;
 613
 614 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 615                                                          FeatureHasRetAddrStack,
 616                                                          FeatureTrustZone,
 617                                                          FeatureSlowFPBrcc,
 618                                                          FeatureHasVMLxHazards,
 619                                                          FeatureHasSlowFPVMLx,
 620                                                          FeatureVMLxForwarding,
 621                                                          FeatureMP,
 622                                                          FeatureVFP4,
 623                                                          FeatureVirtualization]>;
 624
 625 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 626                                                          FeatureHasRetAddrStack,
 627                                                          FeatureNonpipelinedVFP,
 628                                                          FeatureTrustZone,
 629                                                          FeatureSlowFPBrcc,
 630                                                          FeatureHasVMLxHazards,
 631                                                          FeatureHasSlowFPVMLx,
 632                                                          FeatureVMLxForwarding]>;
 633
 634 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 635                                                          FeatureHasRetAddrStack,
 636                                                          FeatureTrustZone,
 637                                                          FeatureHasVMLxHazards,
 638                                                          FeatureVMLxForwarding,
 639                                                          FeatureFP16,
 640                                                          FeatureAvoidPartialCPSR,
 641                                                          FeatureExpandMLx,
 642                                                          FeaturePreferVMOVSR,
 643                                                          FeatureMuxedUnits,
 644                                                          FeatureNEONForFPMovs,
 645                                                          FeatureCheckVLDnAlign,
 646                                                          FeatureMP]>;
 647
 648 // FIXME: A12 has currently the same Schedule model as A9
 649 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 650                                                          FeatureHasRetAddrStack,
 651                                                          FeatureTrustZone,
 652                                                          FeatureVMLxForwarding,
 653                                                          FeatureVFP4,
 654                                                          FeatureAvoidPartialCPSR,
 655                                                          FeatureVirtualization,
 656                                                          FeatureMP]>;
 657
 658 // FIXME: A15 has currently the same Schedule model as A9.
 659 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 660                                                          FeatureDontWidenVMOVS,
 661                                                          FeatureHasRetAddrStack,
 662                                                          FeatureMuxedUnits,
 663                                                          FeatureTrustZone,
 664                                                          FeatureVFP4,
 665                                                          FeatureMP,
 666                                                          FeatureCheckVLDnAlign,
 667                                                          FeatureAvoidPartialCPSR,
 668                                                          FeatureVirtualization]>;
 669
 670 // FIXME: A17 has currently the same Schedule model as A9
 671 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 672                                                          FeatureHasRetAddrStack,
 673                                                          FeatureTrustZone,
 674                                                          FeatureMP,
 675                                                          FeatureVMLxForwarding,
 676                                                          FeatureVFP4,
 677                                                          FeatureAvoidPartialCPSR,
 678                                                          FeatureVirtualization]>;
 679
 680 // FIXME: krait has currently the same Schedule model as A9
 681 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
 682 //        division features.
 683 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 684                                                          FeatureHasRetAddrStack,
 685                                                          FeatureMuxedUnits,
 686                                                          FeatureCheckVLDnAlign,
 687                                                          FeatureVMLxForwarding,
 688                                                          FeatureFP16,
 689                                                          FeatureAvoidPartialCPSR,
 690                                                          FeatureVFP4,
 691                                                          FeatureHWDivThumb,
 692                                                          FeatureHWDivARM]>;
 693
 694 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 695                                                          FeatureHasRetAddrStack,
 696                                                          FeatureNEONForFP,
 697                                                          FeatureVFP4,
 698                                                          FeatureMP,
 699                                                          FeatureHWDivThumb,
 700                                                          FeatureHWDivARM,
 701                                                          FeatureAvoidPartialCPSR,
 702                                                          FeatureAvoidMOVsShOp,
 703                                                          FeatureHasSlowFPVMLx,
 704                                                          FeatureHasVMLxHazards,
 705                                                          FeatureProfUnpredicate,
 706                                                          FeaturePrefISHSTBarrier,
 707                                                          FeatureSlowOddRegister,
 708                                                          FeatureSlowLoadDSubreg,
 709                                                          FeatureSlowVGETLNi32,
 710                                                          FeatureSlowVDUP32]>;
 711
 712 // FIXME: R4 has currently the same ProcessorModel as A8.
 713 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 714                                                          FeatureHasRetAddrStack,
 715                                                          FeatureAvoidPartialCPSR]>;
 716
 717 // FIXME: R4F has currently the same ProcessorModel as A8.
 718 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 719                                                          FeatureHasRetAddrStack,
 720                                                          FeatureSlowFPBrcc,
 721                                                          FeatureHasSlowFPVMLx,
 722                                                          FeatureVFP3,
 723                                                          FeatureD16,
 724                                                          FeatureAvoidPartialCPSR]>;
 725
 726 // FIXME: R5 has currently the same ProcessorModel as A8.
 727 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 728                                                          FeatureHasRetAddrStack,
 729                                                          FeatureVFP3,
 730                                                          FeatureD16,
 731                                                          FeatureSlowFPBrcc,
 732                                                          FeatureHWDivARM,
 733                                                          FeatureHasSlowFPVMLx,
 734                                                          FeatureAvoidPartialCPSR]>;
 735
 736 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 737 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 738                                                          FeatureHasRetAddrStack,
 739                                                          FeatureVFP3,
 740                                                          FeatureD16,
 741                                                          FeatureFP16,
 742                                                          FeatureMP,
 743                                                          FeatureSlowFPBrcc,
 744                                                          FeatureHWDivARM,
 745                                                          FeatureHasSlowFPVMLx,
 746                                                          FeatureAvoidPartialCPSR]>;
 747
 748 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
 749                                                          FeatureHasRetAddrStack,
 750                                                          FeatureVFP3,
 751                                                          FeatureD16,
 752                                                          FeatureFP16,
 753                                                          FeatureMP,
 754                                                          FeatureSlowFPBrcc,
 755                                                          FeatureHWDivARM,
 756                                                          FeatureHasSlowFPVMLx,
 757                                                          FeatureAvoidPartialCPSR]>;
 758
 759 def : ProcNoItin<"cortex-m3",                           [ARMv7m, ProcM3]>;
 760 def : ProcNoItin<"sc300",                               [ARMv7m, ProcM3]>;
 761
 762 def : ProcNoItin<"cortex-m4",                           [ARMv7em,
 763                                                          FeatureVFP4,
 764                                                          FeatureVFPOnlySP,
 765                                                          FeatureD16]>;
 766
 767 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 768                                                          FeatureFPARMv8,
 769                                                          FeatureD16]>;
 770
 771 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
 772                                                          FeatureNoMovt]>;
 773
 774 def : ProcNoItin<"cortex-m33",                          [ARMv8mMainline,
 775                                                          FeatureDSP,
 776                                                          FeatureFPARMv8,
 777                                                          FeatureD16,
 778                                                          FeatureVFPOnlySP]>;
 779
 780 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
 781                                                          FeatureHWDivThumb,
 782                                                          FeatureHWDivARM,
 783                                                          FeatureCrypto,
 784                                                          FeatureCRC]>;
 785
 786 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
 787                                                          FeatureHWDivThumb,
 788                                                          FeatureHWDivARM,
 789                                                          FeatureCrypto,
 790                                                          FeatureCRC]>;
 791
 792 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
 793                                                          FeatureHWDivThumb,
 794                                                          FeatureHWDivARM,
 795                                                          FeatureCrypto,
 796                                                          FeatureCRC,
 797                                                          FeatureFPAO]>;
 798
 799 def : ProcessorModel<"cortex-a57",  CortexA57Model, [ARMv8a, ProcA57,
 800                                                      FeatureHWDivThumb,
 801                                                      FeatureHWDivARM,
 802                                                      FeatureCrypto,
 803                                                      FeatureCRC,
 804                                                      FeatureFPAO,
 805                                                      FeatureAvoidPartialCPSR,
 806                                                      FeatureCheapPredicableCPSR]>;
 807
 808 def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
 809                                                          FeatureHWDivThumb,
 810                                                          FeatureHWDivARM,
 811                                                          FeatureCrypto,
 812                                                          FeatureCRC]>;
 813
 814 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
 815                                                          FeatureHWDivThumb,
 816                                                          FeatureHWDivARM,
 817                                                          FeatureCrypto,
 818                                                          FeatureCRC]>;
 819
 820 // Cyclone is very similar to swift
 821 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
 822                                                          FeatureHasRetAddrStack,
 823                                                          FeatureNEONForFP,
 824                                                          FeatureVFP4,
 825                                                          FeatureMP,
 826                                                          FeatureHWDivThumb,
 827                                                          FeatureHWDivARM,
 828                                                          FeatureAvoidPartialCPSR,
 829                                                          FeatureAvoidMOVsShOp,
 830                                                          FeatureHasSlowFPVMLx,
 831                                                          FeatureCrypto,
 832                                                          FeatureZCZeroing]>;
 833
 834 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
 835                                                          FeatureHWDivThumb,
 836                                                          FeatureHWDivARM,
 837                                                          FeatureCrypto,
 838                                                          FeatureCRC]>;
 839
 840 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
 841                                                          FeatureHWDivThumb,
 842                                                          FeatureHWDivARM,
 843                                                          FeatureCrypto,
 844                                                          FeatureCRC]>;
 845
 846 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynosM1,
 847                                                          FeatureHWDivThumb,
 848                                                          FeatureHWDivARM,
 849                                                          FeatureCrypto,
 850                                                          FeatureCRC]>;
 851
 852 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
 853                                                          FeatureHWDivThumb,
 854                                                          FeatureHWDivARM,
 855                                                          FeatureCrypto,
 856                                                          FeatureCRC]>;
 857
 858 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
 859                                                          FeatureFPAO]>;
 860
 861 //===----------------------------------------------------------------------===//
 862 // Register File Description
 863 //===----------------------------------------------------------------------===//
 864
 865 include "ARMRegisterInfo.td"
 866
 867 include "ARMRegisterBanks.td"
 868
 869 include "ARMCallingConv.td"
 870
 871 //===----------------------------------------------------------------------===//
 872 // Instruction Descriptions
 873 //===----------------------------------------------------------------------===//
 874
 875 include "ARMInstrInfo.td"
 876
 877 def ARMInstrInfo : InstrInfo;
 878
 879 //===----------------------------------------------------------------------===//
 880 // Declare the target which we are implementing
 881 //===----------------------------------------------------------------------===//
 882
 883 def ARMAsmWriter : AsmWriter {
 884   string AsmWriterClassName  = "InstPrinter";
 885   int PassSubtarget = 1;
 886   int Variant = 0;
 887   bit isMCAsmWriter = 1;
 888 }
 889
 890 def ARMAsmParserVariant : AsmParserVariant {
 891   int Variant = 0;
 892   string Name = "ARM";
 893   string BreakCharacters = ".";
 894 }
 895
 896 def ARM : Target {
 897   // Pull in Instruction Info:
 898   let InstructionSet = ARMInstrInfo;
 899   let AssemblyWriters = [ARMAsmWriter];
 900   let AssemblyParserVariants = [ARMAsmParserVariant];
 901 }