contrib/llvm/lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Subtarget state.
  21 //
  22
  23 def ModeThumb             : SubtargetFeature<"thumb-mode", "InThumbMode",
  24                                              "true", "Thumb mode">;
  25
  26 def ModeSoftFloat         : SubtargetFeature<"soft-float","UseSoftFloat",
  27                                              "true", "Use software floating "
  28                                              "point features.">;
  29
  30
  31 //===----------------------------------------------------------------------===//
  32 // ARM Subtarget features.
  33 //
  34
  35 // Floating Point, HW Division and Neon Support
  36 def FeatureVFP2           : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  37                                              "Enable VFP2 instructions">;
  38
  39 def FeatureVFP3           : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  40                                              "Enable VFP3 instructions",
  41                                              [FeatureVFP2]>;
  42
  43 def FeatureNEON           : SubtargetFeature<"neon", "HasNEON", "true",
  44                                              "Enable NEON instructions",
  45                                              [FeatureVFP3]>;
  46
  47 def FeatureFP16           : SubtargetFeature<"fp16", "HasFP16", "true",
  48                                              "Enable half-precision "
  49                                              "floating point">;
  50
  51 def FeatureVFP4           : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  52                                              "Enable VFP4 instructions",
  53                                              [FeatureVFP3, FeatureFP16]>;
  54
  55 def FeatureFPARMv8        : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  56                                              "true", "Enable ARMv8 FP",
  57                                              [FeatureVFP4]>;
  58
  59 def FeatureFullFP16       : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  60                                              "Enable full half-precision "
  61                                              "floating point",
  62                                              [FeatureFPARMv8]>;
  63
  64 def FeatureVFPOnlySP      : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  65                                              "Floating point unit supports "
  66                                              "single precision only">;
  67
  68 def FeatureD16            : SubtargetFeature<"d16", "HasD16", "true",
  69                                              "Restrict FP to 16 double registers">;
  70
  71 def FeatureHWDivThumb     : SubtargetFeature<"hwdiv",
  72                                              "HasHardwareDivideInThumb", "true",
  73                                              "Enable divide instructions in Thumb">;
  74
  75 def FeatureHWDivARM       : SubtargetFeature<"hwdiv-arm",
  76                                              "HasHardwareDivideInARM", "true",
  77                                              "Enable divide instructions in ARM mode">;
  78
  79 // Atomic Support
  80 def FeatureDB             : SubtargetFeature<"db", "HasDataBarrier", "true",
  81                                              "Has data barrier (dmb/dsb) instructions">;
  82
  83 def FeatureV7Clrex        : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
  84                                              "Has v7 clrex instruction">;
  85
  86 def FeatureDFB  : SubtargetFeature<"dfb", "HasFullDataBarrier", "true",
  87                                    "Has full data barrier (dfb) instruction">;
  88
  89 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
  90                                              "HasAcquireRelease", "true",
  91                                              "Has v8 acquire/release (lda/ldaex "
  92                                              " etc) instructions">;
  93
  94
  95 def FeatureSlowFPBrcc     : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  96                                              "FP compare + branch is slow">;
  97
  98 def FeaturePerfMon        : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  99                                              "Enable support for Performance "
 100                                              "Monitor extensions">;
 101
 102
 103 // TrustZone Security Extensions
 104 def FeatureTrustZone      : SubtargetFeature<"trustzone", "HasTrustZone", "true",
 105                                              "Enable support for TrustZone "
 106                                              "security extensions">;
 107
 108 def Feature8MSecExt       : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
 109                                              "Enable support for ARMv8-M "
 110                                              "Security Extensions">;
 111
 112 def FeatureCrypto         : SubtargetFeature<"crypto", "HasCrypto", "true",
 113                                              "Enable support for "
 114                                              "Cryptography extensions",
 115                                              [FeatureNEON]>;
 116
 117 def FeatureCRC            : SubtargetFeature<"crc", "HasCRC", "true",
 118                                              "Enable support for CRC instructions">;
 119
 120 def FeatureDotProd        : SubtargetFeature<"dotprod", "HasDotProd", "true",
 121                                              "Enable support for dot product instructions",
 122                                              [FeatureNEON]>;
 123
 124 // Not to be confused with FeatureHasRetAddrStack (return address stack)
 125 def FeatureRAS            : SubtargetFeature<"ras", "HasRAS", "true",
 126                                              "Enable Reliability, Availability "
 127                                              "and Serviceability extensions">;
 128
 129 // Fast computation of non-negative address offsets
 130 def FeatureFPAO           : SubtargetFeature<"fpao", "HasFPAO", "true",
 131                                              "Enable fast computation of "
 132                                              "positive address offsets">;
 133
 134 // Fast execution of AES crypto operations
 135 def FeatureFuseAES        : SubtargetFeature<"fuse-aes", "HasFuseAES", "true",
 136                                              "CPU fuses AES crypto operations">;
 137
 138 // The way of reading thread pointer
 139 def FeatureReadTp :  SubtargetFeature<"read-tp-hard", "ReadTPHard", "true",
 140                                       "Reading thread pointer from register">;
 141
 142 // Cyclone can zero VFP registers in 0 cycles.
 143 def FeatureZCZeroing      : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 144                                              "Has zero-cycle zeroing instructions">;
 145
 146 // Whether it is profitable to unpredicate certain instructions during if-conversion
 147 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 148                                               "IsProfitableToUnpredicate", "true",
 149                                               "Is profitable to unpredicate">;
 150
 151 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 152 def FeatureSlowVGETLNi32  : SubtargetFeature<"slow-vgetlni32",
 153                                              "HasSlowVGETLNi32", "true",
 154                                              "Has slow VGETLNi32 - prefer VMOV">;
 155
 156 // Some targets (e.g. Swift) have microcoded VDUP32.
 157 def FeatureSlowVDUP32     : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32",
 158                                              "true",
 159                                              "Has slow VDUP32 - prefer VMOV">;
 160
 161 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 162 // for scalar FP, as this allows more effective execution domain optimization.
 163 def FeaturePreferVMOVSR   : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 164                                              "true", "Prefer VMOVSR">;
 165
 166 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 167 // than ISH
 168 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 169                                                "true", "Prefer ISHST barriers">;
 170
 171 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 172 def FeatureMuxedUnits     : SubtargetFeature<"muxed-units", "HasMuxedUnits",
 173                                              "true",
 174                                              "Has muxed AGU and NEON/FPU">;
 175
 176 // Whether VLDM/VSTM starting with odd register number need more microops
 177 // than single VLDRS
 178 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 179                                               "true", "VLDM/VSTM starting "
 180                                               "with an odd register is slow">;
 181
 182 // Some targets have a renaming dependency when loading into D subregisters.
 183 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 184                                               "SlowLoadDSubregister", "true",
 185                                               "Loading into D subregs is slow">;
 186
 187 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 188 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 189                                              "DontWidenVMOVS", "true",
 190                                              "Don't widen VMOVS to VMOVD">;
 191
 192 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 193 def FeatureExpandMLx      : SubtargetFeature<"expand-fp-mlx",
 194                                              "ExpandMLx", "true",
 195                                              "Expand VFP/NEON MLA/MLS instructions">;
 196
 197 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 198 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 199                                              "true", "Has VMLx hazards">;
 200
 201 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 202 // VFP to NEON, as an execution domain optimization.
 203 def FeatureNEONForFPMovs  : SubtargetFeature<"neon-fpmovs",
 204                                              "UseNEONForFPMovs", "true",
 205                                              "Convert VMOVSR, VMOVRS, "
 206                                              "VMOVS to NEON">;
 207
 208 // Some processors benefit from using NEON instructions for scalar
 209 // single-precision FP operations. This affects instruction selection and should
 210 // only be enabled if the handling of denormals is not important.
 211 def FeatureNEONForFP      : SubtargetFeature<"neonfp",
 212                                              "UseNEONForSinglePrecisionFP",
 213                                              "true",
 214                                              "Use NEON for single precision FP">;
 215
 216 // On some processors, VLDn instructions that access unaligned data take one
 217 // extra cycle. Take that into account when computing operand latencies.
 218 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 219                                              "true",
 220                                              "Check for VLDn unaligned access">;
 221
 222 // Some processors have a nonpipelined VFP coprocessor.
 223 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 224                                               "NonpipelinedVFP", "true",
 225                                               "VFP instructions are not pipelined">;
 226
 227 // Some processors have FP multiply-accumulate instructions that don't
 228 // play nicely with other VFP / NEON instructions, and it's generally better
 229 // to just not use them.
 230 def FeatureHasSlowFPVMLx  : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 231                                              "Disable VFP / NEON MAC instructions">;
 232
 233 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 234 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 235                                              "HasVMLxForwarding", "true",
 236                                              "Has multiplier accumulator forwarding">;
 237
 238 // Disable 32-bit to 16-bit narrowing for experimentation.
 239 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 240                                              "Prefer 32-bit Thumb instrs">;
 241
 242 /// Some instructions update CPSR partially, which can add false dependency for
 243 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 244 /// mapped to a separate physical register. Avoid partial CPSR update for these
 245 /// processors.
 246 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 247                                                "AvoidCPSRPartialUpdate", "true",
 248                                  "Avoid CPSR partial update for OOO execution">;
 249
 250 /// Disable +1 predication cost for instructions updating CPSR.
 251 /// Enabled for Cortex-A57.
 252 def FeatureCheapPredicableCPSR : SubtargetFeature<"cheap-predicable-cpsr",
 253                                                   "CheapPredicableCPSRDef",
 254                                                   "true",
 255                   "Disable +1 predication cost for instructions updating CPSR">;
 256
 257 def FeatureAvoidMOVsShOp  : SubtargetFeature<"avoid-movs-shop",
 258                                              "AvoidMOVsShifterOperand", "true",
 259                                              "Avoid movs instructions with "
 260                                              "shifter operand">;
 261
 262 // Some processors perform return stack prediction. CodeGen should avoid issue
 263 // "normal" call instructions to callees which do not return.
 264 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack",
 265                                               "HasRetAddrStack", "true",
 266                                               "Has return address stack">;
 267
 268 // Some processors have no branch predictor, which changes the expected cost of
 269 // taking a branch which affects the choice of whether to use predicated
 270 // instructions.
 271 def FeatureHasNoBranchPredictor : SubtargetFeature<"no-branch-predictor",
 272                                                    "HasBranchPredictor", "false",
 273                                                    "Has no branch predictor">;
 274
 275 /// DSP extension.
 276 def FeatureDSP            : SubtargetFeature<"dsp", "HasDSP", "true",
 277                                              "Supports DSP instructions in "
 278                                              "ARM and/or Thumb2">;
 279
 280 // Multiprocessing extension.
 281 def FeatureMP             : SubtargetFeature<"mp", "HasMPExtension", "true",
 282                                         "Supports Multiprocessing extension">;
 283
 284 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 285 def FeatureVirtualization : SubtargetFeature<"virtualization",
 286                                              "HasVirtualization", "true",
 287                                              "Supports Virtualization extension",
 288                                              [FeatureHWDivThumb, FeatureHWDivARM]>;
 289
 290 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 291 // See ARMInstrInfo.td for details.
 292 def FeatureNaClTrap       : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 293                                              "NaCl trap">;
 294
 295 def FeatureStrictAlign    : SubtargetFeature<"strict-align",
 296                                              "StrictAlign", "true",
 297                                              "Disallow all unaligned memory "
 298                                              "access">;
 299
 300 def FeatureLongCalls      : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 301                                              "Generate calls via indirect call "
 302                                              "instructions">;
 303
 304 def FeatureExecuteOnly    : SubtargetFeature<"execute-only",
 305                                              "GenExecuteOnly", "true",
 306                                              "Enable the generation of "
 307                                              "execute only code.">;
 308
 309 def FeatureReserveR9      : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 310                                              "Reserve R9, making it unavailable"
 311                                              " as GPR">;
 312
 313 def FeatureNoMovt         : SubtargetFeature<"no-movt", "NoMovt", "true",
 314                                              "Don't use movt/movw pairs for "
 315                                              "32-bit imms">;
 316
 317 def FeatureNoNegativeImmediates
 318                           : SubtargetFeature<"no-neg-immediates",
 319                                              "NegativeImmediates", "false",
 320                                              "Convert immediates and instructions "
 321                                              "to their negated or complemented "
 322                                              "equivalent when the immediate does "
 323                                              "not fit in the encoding.">;
 324
 325 // Use the MachineScheduler for instruction scheduling for the subtarget.
 326 def FeatureUseMISched: SubtargetFeature<"use-misched", "UseMISched", "true",
 327                                         "Use the MachineScheduler">;
 328
 329 def FeatureNoPostRASched : SubtargetFeature<"disable-postra-scheduler",
 330     "DisablePostRAScheduler", "true",
 331     "Don't schedule again after register allocation">;
 332
 333 //===----------------------------------------------------------------------===//
 334 // ARM architecture class
 335 //
 336
 337 // A-series ISA
 338 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 339                                      "Is application profile ('A' series)">;
 340
 341 // R-series ISA
 342 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 343                                      "Is realtime profile ('R' series)">;
 344
 345 // M-series ISA
 346 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 347                                      "Is microcontroller profile ('M' series)">;
 348
 349
 350 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
 351                                      "Enable Thumb2 instructions">;
 352
 353 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
 354                                      "Does not support ARM mode execution">;
 355
 356 //===----------------------------------------------------------------------===//
 357 // ARM ISAa.
 358 //
 359
 360 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 361                                    "Support ARM v4T instructions">;
 362
 363 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 364                                    "Support ARM v5T instructions",
 365                                    [HasV4TOps]>;
 366
 367 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 368                                    "Support ARM v5TE, v5TEj, and "
 369                                    "v5TExp instructions",
 370                                    [HasV5TOps]>;
 371
 372 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 373                                    "Support ARM v6 instructions",
 374                                    [HasV5TEOps]>;
 375
 376 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 377                                    "Support ARM v6M instructions",
 378                                    [HasV6Ops]>;
 379
 380 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 381                                          "Support ARM v8M Baseline instructions",
 382                                          [HasV6MOps]>;
 383
 384 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 385                                    "Support ARM v6k instructions",
 386                                    [HasV6Ops]>;
 387
 388 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 389                                    "Support ARM v6t2 instructions",
 390                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 391
 392 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 393                                    "Support ARM v7 instructions",
 394                                    [HasV6T2Ops, FeaturePerfMon,
 395                                     FeatureV7Clrex]>;
 396
 397 def HasV8MMainlineOps :
 398                   SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 399                                    "Support ARM v8M Mainline instructions",
 400                                    [HasV7Ops]>;
 401
 402 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 403                                    "Support ARM v8 instructions",
 404                                    [HasV7Ops, FeatureAcquireRelease]>;
 405
 406 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 407                                    "Support ARM v8.1a instructions",
 408                                    [HasV8Ops]>;
 409
 410 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 411                                    "Support ARM v8.2a instructions",
 412                                    [HasV8_1aOps]>;
 413
 414 def HasV8_3aOps   : SubtargetFeature<"v8.3a", "HasV8_3aOps", "true",
 415                                    "Support ARM v8.3a instructions",
 416                                    [HasV8_2aOps]>;
 417
 418 //===----------------------------------------------------------------------===//
 419 // ARM Processor subtarget features.
 420 //
 421
 422 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 423                                    "Cortex-A5 ARM processors", []>;
 424 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 425                                    "Cortex-A7 ARM processors", []>;
 426 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 427                                    "Cortex-A8 ARM processors", []>;
 428 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 429                                    "Cortex-A9 ARM processors", []>;
 430 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 431                                    "Cortex-A12 ARM processors", []>;
 432 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 433                                    "Cortex-A15 ARM processors", []>;
 434 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 435                                    "Cortex-A17 ARM processors", []>;
 436 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 437                                    "Cortex-A32 ARM processors", []>;
 438 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 439                                    "Cortex-A35 ARM processors", []>;
 440 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 441                                    "Cortex-A53 ARM processors", []>;
 442 def ProcA55     : SubtargetFeature<"a55", "ARMProcFamily", "CortexA55",
 443                                    "Cortex-A55 ARM processors", []>;
 444 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 445                                    "Cortex-A57 ARM processors", []>;
 446 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 447                                    "Cortex-A72 ARM processors", []>;
 448 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 449                                    "Cortex-A73 ARM processors", []>;
 450 def ProcA75     : SubtargetFeature<"a75", "ARMProcFamily", "CortexA75",
 451                                    "Cortex-A75 ARM processors", []>;
 452
 453 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 454                                    "Qualcomm Krait processors", []>;
 455 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 456                                    "Qualcomm Kryo processors", []>;
 457 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 458                                    "Swift ARM processors", []>;
 459
 460 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 461                                     "Samsung Exynos-Mx processors", []>;
 462
 463 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 464                                    "Cortex-R4 ARM processors", []>;
 465 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 466                                    "Cortex-R5 ARM processors", []>;
 467 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 468                                    "Cortex-R7 ARM processors", []>;
 469 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 470                                    "Cortex-R52 ARM processors", []>;
 471
 472 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 473                                    "Cortex-M3 ARM processors", []>;
 474
 475
 476 //===----------------------------------------------------------------------===//
 477 // ARM Helper classes.
 478 //
 479
 480 class Architecture<string fname, string aname, list<SubtargetFeature> features>
 481   : SubtargetFeature<fname, "ARMArch", aname,
 482                      !strconcat(aname, " architecture"), features>;
 483
 484 class ProcNoItin<string Name, list<SubtargetFeature> Features>
 485   : Processor<Name, NoItineraries, Features>;
 486
 487
 488 //===----------------------------------------------------------------------===//
 489 // ARM architectures
 490 //
 491
 492 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 493
 494 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 495
 496 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 497
 498 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 499
 500 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 501
 502 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 503
 504 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 505
 506 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 507
 508 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 509
 510 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops]>;
 511
 512 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 513                                                        FeatureDSP]>;
 514
 515 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 516
 517 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 518                                                        FeatureTrustZone]>;
 519
 520 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 521                                                        FeatureNoARM,
 522                                                        ModeThumb,
 523                                                        FeatureDB,
 524                                                        FeatureMClass]>;
 525
 526 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 527                                                        FeatureNoARM,
 528                                                        ModeThumb,
 529                                                        FeatureDB,
 530                                                        FeatureMClass]>;
 531
 532 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 533                                                        FeatureNEON,
 534                                                        FeatureDB,
 535                                                        FeatureDSP,
 536                                                        FeatureAClass]>;
 537
 538 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 539                                                        FeatureNEON,
 540                                                        FeatureDB,
 541                                                        FeatureDSP,
 542                                                        FeatureTrustZone,
 543                                                        FeatureMP,
 544                                                        FeatureVirtualization,
 545                                                        FeatureAClass]>;
 546
 547 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 548                                                        FeatureDB,
 549                                                        FeatureDSP,
 550                                                        FeatureHWDivThumb,
 551                                                        FeatureRClass]>;
 552
 553 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 554                                                        FeatureThumb2,
 555                                                        FeatureNoARM,
 556                                                        ModeThumb,
 557                                                        FeatureDB,
 558                                                        FeatureHWDivThumb,
 559                                                        FeatureMClass]>;
 560
 561 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 562                                                        FeatureThumb2,
 563                                                        FeatureNoARM,
 564                                                        ModeThumb,
 565                                                        FeatureDB,
 566                                                        FeatureHWDivThumb,
 567                                                        FeatureMClass,
 568                                                        FeatureDSP]>;
 569
 570 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 571                                                        FeatureAClass,
 572                                                        FeatureDB,
 573                                                        FeatureFPARMv8,
 574                                                        FeatureNEON,
 575                                                        FeatureDSP,
 576                                                        FeatureTrustZone,
 577                                                        FeatureMP,
 578                                                        FeatureVirtualization,
 579                                                        FeatureCrypto,
 580                                                        FeatureCRC]>;
 581
 582 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 583                                                        FeatureAClass,
 584                                                        FeatureDB,
 585                                                        FeatureFPARMv8,
 586                                                        FeatureNEON,
 587                                                        FeatureDSP,
 588                                                        FeatureTrustZone,
 589                                                        FeatureMP,
 590                                                        FeatureVirtualization,
 591                                                        FeatureCrypto,
 592                                                        FeatureCRC]>;
 593
 594 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 595                                                        FeatureAClass,
 596                                                        FeatureDB,
 597                                                        FeatureFPARMv8,
 598                                                        FeatureNEON,
 599                                                        FeatureDSP,
 600                                                        FeatureTrustZone,
 601                                                        FeatureMP,
 602                                                        FeatureVirtualization,
 603                                                        FeatureCrypto,
 604                                                        FeatureCRC,
 605                                                        FeatureRAS]>;
 606
 607 def ARMv83a   : Architecture<"armv8.3-a", "ARMv83a",  [HasV8_3aOps,
 608                                                        FeatureAClass,
 609                                                        FeatureDB,
 610                                                        FeatureFPARMv8,
 611                                                        FeatureNEON,
 612                                                        FeatureDSP,
 613                                                        FeatureTrustZone,
 614                                                        FeatureMP,
 615                                                        FeatureVirtualization,
 616                                                        FeatureCrypto,
 617                                                        FeatureCRC,
 618                                                        FeatureRAS]>;
 619
 620 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 621                                                        FeatureRClass,
 622                                                        FeatureDB,
 623                                                        FeatureDFB,
 624                                                        FeatureDSP,
 625                                                        FeatureCRC,
 626                                                        FeatureMP,
 627                                                        FeatureVirtualization,
 628                                                        FeatureFPARMv8,
 629                                                        FeatureNEON]>;
 630
 631 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 632                                                       [HasV8MBaselineOps,
 633                                                        FeatureNoARM,
 634                                                        ModeThumb,
 635                                                        FeatureDB,
 636                                                        FeatureHWDivThumb,
 637                                                        FeatureV7Clrex,
 638                                                        Feature8MSecExt,
 639                                                        FeatureAcquireRelease,
 640                                                        FeatureMClass]>;
 641
 642 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 643                                                       [HasV8MMainlineOps,
 644                                                        FeatureNoARM,
 645                                                        ModeThumb,
 646                                                        FeatureDB,
 647                                                        FeatureHWDivThumb,
 648                                                        Feature8MSecExt,
 649                                                        FeatureAcquireRelease,
 650                                                        FeatureMClass]>;
 651
 652 // Aliases
 653 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 654 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 655 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 656 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 657 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 658 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 659
 660
 661 //===----------------------------------------------------------------------===//
 662 // ARM schedules.
 663 //===----------------------------------------------------------------------===//
 664 //
 665 include "ARMSchedule.td"
 666
 667 //===----------------------------------------------------------------------===//
 668 // ARM processors
 669 //
 670
 671 // Dummy CPU, used to target architectures
 672 def : ProcessorModel<"generic",     CortexA8Model,      []>;
 673
 674 // FIXME: Several processors below are not using their own scheduler
 675 // model, but one of similar/previous processor. These should be fixed.
 676
 677 def : ProcNoItin<"arm8",                                [ARMv4]>;
 678 def : ProcNoItin<"arm810",                              [ARMv4]>;
 679 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 680 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 681 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 682 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 683
 684 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 685 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 686 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 687 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 688 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 689 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 690 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 691 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 692 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 693 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 694 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 695
 696 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 697 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 698
 699 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 700 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 701 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 702 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 703 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 704 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 705 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 706 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 707 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 708 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 709
 710 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 711 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 712                                                          FeatureVFP2,
 713                                                          FeatureHasSlowFPVMLx]>;
 714
 715 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 716 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 717 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 718 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 719
 720 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 721 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 722 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 723                                                          FeatureVFP2,
 724                                                          FeatureHasSlowFPVMLx]>;
 725
 726 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 727 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 728                                                          FeatureVFP2,
 729                                                          FeatureHasSlowFPVMLx]>;
 730
 731 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 732 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 733                                                          FeatureVFP2,
 734                                                          FeatureHasSlowFPVMLx]>;
 735
 736 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 737                                                          FeatureHasRetAddrStack,
 738                                                          FeatureTrustZone,
 739                                                          FeatureSlowFPBrcc,
 740                                                          FeatureHasSlowFPVMLx,
 741                                                          FeatureVMLxForwarding,
 742                                                          FeatureMP,
 743                                                          FeatureVFP4]>;
 744
 745 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 746                                                          FeatureHasRetAddrStack,
 747                                                          FeatureTrustZone,
 748                                                          FeatureSlowFPBrcc,
 749                                                          FeatureHasVMLxHazards,
 750                                                          FeatureHasSlowFPVMLx,
 751                                                          FeatureVMLxForwarding,
 752                                                          FeatureMP,
 753                                                          FeatureVFP4,
 754                                                          FeatureVirtualization]>;
 755
 756 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 757                                                          FeatureHasRetAddrStack,
 758                                                          FeatureNonpipelinedVFP,
 759                                                          FeatureTrustZone,
 760                                                          FeatureSlowFPBrcc,
 761                                                          FeatureHasVMLxHazards,
 762                                                          FeatureHasSlowFPVMLx,
 763                                                          FeatureVMLxForwarding]>;
 764
 765 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 766                                                          FeatureHasRetAddrStack,
 767                                                          FeatureTrustZone,
 768                                                          FeatureHasVMLxHazards,
 769                                                          FeatureVMLxForwarding,
 770                                                          FeatureFP16,
 771                                                          FeatureAvoidPartialCPSR,
 772                                                          FeatureExpandMLx,
 773                                                          FeaturePreferVMOVSR,
 774                                                          FeatureMuxedUnits,
 775                                                          FeatureNEONForFPMovs,
 776                                                          FeatureCheckVLDnAlign,
 777                                                          FeatureMP]>;
 778
 779 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 780                                                          FeatureHasRetAddrStack,
 781                                                          FeatureTrustZone,
 782                                                          FeatureVMLxForwarding,
 783                                                          FeatureVFP4,
 784                                                          FeatureAvoidPartialCPSR,
 785                                                          FeatureVirtualization,
 786                                                          FeatureMP]>;
 787
 788 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 789                                                          FeatureDontWidenVMOVS,
 790                                                          FeatureHasRetAddrStack,
 791                                                          FeatureMuxedUnits,
 792                                                          FeatureTrustZone,
 793                                                          FeatureVFP4,
 794                                                          FeatureMP,
 795                                                          FeatureCheckVLDnAlign,
 796                                                          FeatureAvoidPartialCPSR,
 797                                                          FeatureVirtualization]>;
 798
 799 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 800                                                          FeatureHasRetAddrStack,
 801                                                          FeatureTrustZone,
 802                                                          FeatureMP,
 803                                                          FeatureVMLxForwarding,
 804                                                          FeatureVFP4,
 805                                                          FeatureAvoidPartialCPSR,
 806                                                          FeatureVirtualization]>;
 807
 808 // FIXME: krait has currently the same features as A9 plus VFP4 and  HWDiv
 809 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 810                                                          FeatureHasRetAddrStack,
 811                                                          FeatureMuxedUnits,
 812                                                          FeatureCheckVLDnAlign,
 813                                                          FeatureVMLxForwarding,
 814                                                          FeatureFP16,
 815                                                          FeatureAvoidPartialCPSR,
 816                                                          FeatureVFP4,
 817                                                          FeatureHWDivThumb,
 818                                                          FeatureHWDivARM]>;
 819
 820 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 821                                                          FeatureHasRetAddrStack,
 822                                                          FeatureNEONForFP,
 823                                                          FeatureVFP4,
 824                                                          FeatureMP,
 825                                                          FeatureHWDivThumb,
 826                                                          FeatureHWDivARM,
 827                                                          FeatureAvoidPartialCPSR,
 828                                                          FeatureAvoidMOVsShOp,
 829                                                          FeatureHasSlowFPVMLx,
 830                                                          FeatureHasVMLxHazards,
 831                                                          FeatureProfUnpredicate,
 832                                                          FeaturePrefISHSTBarrier,
 833                                                          FeatureSlowOddRegister,
 834                                                          FeatureSlowLoadDSubreg,
 835                                                          FeatureSlowVGETLNi32,
 836                                                          FeatureSlowVDUP32,
 837                                                          FeatureUseMISched,
 838                                                          FeatureNoPostRASched]>;
 839
 840 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 841                                                          FeatureHasRetAddrStack,
 842                                                          FeatureAvoidPartialCPSR]>;
 843
 844 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 845                                                          FeatureHasRetAddrStack,
 846                                                          FeatureSlowFPBrcc,
 847                                                          FeatureHasSlowFPVMLx,
 848                                                          FeatureVFP3,
 849                                                          FeatureD16,
 850                                                          FeatureAvoidPartialCPSR]>;
 851
 852 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 853                                                          FeatureHasRetAddrStack,
 854                                                          FeatureVFP3,
 855                                                          FeatureD16,
 856                                                          FeatureSlowFPBrcc,
 857                                                          FeatureHWDivARM,
 858                                                          FeatureHasSlowFPVMLx,
 859                                                          FeatureAvoidPartialCPSR]>;
 860
 861 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 862                                                          FeatureHasRetAddrStack,
 863                                                          FeatureVFP3,
 864                                                          FeatureD16,
 865                                                          FeatureFP16,
 866                                                          FeatureMP,
 867                                                          FeatureSlowFPBrcc,
 868                                                          FeatureHWDivARM,
 869                                                          FeatureHasSlowFPVMLx,
 870                                                          FeatureAvoidPartialCPSR]>;
 871
 872 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
 873                                                          FeatureHasRetAddrStack,
 874                                                          FeatureVFP3,
 875                                                          FeatureD16,
 876                                                          FeatureFP16,
 877                                                          FeatureMP,
 878                                                          FeatureSlowFPBrcc,
 879                                                          FeatureHWDivARM,
 880                                                          FeatureHasSlowFPVMLx,
 881                                                          FeatureAvoidPartialCPSR]>;
 882
 883 def : ProcessorModel<"cortex-m3", CortexM3Model,        [ARMv7m,
 884                                                          ProcM3,
 885                                                          FeatureHasNoBranchPredictor]>;
 886
 887 def : ProcessorModel<"sc300",     CortexM3Model,        [ARMv7m,
 888                                                          ProcM3,
 889                                                          FeatureHasNoBranchPredictor]>;
 890
 891 def : ProcessorModel<"cortex-m4", CortexM3Model,        [ARMv7em,
 892                                                          FeatureVFP4,
 893                                                          FeatureVFPOnlySP,
 894                                                          FeatureD16,
 895                                                          FeatureHasNoBranchPredictor]>;
 896
 897 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 898                                                          FeatureFPARMv8,
 899                                                          FeatureD16]>;
 900
 901 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
 902                                                          FeatureNoMovt]>;
 903
 904 def : ProcessorModel<"cortex-m33", CortexM3Model,       [ARMv8mMainline,
 905                                                          FeatureDSP,
 906                                                          FeatureFPARMv8,
 907                                                          FeatureD16,
 908                                                          FeatureVFPOnlySP,
 909                                                          FeatureHasNoBranchPredictor]>;
 910
 911 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
 912                                                          FeatureHWDivThumb,
 913                                                          FeatureHWDivARM,
 914                                                          FeatureCrypto,
 915                                                          FeatureCRC]>;
 916
 917 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
 918                                                          FeatureHWDivThumb,
 919                                                          FeatureHWDivARM,
 920                                                          FeatureCrypto,
 921                                                          FeatureCRC]>;
 922
 923 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
 924                                                          FeatureHWDivThumb,
 925                                                          FeatureHWDivARM,
 926                                                          FeatureCrypto,
 927                                                          FeatureCRC,
 928                                                          FeatureFPAO]>;
 929
 930 def : ProcNoItin<"cortex-a55",                          [ARMv82a, ProcA55,
 931                                                          FeatureHWDivThumb,
 932                                                          FeatureHWDivARM,
 933                                                          FeatureDotProd]>;
 934
 935 def : ProcessorModel<"cortex-a57",  CortexA57Model,     [ARMv8a, ProcA57,
 936                                                          FeatureHWDivThumb,
 937                                                          FeatureHWDivARM,
 938                                                          FeatureCrypto,
 939                                                          FeatureCRC,
 940                                                          FeatureFPAO,
 941                                                          FeatureAvoidPartialCPSR,
 942                                                          FeatureCheapPredicableCPSR]>;
 943
 944 def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
 945                                                          FeatureHWDivThumb,
 946                                                          FeatureHWDivARM,
 947                                                          FeatureCrypto,
 948                                                          FeatureCRC]>;
 949
 950 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
 951                                                          FeatureHWDivThumb,
 952                                                          FeatureHWDivARM,
 953                                                          FeatureCrypto,
 954                                                          FeatureCRC]>;
 955
 956 def : ProcNoItin<"cortex-a75",                          [ARMv82a, ProcA75,
 957                                                          FeatureHWDivThumb,
 958                                                          FeatureHWDivARM,
 959                                                          FeatureDotProd]>;
 960
 961 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
 962                                                          FeatureHasRetAddrStack,
 963                                                          FeatureNEONForFP,
 964                                                          FeatureVFP4,
 965                                                          FeatureMP,
 966                                                          FeatureHWDivThumb,
 967                                                          FeatureHWDivARM,
 968                                                          FeatureAvoidPartialCPSR,
 969                                                          FeatureAvoidMOVsShOp,
 970                                                          FeatureHasSlowFPVMLx,
 971                                                          FeatureCrypto,
 972                                                          FeatureUseMISched,
 973                                                          FeatureZCZeroing,
 974                                                          FeatureNoPostRASched]>;
 975
 976 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
 977                                                          FeatureHWDivThumb,
 978                                                          FeatureHWDivARM,
 979                                                          FeatureCrypto,
 980                                                          FeatureCRC]>;
 981
 982 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
 983                                                          FeatureHWDivThumb,
 984                                                          FeatureHWDivARM,
 985                                                          FeatureCrypto,
 986                                                          FeatureCRC]>;
 987
 988 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynosM1,
 989                                                          FeatureHWDivThumb,
 990                                                          FeatureHWDivARM,
 991                                                          FeatureCrypto,
 992                                                          FeatureCRC]>;
 993
 994 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
 995                                                          FeatureHWDivThumb,
 996                                                          FeatureHWDivARM,
 997                                                          FeatureCrypto,
 998                                                          FeatureCRC]>;
 999
1000 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
1001                                                          FeatureFPAO]>;
1002
1003 //===----------------------------------------------------------------------===//
1004 // Register File Description
1005 //===----------------------------------------------------------------------===//
1006
1007 include "ARMRegisterInfo.td"
1008 include "ARMRegisterBanks.td"
1009 include "ARMCallingConv.td"
1010
1011 //===----------------------------------------------------------------------===//
1012 // Instruction Descriptions
1013 //===----------------------------------------------------------------------===//
1014
1015 include "ARMInstrInfo.td"
1016 def ARMInstrInfo : InstrInfo;
1017
1018 //===----------------------------------------------------------------------===//
1019 // Declare the target which we are implementing
1020 //===----------------------------------------------------------------------===//
1021
1022 def ARMAsmWriter : AsmWriter {
1023   string AsmWriterClassName  = "InstPrinter";
1024   int PassSubtarget = 1;
1025   int Variant = 0;
1026   bit isMCAsmWriter = 1;
1027 }
1028
1029 def ARMAsmParser : AsmParser {
1030   bit ReportMultipleNearMisses = 1;
1031 }
1032
1033 def ARMAsmParserVariant : AsmParserVariant {
1034   int Variant = 0;
1035   string Name = "ARM";
1036   string BreakCharacters = ".";
1037 }
1038
1039 def ARM : Target {
1040   // Pull in Instruction Info.
1041   let InstructionSet = ARMInstrInfo;
1042   let AssemblyWriters = [ARMAsmWriter];
1043   let AssemblyParsers = [ARMAsmParser];
1044   let AssemblyParserVariants = [ARMAsmParserVariant];
1045 }