1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Helper classes.
23 class ProcNoItin<string Name, list<SubtargetFeature> Features>
24 : Processor<Name, NoItineraries, Features>;
26 class Architecture<string fname, string aname, list<SubtargetFeature> features >
27 : SubtargetFeature<fname, "ARMArch", aname,
28 !strconcat(aname, " architecture"), features>;
30 //===----------------------------------------------------------------------===//
31 // ARM Subtarget state.
34 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
37 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
38 "Use software floating point features.">;
40 //===----------------------------------------------------------------------===//
41 // ARM Subtarget features.
44 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
45 "Enable VFP2 instructions">;
46 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
47 "Enable VFP3 instructions",
49 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
50 "Enable NEON instructions",
52 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
53 "Enable Thumb2 instructions">;
54 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
55 "Does not support ARM mode execution",
57 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
58 "Enable half-precision floating point">;
59 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
60 "Enable VFP4 instructions",
61 [FeatureVFP3, FeatureFP16]>;
62 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
63 "true", "Enable ARMv8 FP",
65 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
66 "Enable full half-precision floating point",
68 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
69 "Restrict FP to 16 double registers">;
70 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
71 "Enable divide instructions">;
72 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
73 "HasHardwareDivideInARM", "true",
74 "Enable divide instructions in ARM mode">;
75 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
76 "Enable Thumb2 extract and pack instructions">;
77 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
78 "Has data barrier (dmb / dsb) instructions">;
79 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
80 "Has v7 clrex instruction">;
81 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
82 "HasAcquireRelease", "true",
83 "Has v8 acquire/release (lda/ldaex etc) instructions">;
84 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
85 "FP compare + branch is slow">;
86 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
87 "Floating point unit supports single precision only">;
88 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
89 "Enable support for Performance Monitor extensions">;
90 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
91 "Enable support for TrustZone security extensions">;
92 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
93 "Enable support for ARMv8-M Security Extensions">;
94 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
95 "Enable support for Cryptography extensions",
97 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
98 "Enable support for CRC instructions">;
99 // Not to be confused with FeatureHasRetAddrStack (return address stack)
100 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
101 "Enable Reliability, Availability and Serviceability extensions">;
102 def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
103 "Enable fast computation of positive address offsets">;
106 // Cyclone has preferred instructions for zeroing VFP registers, which can
107 // execute in 0 cycles.
108 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
109 "Has zero-cycle zeroing instructions">;
111 // Whether or not it may be profitable to unpredicate certain instructions
112 // during if conversion.
113 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
114 "IsProfitableToUnpredicate",
116 "Is profitable to unpredicate">;
118 // Some targets (e.g. Swift) have microcoded VGETLNi32.
119 def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
120 "HasSlowVGETLNi32", "true",
121 "Has slow VGETLNi32 - prefer VMOV">;
123 // Some targets (e.g. Swift) have microcoded VDUP32.
124 def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
125 "Has slow VDUP32 - prefer VMOV">;
127 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
128 // for scalar FP, as this allows more effective execution domain optimization.
129 def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
130 "true", "Prefer VMOVSR">;
132 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
134 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
135 "true", "Prefer ISHST barriers">;
137 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
138 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
139 "Has muxed AGU and NEON/FPU">;
141 // On some targets, a VLDM/VSTM starting with an odd register number needs more
142 // microops than single VLDRS.
143 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
144 "true", "VLDM/VSTM starting with an odd register is slow">;
146 // Some targets have a renaming dependency when loading into D subregisters.
147 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
148 "SlowLoadDSubregister", "true",
149 "Loading into D subregs is slow">;
150 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
151 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
152 "DontWidenVMOVS", "true",
153 "Don't widen VMOVS to VMOVD">;
155 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
156 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
157 "Expand VFP/NEON MLA/MLS instructions">;
159 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
160 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
161 "true", "Has VMLx hazards">;
163 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
164 // VFP to NEON, as an execution domain optimization.
165 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
166 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
168 // Some processors benefit from using NEON instructions for scalar
169 // single-precision FP operations. This affects instruction selection and should
170 // only be enabled if the handling of denormals is not important.
171 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
173 "Use NEON for single precision FP">;
175 // On some processors, VLDn instructions that access unaligned data take one
176 // extra cycle. Take that into account when computing operand latencies.
177 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
179 "Check for VLDn unaligned access">;
181 // Some processors have a nonpipelined VFP coprocessor.
182 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
183 "NonpipelinedVFP", "true",
184 "VFP instructions are not pipelined">;
186 // Some processors have FP multiply-accumulate instructions that don't
187 // play nicely with other VFP / NEON instructions, and it's generally better
188 // to just not use them.
189 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
190 "Disable VFP / NEON MAC instructions">;
192 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
193 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
194 "HasVMLxForwarding", "true",
195 "Has multiplier accumulator forwarding">;
197 // Disable 32-bit to 16-bit narrowing for experimentation.
198 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
199 "Prefer 32-bit Thumb instrs">;
201 /// Some instructions update CPSR partially, which can add false dependency for
202 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
203 /// mapped to a separate physical register. Avoid partial CPSR update for these
205 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
206 "AvoidCPSRPartialUpdate", "true",
207 "Avoid CPSR partial update for OOO execution">;
209 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
210 "AvoidMOVsShifterOperand", "true",
211 "Avoid movs instructions with shifter operand">;
213 // Some processors perform return stack prediction. CodeGen should avoid issue
214 // "normal" call instructions to callees which do not return.
215 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
216 "Has return address stack">;
219 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
220 "Supports DSP instructions in ARM and/or Thumb2">;
222 // Multiprocessing extension.
223 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
224 "Supports Multiprocessing extension">;
226 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
227 def FeatureVirtualization : SubtargetFeature<"virtualization",
228 "HasVirtualization", "true",
229 "Supports Virtualization extension",
230 [FeatureHWDiv, FeatureHWDivARM]>;
233 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
234 "Is microcontroller profile ('M' series)">;
237 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
238 "Is realtime profile ('R' series)">;
241 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
242 "Is application profile ('A' series)">;
244 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
245 // See ARMInstrInfo.td for details.
246 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
249 def FeatureStrictAlign : SubtargetFeature<"strict-align",
250 "StrictAlign", "true",
251 "Disallow all unaligned memory "
254 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
255 "Generate calls via indirect call "
258 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
259 "Reserve R9, making it unavailable as "
262 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
263 "Don't use movt/movw pairs for 32-bit "
267 //===----------------------------------------------------------------------===//
271 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
272 "Support ARM v4T instructions">;
273 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
274 "Support ARM v5T instructions",
276 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
277 "Support ARM v5TE, v5TEj, and v5TExp instructions",
279 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
280 "Support ARM v6 instructions",
282 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
283 "Support ARM v6M instructions",
285 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
286 "Support ARM v8M Baseline instructions",
288 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
289 "Support ARM v6k instructions",
291 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
292 "Support ARM v6t2 instructions",
293 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
294 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
295 "Support ARM v7 instructions",
296 [HasV6T2Ops, FeaturePerfMon,
298 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
299 "Support ARM v8 instructions",
300 [HasV7Ops, FeatureAcquireRelease,
302 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
303 "Support ARM v8.1a instructions",
305 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
306 "Support ARM v8.2a instructions",
308 def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
309 "Support ARM v8M Mainline instructions",
313 //===----------------------------------------------------------------------===//
314 // ARM Processor subtarget features.
317 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
318 "Cortex-A5 ARM processors", []>;
319 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
320 "Cortex-A7 ARM processors", []>;
321 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
322 "Cortex-A8 ARM processors", []>;
323 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
324 "Cortex-A9 ARM processors", []>;
325 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
326 "Cortex-A12 ARM processors", []>;
327 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
328 "Cortex-A15 ARM processors", []>;
329 def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
330 "Cortex-A17 ARM processors", []>;
331 def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
332 "Cortex-A32 ARM processors", []>;
333 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
334 "Cortex-A35 ARM processors", []>;
335 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
336 "Cortex-A53 ARM processors", []>;
337 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
338 "Cortex-A57 ARM processors", []>;
339 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
340 "Cortex-A72 ARM processors", []>;
341 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
342 "Cortex-A73 ARM processors", []>;
344 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
345 "Qualcomm ARM processors", []>;
346 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
347 "Swift ARM processors", []>;
349 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
350 "Samsung Exynos-M1 processors", []>;
352 def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
353 "Cortex-R4 ARM processors", []>;
354 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
355 "Cortex-R5 ARM processors", []>;
356 def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
357 "Cortex-R7 ARM processors", []>;
358 def ProcR52 : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
359 "Cortex-R52 ARM processors", []>;
361 def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
362 "Cortex-M3 ARM processors", []>;
364 //===----------------------------------------------------------------------===//
368 include "ARMSchedule.td"
371 //===----------------------------------------------------------------------===//
375 def ARMv2 : Architecture<"armv2", "ARMv2", []>;
377 def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
379 def ARMv3 : Architecture<"armv3", "ARMv3", []>;
381 def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
383 def ARMv4 : Architecture<"armv4", "ARMv4", []>;
385 def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
387 def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
389 def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
391 def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
393 def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
395 def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
399 def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
401 def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
404 def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
409 def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
414 def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
421 def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
428 def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
435 def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
444 def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
452 FeatureVirtualization,
456 def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
464 FeatureVirtualization,
468 def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
476 FeatureVirtualization,
481 def ARMv8r : Architecture<"armv8-r", "ARMv8r", [HasV8Ops,
490 FeatureVirtualization,
494 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
501 FeatureAcquireRelease,
504 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
510 FeatureAcquireRelease,
514 def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
515 def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
516 def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
517 def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
518 def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
519 def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
522 //===----------------------------------------------------------------------===//
526 // Dummy CPU, used to target architectures
527 def : ProcNoItin<"generic", []>;
529 def : ProcNoItin<"arm8", [ARMv4]>;
530 def : ProcNoItin<"arm810", [ARMv4]>;
531 def : ProcNoItin<"strongarm", [ARMv4]>;
532 def : ProcNoItin<"strongarm110", [ARMv4]>;
533 def : ProcNoItin<"strongarm1100", [ARMv4]>;
534 def : ProcNoItin<"strongarm1110", [ARMv4]>;
536 def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
537 def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
538 def : ProcNoItin<"arm710t", [ARMv4t]>;
539 def : ProcNoItin<"arm720t", [ARMv4t]>;
540 def : ProcNoItin<"arm9", [ARMv4t]>;
541 def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
542 def : ProcNoItin<"arm920", [ARMv4t]>;
543 def : ProcNoItin<"arm920t", [ARMv4t]>;
544 def : ProcNoItin<"arm922t", [ARMv4t]>;
545 def : ProcNoItin<"arm940t", [ARMv4t]>;
546 def : ProcNoItin<"ep9312", [ARMv4t]>;
548 def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
549 def : ProcNoItin<"arm1020t", [ARMv5t]>;
551 def : ProcNoItin<"arm9e", [ARMv5te]>;
552 def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
553 def : ProcNoItin<"arm946e-s", [ARMv5te]>;
554 def : ProcNoItin<"arm966e-s", [ARMv5te]>;
555 def : ProcNoItin<"arm968e-s", [ARMv5te]>;
556 def : ProcNoItin<"arm10e", [ARMv5te]>;
557 def : ProcNoItin<"arm1020e", [ARMv5te]>;
558 def : ProcNoItin<"arm1022e", [ARMv5te]>;
559 def : ProcNoItin<"xscale", [ARMv5te]>;
560 def : ProcNoItin<"iwmmxt", [ARMv5te]>;
562 def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
563 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
565 FeatureHasSlowFPVMLx]>;
567 def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
568 def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
569 def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
570 def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
572 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
573 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
575 FeatureHasSlowFPVMLx]>;
577 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
578 def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
580 FeatureHasSlowFPVMLx]>;
582 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
583 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
585 FeatureHasSlowFPVMLx]>;
587 // FIXME: A5 has currently the same Schedule model as A8
588 def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
589 FeatureHasRetAddrStack,
592 FeatureHasSlowFPVMLx,
593 FeatureVMLxForwarding,
597 def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
598 FeatureHasRetAddrStack,
601 FeatureHasVMLxHazards,
602 FeatureHasSlowFPVMLx,
603 FeatureVMLxForwarding,
608 FeatureVirtualization]>;
610 def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
611 FeatureHasRetAddrStack,
612 FeatureNonpipelinedVFP,
615 FeatureHasVMLxHazards,
616 FeatureHasSlowFPVMLx,
617 FeatureVMLxForwarding]>;
619 def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
620 FeatureHasRetAddrStack,
622 FeatureHasVMLxHazards,
623 FeatureVMLxForwarding,
625 FeatureAvoidPartialCPSR,
629 FeatureNEONForFPMovs,
630 FeatureCheckVLDnAlign,
633 // FIXME: A12 has currently the same Schedule model as A9
634 def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
635 FeatureHasRetAddrStack,
637 FeatureVMLxForwarding,
641 FeatureAvoidPartialCPSR,
642 FeatureVirtualization,
645 // FIXME: A15 has currently the same Schedule model as A9.
646 def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
647 FeatureDontWidenVMOVS,
648 FeatureHasRetAddrStack,
653 FeatureCheckVLDnAlign,
656 FeatureAvoidPartialCPSR,
657 FeatureVirtualization]>;
659 // FIXME: A17 has currently the same Schedule model as A9
660 def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
661 FeatureHasRetAddrStack,
664 FeatureVMLxForwarding,
668 FeatureAvoidPartialCPSR,
669 FeatureVirtualization]>;
671 // FIXME: krait has currently the same Schedule model as A9
672 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
673 // division features.
674 def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
675 FeatureHasRetAddrStack,
677 FeatureCheckVLDnAlign,
678 FeatureVMLxForwarding,
680 FeatureAvoidPartialCPSR,
685 def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
686 FeatureHasRetAddrStack,
692 FeatureAvoidPartialCPSR,
693 FeatureAvoidMOVsShOp,
694 FeatureHasSlowFPVMLx,
695 FeatureHasVMLxHazards,
696 FeatureProfUnpredicate,
697 FeaturePrefISHSTBarrier,
698 FeatureSlowOddRegister,
699 FeatureSlowLoadDSubreg,
700 FeatureSlowVGETLNi32,
703 // FIXME: R4 has currently the same ProcessorModel as A8.
704 def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
705 FeatureHasRetAddrStack,
706 FeatureAvoidPartialCPSR]>;
708 // FIXME: R4F has currently the same ProcessorModel as A8.
709 def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
710 FeatureHasRetAddrStack,
712 FeatureHasSlowFPVMLx,
715 FeatureAvoidPartialCPSR]>;
717 // FIXME: R5 has currently the same ProcessorModel as A8.
718 def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
719 FeatureHasRetAddrStack,
724 FeatureHasSlowFPVMLx,
725 FeatureAvoidPartialCPSR]>;
727 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
728 def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
729 FeatureHasRetAddrStack,
736 FeatureHasSlowFPVMLx,
737 FeatureAvoidPartialCPSR]>;
739 def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
740 FeatureHasRetAddrStack,
747 FeatureHasSlowFPVMLx,
748 FeatureAvoidPartialCPSR]>;
750 def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
751 def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
753 def : ProcNoItin<"cortex-m4", [ARMv7em,
758 def : ProcNoItin<"cortex-m7", [ARMv7em,
762 def : ProcNoItin<"cortex-a32", [ARMv8a,
768 def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
774 def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
781 def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
788 def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
794 def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
800 // Cyclone is very similar to swift
801 def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
802 FeatureHasRetAddrStack,
808 FeatureAvoidPartialCPSR,
809 FeatureAvoidMOVsShOp,
810 FeatureHasSlowFPVMLx,
814 def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
820 def : ProcNoItin<"exynos-m2", [ARMv8a, ProcExynosM1,
826 def : ProcNoItin<"exynos-m3", [ARMv8a, ProcExynosM1,
832 def : ProcessorModel<"cortex-r52", CortexR52Model, [ARMv8r, ProcR52,
835 //===----------------------------------------------------------------------===//
836 // Register File Description
837 //===----------------------------------------------------------------------===//
839 include "ARMRegisterInfo.td"
841 include "ARMCallingConv.td"
843 //===----------------------------------------------------------------------===//
844 // Instruction Descriptions
845 //===----------------------------------------------------------------------===//
847 include "ARMInstrInfo.td"
849 def ARMInstrInfo : InstrInfo;
851 //===----------------------------------------------------------------------===//
852 // Declare the target which we are implementing
853 //===----------------------------------------------------------------------===//
855 def ARMAsmWriter : AsmWriter {
856 string AsmWriterClassName = "InstPrinter";
857 int PassSubtarget = 1;
859 bit isMCAsmWriter = 1;
862 def ARMAsmParserVariant : AsmParserVariant {
865 string BreakCharacters = ".";
869 // Pull in Instruction Info:
870 let InstructionSet = ARMInstrInfo;
871 let AssemblyWriters = [ARMAsmWriter];
872 let AssemblyParserVariants = [ARMAsmParserVariant];