contrib/llvm/lib/Target/ARM/ARM.td

   1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 //
  11 //===----------------------------------------------------------------------===//
  12
  13 //===----------------------------------------------------------------------===//
  14 // Target-independent interfaces which we are implementing
  15 //===----------------------------------------------------------------------===//
  16
  17 include "llvm/Target/Target.td"
  18
  19 //===----------------------------------------------------------------------===//
  20 // ARM Helper classes.
  21 //
  22
  23 class ProcNoItin<string Name, list<SubtargetFeature> Features>
  24  : Processor<Name, NoItineraries, Features>;
  25
  26 class Architecture<string fname, string aname, list<SubtargetFeature> features >
  27   : SubtargetFeature<fname, "ARMArch", aname,
  28                      !strconcat(aname, " architecture"), features>;
  29
  30 //===----------------------------------------------------------------------===//
  31 // ARM Subtarget state.
  32 //
  33
  34 def ModeThumb  : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
  35                                   "Thumb mode">;
  36
  37 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
  38                                      "Use software floating point features.">;
  39
  40 //===----------------------------------------------------------------------===//
  41 // ARM Subtarget features.
  42 //
  43
  44 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
  45                                    "Enable VFP2 instructions">;
  46 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
  47                                    "Enable VFP3 instructions",
  48                                    [FeatureVFP2]>;
  49 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
  50                                    "Enable NEON instructions",
  51                                    [FeatureVFP3]>;
  52 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
  53                                      "Enable Thumb2 instructions">;
  54 def FeatureNoARM  : SubtargetFeature<"noarm", "NoARM", "true",
  55                                      "Does not support ARM mode execution",
  56                                      [ModeThumb]>;
  57 def FeatureFP16   : SubtargetFeature<"fp16", "HasFP16", "true",
  58                                      "Enable half-precision floating point">;
  59 def FeatureVFP4   : SubtargetFeature<"vfp4", "HasVFPv4", "true",
  60                                      "Enable VFP4 instructions",
  61                                      [FeatureVFP3, FeatureFP16]>;
  62 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
  63                                    "true", "Enable ARMv8 FP",
  64                                    [FeatureVFP4]>;
  65 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
  66                                        "Enable full half-precision floating point",
  67                                        [FeatureFPARMv8]>;
  68 def FeatureD16    : SubtargetFeature<"d16", "HasD16", "true",
  69                                      "Restrict FP to 16 double registers">;
  70 def FeatureHWDivThumb : SubtargetFeature<"hwdiv", "HasHardwareDivideInThumb",
  71                                          "true",
  72                                          "Enable divide instructions in Thumb">;
  73 def FeatureHWDivARM  : SubtargetFeature<"hwdiv-arm",
  74                                         "HasHardwareDivideInARM", "true",
  75                                       "Enable divide instructions in ARM mode">;
  76 def FeatureDB     : SubtargetFeature<"db", "HasDataBarrier", "true",
  77                                    "Has data barrier (dmb / dsb) instructions">;
  78 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
  79                                       "Has v7 clrex instruction">;
  80 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
  81                                              "HasAcquireRelease", "true",
  82                          "Has v8 acquire/release (lda/ldaex etc) instructions">;
  83 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
  84                                          "FP compare + branch is slow">;
  85 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
  86                           "Floating point unit supports single precision only">;
  87 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
  88                            "Enable support for Performance Monitor extensions">;
  89 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
  90                           "Enable support for TrustZone security extensions">;
  91 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
  92                           "Enable support for ARMv8-M Security Extensions">;
  93 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
  94                           "Enable support for Cryptography extensions",
  95                           [FeatureNEON]>;
  96 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
  97                           "Enable support for CRC instructions">;
  98 // Not to be confused with FeatureHasRetAddrStack (return address stack)
  99 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
 100                 "Enable Reliability, Availability and Serviceability extensions">;
 101 def FeatureFPAO : SubtargetFeature<"fpao", "HasFPAO", "true",
 102                 "Enable fast computation of positive address offsets">;
 103
 104
 105 // Cyclone has preferred instructions for zeroing VFP registers, which can
 106 // execute in 0 cycles.
 107 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
 108                                         "Has zero-cycle zeroing instructions">;
 109
 110 // Whether or not it may be profitable to unpredicate certain instructions
 111 // during if conversion.
 112 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
 113                                               "IsProfitableToUnpredicate",
 114                                               "true",
 115                                               "Is profitable to unpredicate">;
 116
 117 // Some targets (e.g. Swift) have microcoded VGETLNi32.
 118 def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
 119                                             "HasSlowVGETLNi32", "true",
 120                                             "Has slow VGETLNi32 - prefer VMOV">;
 121
 122 // Some targets (e.g. Swift) have microcoded VDUP32.
 123 def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
 124                                          "Has slow VDUP32 - prefer VMOV">;
 125
 126 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
 127 // for scalar FP, as this allows more effective execution domain optimization.
 128 def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
 129                                            "true", "Prefer VMOVSR">;
 130
 131 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
 132 // than ISH
 133 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
 134                                            "true", "Prefer ISHST barriers">;
 135
 136 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
 137 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
 138                                          "Has muxed AGU and NEON/FPU">;
 139
 140 // On some targets, a VLDM/VSTM starting with an odd register number needs more
 141 // microops than single VLDRS.
 142 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
 143                      "true", "VLDM/VSTM starting with an odd register is slow">;
 144
 145 // Some targets have a renaming dependency when loading into D subregisters.
 146 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
 147                                               "SlowLoadDSubregister", "true",
 148                                               "Loading into D subregs is slow">;
 149 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
 150 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
 151                                              "DontWidenVMOVS", "true",
 152                                              "Don't widen VMOVS to VMOVD">;
 153
 154 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
 155 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
 156                                         "Expand VFP/NEON MLA/MLS instructions">;
 157
 158 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
 159 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
 160                                              "true", "Has VMLx hazards">;
 161
 162 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
 163 // VFP to NEON, as an execution domain optimization.
 164 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
 165                               "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
 166
 167 // Some processors benefit from using NEON instructions for scalar
 168 // single-precision FP operations. This affects instruction selection and should
 169 // only be enabled if the handling of denormals is not important.
 170 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
 171                                         "true",
 172                                         "Use NEON for single precision FP">;
 173
 174 // On some processors, VLDn instructions that access unaligned data take one
 175 // extra cycle. Take that into account when computing operand latencies.
 176 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
 177                                              "true",
 178                                              "Check for VLDn unaligned access">;
 179
 180 // Some processors have a nonpipelined VFP coprocessor.
 181 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
 182                                               "NonpipelinedVFP", "true",
 183                                           "VFP instructions are not pipelined">;
 184
 185 // Some processors have FP multiply-accumulate instructions that don't
 186 // play nicely with other VFP / NEON instructions, and it's generally better
 187 // to just not use them.
 188 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
 189                                          "Disable VFP / NEON MAC instructions">;
 190
 191 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
 192 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
 193                                        "HasVMLxForwarding", "true",
 194                                        "Has multiplier accumulator forwarding">;
 195
 196 // Disable 32-bit to 16-bit narrowing for experimentation.
 197 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
 198                                              "Prefer 32-bit Thumb instrs">;
 199
 200 /// Some instructions update CPSR partially, which can add false dependency for
 201 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
 202 /// mapped to a separate physical register. Avoid partial CPSR update for these
 203 /// processors.
 204 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
 205                                                "AvoidCPSRPartialUpdate", "true",
 206                                  "Avoid CPSR partial update for OOO execution">;
 207
 208 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
 209                                             "AvoidMOVsShifterOperand", "true",
 210                                 "Avoid movs instructions with shifter operand">;
 211
 212 // Some processors perform return stack prediction. CodeGen should avoid issue
 213 // "normal" call instructions to callees which do not return.
 214 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
 215                                      "Has return address stack">;
 216
 217 /// DSP extension.
 218 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
 219                               "Supports DSP instructions in ARM and/or Thumb2">;
 220
 221 // Multiprocessing extension.
 222 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
 223                                  "Supports Multiprocessing extension">;
 224
 225 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
 226 def FeatureVirtualization : SubtargetFeature<"virtualization",
 227                                  "HasVirtualization", "true",
 228                                  "Supports Virtualization extension",
 229                                  [FeatureHWDivThumb, FeatureHWDivARM]>;
 230
 231 // M-series ISA
 232 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
 233                                      "Is microcontroller profile ('M' series)">;
 234
 235 // R-series ISA
 236 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
 237                                      "Is realtime profile ('R' series)">;
 238
 239 // A-series ISA
 240 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
 241                                      "Is application profile ('A' series)">;
 242
 243 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
 244 // See ARMInstrInfo.td for details.
 245 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
 246                                        "NaCl trap">;
 247
 248 def FeatureStrictAlign : SubtargetFeature<"strict-align",
 249                                           "StrictAlign", "true",
 250                                           "Disallow all unaligned memory "
 251                                           "access">;
 252
 253 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
 254                                         "Generate calls via indirect call "
 255                                         "instructions">;
 256
 257 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
 258                                         "Reserve R9, making it unavailable as "
 259                                         "GPR">;
 260
 261 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
 262                                      "Don't use movt/movw pairs for 32-bit "
 263                                      "imms">;
 264
 265 def FeatureNoNegativeImmediates : SubtargetFeature<"no-neg-immediates",
 266                                         "NegativeImmediates", "false",
 267                                         "Convert immediates and instructions "
 268                                         "to their negated or complemented "
 269                                         "equivalent when the immediate does "
 270                                         "not fit in the encoding.">;
 271
 272 //===----------------------------------------------------------------------===//
 273 // ARM ISAa.
 274 //
 275
 276 def HasV4TOps   : SubtargetFeature<"v4t", "HasV4TOps", "true",
 277                                    "Support ARM v4T instructions">;
 278 def HasV5TOps   : SubtargetFeature<"v5t", "HasV5TOps", "true",
 279                                    "Support ARM v5T instructions",
 280                                    [HasV4TOps]>;
 281 def HasV5TEOps  : SubtargetFeature<"v5te", "HasV5TEOps", "true",
 282                              "Support ARM v5TE, v5TEj, and v5TExp instructions",
 283                                    [HasV5TOps]>;
 284 def HasV6Ops    : SubtargetFeature<"v6", "HasV6Ops", "true",
 285                                    "Support ARM v6 instructions",
 286                                    [HasV5TEOps]>;
 287 def HasV6MOps   : SubtargetFeature<"v6m", "HasV6MOps", "true",
 288                                    "Support ARM v6M instructions",
 289                                    [HasV6Ops]>;
 290 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
 291                                          "Support ARM v8M Baseline instructions",
 292                                          [HasV6MOps]>;
 293 def HasV6KOps   : SubtargetFeature<"v6k", "HasV6KOps", "true",
 294                                    "Support ARM v6k instructions",
 295                                    [HasV6Ops]>;
 296 def HasV6T2Ops  : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
 297                                    "Support ARM v6t2 instructions",
 298                                    [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
 299 def HasV7Ops    : SubtargetFeature<"v7", "HasV7Ops", "true",
 300                                    "Support ARM v7 instructions",
 301                                    [HasV6T2Ops, FeaturePerfMon,
 302                                     FeatureV7Clrex]>;
 303 def HasV8Ops    : SubtargetFeature<"v8", "HasV8Ops", "true",
 304                                    "Support ARM v8 instructions",
 305                                    [HasV7Ops, FeatureAcquireRelease]>;
 306 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
 307                                    "Support ARM v8.1a instructions",
 308                                    [HasV8Ops]>;
 309 def HasV8_2aOps   : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
 310                                    "Support ARM v8.2a instructions",
 311                                    [HasV8_1aOps]>;
 312 def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
 313                                          "Support ARM v8M Mainline instructions",
 314                                          [HasV7Ops]>;
 315
 316
 317 //===----------------------------------------------------------------------===//
 318 // ARM Processor subtarget features.
 319 //
 320
 321 def ProcA5      : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
 322                                    "Cortex-A5 ARM processors", []>;
 323 def ProcA7      : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
 324                                    "Cortex-A7 ARM processors", []>;
 325 def ProcA8      : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
 326                                    "Cortex-A8 ARM processors", []>;
 327 def ProcA9      : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
 328                                    "Cortex-A9 ARM processors", []>;
 329 def ProcA12     : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
 330                                    "Cortex-A12 ARM processors", []>;
 331 def ProcA15     : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
 332                                    "Cortex-A15 ARM processors", []>;
 333 def ProcA17     : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
 334                                    "Cortex-A17 ARM processors", []>;
 335 def ProcA32     : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
 336                                    "Cortex-A32 ARM processors", []>;
 337 def ProcA35     : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
 338                                    "Cortex-A35 ARM processors", []>;
 339 def ProcA53     : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
 340                                    "Cortex-A53 ARM processors", []>;
 341 def ProcA57     : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
 342                                    "Cortex-A57 ARM processors", []>;
 343 def ProcA72     : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
 344                                    "Cortex-A72 ARM processors", []>;
 345 def ProcA73     : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
 346                                    "Cortex-A73 ARM processors", []>;
 347
 348 def ProcKrait   : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
 349                                    "Qualcomm Krait processors", []>;
 350 def ProcKryo    : SubtargetFeature<"kryo", "ARMProcFamily", "Kryo",
 351                                    "Qualcomm Kryo processors", []>;
 352 def ProcSwift   : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
 353                                    "Swift ARM processors", []>;
 354
 355 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
 356                                     "Samsung Exynos-M1 processors", []>;
 357
 358 def ProcR4      : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
 359                                    "Cortex-R4 ARM processors", []>;
 360 def ProcR5      : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
 361                                    "Cortex-R5 ARM processors", []>;
 362 def ProcR7      : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
 363                                    "Cortex-R7 ARM processors", []>;
 364 def ProcR52     : SubtargetFeature<"r52", "ARMProcFamily", "CortexR52",
 365                                    "Cortex-R52 ARM processors", []>;
 366
 367 def ProcM3      : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
 368                                    "Cortex-M3 ARM processors", []>;
 369
 370 //===----------------------------------------------------------------------===//
 371 // ARM schedules.
 372 //
 373
 374 include "ARMSchedule.td"
 375
 376
 377 //===----------------------------------------------------------------------===//
 378 // ARM architectures
 379 //
 380
 381 def ARMv2     : Architecture<"armv2",     "ARMv2",    []>;
 382
 383 def ARMv2a    : Architecture<"armv2a",    "ARMv2a",   []>;
 384
 385 def ARMv3     : Architecture<"armv3",     "ARMv3",    []>;
 386
 387 def ARMv3m    : Architecture<"armv3m",    "ARMv3m",   []>;
 388
 389 def ARMv4     : Architecture<"armv4",     "ARMv4",    []>;
 390
 391 def ARMv4t    : Architecture<"armv4t",    "ARMv4t",   [HasV4TOps]>;
 392
 393 def ARMv5t    : Architecture<"armv5t",    "ARMv5t",   [HasV5TOps]>;
 394
 395 def ARMv5te   : Architecture<"armv5te",   "ARMv5te",  [HasV5TEOps]>;
 396
 397 def ARMv5tej  : Architecture<"armv5tej",  "ARMv5tej", [HasV5TEOps]>;
 398
 399 def ARMv6     : Architecture<"armv6",     "ARMv6",    [HasV6Ops]>;
 400
 401 def ARMv6t2   : Architecture<"armv6t2",   "ARMv6t2",  [HasV6T2Ops,
 402                                                        FeatureDSP]>;
 403
 404 def ARMv6k    : Architecture<"armv6k",    "ARMv6k",   [HasV6KOps]>;
 405
 406 def ARMv6kz   : Architecture<"armv6kz",   "ARMv6kz",  [HasV6KOps,
 407                                                        FeatureTrustZone]>;
 408
 409 def ARMv6m    : Architecture<"armv6-m",   "ARMv6m",   [HasV6MOps,
 410                                                        FeatureNoARM,
 411                                                        FeatureDB,
 412                                                        FeatureMClass]>;
 413
 414 def ARMv6sm   : Architecture<"armv6s-m",  "ARMv6sm",  [HasV6MOps,
 415                                                        FeatureNoARM,
 416                                                        FeatureDB,
 417                                                        FeatureMClass]>;
 418
 419 def ARMv7a    : Architecture<"armv7-a",   "ARMv7a",   [HasV7Ops,
 420                                                        FeatureNEON,
 421                                                        FeatureDB,
 422                                                        FeatureDSP,
 423                                                        FeatureAClass]>;
 424
 425 def ARMv7ve   : Architecture<"armv7ve",   "ARMv7ve",  [HasV7Ops,
 426                                                        FeatureNEON,
 427                                                        FeatureDB,
 428                                                        FeatureDSP,
 429                                                        FeatureTrustZone,
 430                                                        FeatureMP,
 431                                                        FeatureVirtualization,
 432                                                        FeatureAClass]>;
 433
 434 def ARMv7r    : Architecture<"armv7-r",   "ARMv7r",   [HasV7Ops,
 435                                                        FeatureDB,
 436                                                        FeatureDSP,
 437                                                        FeatureHWDivThumb,
 438                                                        FeatureRClass]>;
 439
 440 def ARMv7m    : Architecture<"armv7-m",   "ARMv7m",   [HasV7Ops,
 441                                                        FeatureThumb2,
 442                                                        FeatureNoARM,
 443                                                        FeatureDB,
 444                                                        FeatureHWDivThumb,
 445                                                        FeatureMClass]>;
 446
 447 def ARMv7em   : Architecture<"armv7e-m",  "ARMv7em",  [HasV7Ops,
 448                                                        FeatureThumb2,
 449                                                        FeatureNoARM,
 450                                                        FeatureDB,
 451                                                        FeatureHWDivThumb,
 452                                                        FeatureMClass,
 453                                                        FeatureDSP]>;
 454
 455 def ARMv8a    : Architecture<"armv8-a",   "ARMv8a",   [HasV8Ops,
 456                                                        FeatureAClass,
 457                                                        FeatureDB,
 458                                                        FeatureFPARMv8,
 459                                                        FeatureNEON,
 460                                                        FeatureDSP,
 461                                                        FeatureTrustZone,
 462                                                        FeatureMP,
 463                                                        FeatureVirtualization,
 464                                                        FeatureCrypto,
 465                                                        FeatureCRC]>;
 466
 467 def ARMv81a   : Architecture<"armv8.1-a", "ARMv81a",  [HasV8_1aOps,
 468                                                        FeatureAClass,
 469                                                        FeatureDB,
 470                                                        FeatureFPARMv8,
 471                                                        FeatureNEON,
 472                                                        FeatureDSP,
 473                                                        FeatureTrustZone,
 474                                                        FeatureMP,
 475                                                        FeatureVirtualization,
 476                                                        FeatureCrypto,
 477                                                        FeatureCRC]>;
 478
 479 def ARMv82a   : Architecture<"armv8.2-a", "ARMv82a",  [HasV8_2aOps,
 480                                                        FeatureAClass,
 481                                                        FeatureDB,
 482                                                        FeatureFPARMv8,
 483                                                        FeatureNEON,
 484                                                        FeatureDSP,
 485                                                        FeatureTrustZone,
 486                                                        FeatureMP,
 487                                                        FeatureVirtualization,
 488                                                        FeatureCrypto,
 489                                                        FeatureCRC,
 490                                                        FeatureRAS]>;
 491
 492 def ARMv8r    : Architecture<"armv8-r",   "ARMv8r",   [HasV8Ops,
 493                                                        FeatureRClass,
 494                                                        FeatureDB,
 495                                                        FeatureDSP,
 496                                                        FeatureCRC,
 497                                                        FeatureMP,
 498                                                        FeatureVirtualization,
 499                                                        FeatureFPARMv8,
 500                                                        FeatureNEON]>;
 501
 502 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
 503                                                       [HasV8MBaselineOps,
 504                                                        FeatureNoARM,
 505                                                        FeatureDB,
 506                                                        FeatureHWDivThumb,
 507                                                        FeatureV7Clrex,
 508                                                        Feature8MSecExt,
 509                                                        FeatureAcquireRelease,
 510                                                        FeatureMClass]>;
 511
 512 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
 513                                                       [HasV8MMainlineOps,
 514                                                        FeatureNoARM,
 515                                                        FeatureDB,
 516                                                        FeatureHWDivThumb,
 517                                                        Feature8MSecExt,
 518                                                        FeatureAcquireRelease,
 519                                                        FeatureMClass]>;
 520
 521 // Aliases
 522 def IWMMXT   : Architecture<"iwmmxt",      "ARMv5te",  [ARMv5te]>;
 523 def IWMMXT2  : Architecture<"iwmmxt2",     "ARMv5te",  [ARMv5te]>;
 524 def XScale   : Architecture<"xscale",      "ARMv5te",  [ARMv5te]>;
 525 def ARMv6j   : Architecture<"armv6j",      "ARMv7a",   [ARMv6]>;
 526 def ARMv7k   : Architecture<"armv7k",      "ARMv7a",   [ARMv7a]>;
 527 def ARMv7s   : Architecture<"armv7s",      "ARMv7a",   [ARMv7a]>;
 528
 529
 530 //===----------------------------------------------------------------------===//
 531 // ARM processors
 532 //
 533
 534 // Dummy CPU, used to target architectures
 535 def : ProcNoItin<"generic",                             []>;
 536
 537 def : ProcNoItin<"arm8",                                [ARMv4]>;
 538 def : ProcNoItin<"arm810",                              [ARMv4]>;
 539 def : ProcNoItin<"strongarm",                           [ARMv4]>;
 540 def : ProcNoItin<"strongarm110",                        [ARMv4]>;
 541 def : ProcNoItin<"strongarm1100",                       [ARMv4]>;
 542 def : ProcNoItin<"strongarm1110",                       [ARMv4]>;
 543
 544 def : ProcNoItin<"arm7tdmi",                            [ARMv4t]>;
 545 def : ProcNoItin<"arm7tdmi-s",                          [ARMv4t]>;
 546 def : ProcNoItin<"arm710t",                             [ARMv4t]>;
 547 def : ProcNoItin<"arm720t",                             [ARMv4t]>;
 548 def : ProcNoItin<"arm9",                                [ARMv4t]>;
 549 def : ProcNoItin<"arm9tdmi",                            [ARMv4t]>;
 550 def : ProcNoItin<"arm920",                              [ARMv4t]>;
 551 def : ProcNoItin<"arm920t",                             [ARMv4t]>;
 552 def : ProcNoItin<"arm922t",                             [ARMv4t]>;
 553 def : ProcNoItin<"arm940t",                             [ARMv4t]>;
 554 def : ProcNoItin<"ep9312",                              [ARMv4t]>;
 555
 556 def : ProcNoItin<"arm10tdmi",                           [ARMv5t]>;
 557 def : ProcNoItin<"arm1020t",                            [ARMv5t]>;
 558
 559 def : ProcNoItin<"arm9e",                               [ARMv5te]>;
 560 def : ProcNoItin<"arm926ej-s",                          [ARMv5te]>;
 561 def : ProcNoItin<"arm946e-s",                           [ARMv5te]>;
 562 def : ProcNoItin<"arm966e-s",                           [ARMv5te]>;
 563 def : ProcNoItin<"arm968e-s",                           [ARMv5te]>;
 564 def : ProcNoItin<"arm10e",                              [ARMv5te]>;
 565 def : ProcNoItin<"arm1020e",                            [ARMv5te]>;
 566 def : ProcNoItin<"arm1022e",                            [ARMv5te]>;
 567 def : ProcNoItin<"xscale",                              [ARMv5te]>;
 568 def : ProcNoItin<"iwmmxt",                              [ARMv5te]>;
 569
 570 def : Processor<"arm1136j-s",       ARMV6Itineraries,   [ARMv6]>;
 571 def : Processor<"arm1136jf-s",      ARMV6Itineraries,   [ARMv6,
 572                                                          FeatureVFP2,
 573                                                          FeatureHasSlowFPVMLx]>;
 574
 575 def : Processor<"cortex-m0",        ARMV6Itineraries,   [ARMv6m]>;
 576 def : Processor<"cortex-m0plus",    ARMV6Itineraries,   [ARMv6m]>;
 577 def : Processor<"cortex-m1",        ARMV6Itineraries,   [ARMv6m]>;
 578 def : Processor<"sc000",            ARMV6Itineraries,   [ARMv6m]>;
 579
 580 def : Processor<"arm1176j-s",       ARMV6Itineraries,   [ARMv6kz]>;
 581 def : Processor<"arm1176jz-s",      ARMV6Itineraries,   [ARMv6kz]>;
 582 def : Processor<"arm1176jzf-s",     ARMV6Itineraries,   [ARMv6kz,
 583                                                          FeatureVFP2,
 584                                                          FeatureHasSlowFPVMLx]>;
 585
 586 def : Processor<"mpcorenovfp",      ARMV6Itineraries,   [ARMv6k]>;
 587 def : Processor<"mpcore",           ARMV6Itineraries,   [ARMv6k,
 588                                                          FeatureVFP2,
 589                                                          FeatureHasSlowFPVMLx]>;
 590
 591 def : Processor<"arm1156t2-s",      ARMV6Itineraries,   [ARMv6t2]>;
 592 def : Processor<"arm1156t2f-s",     ARMV6Itineraries,   [ARMv6t2,
 593                                                          FeatureVFP2,
 594                                                          FeatureHasSlowFPVMLx]>;
 595
 596 // FIXME: A5 has currently the same Schedule model as A8
 597 def : ProcessorModel<"cortex-a5",   CortexA8Model,      [ARMv7a, ProcA5,
 598                                                          FeatureHasRetAddrStack,
 599                                                          FeatureTrustZone,
 600                                                          FeatureSlowFPBrcc,
 601                                                          FeatureHasSlowFPVMLx,
 602                                                          FeatureVMLxForwarding,
 603                                                          FeatureMP,
 604                                                          FeatureVFP4]>;
 605
 606 def : ProcessorModel<"cortex-a7",   CortexA8Model,      [ARMv7a, ProcA7,
 607                                                          FeatureHasRetAddrStack,
 608                                                          FeatureTrustZone,
 609                                                          FeatureSlowFPBrcc,
 610                                                          FeatureHasVMLxHazards,
 611                                                          FeatureHasSlowFPVMLx,
 612                                                          FeatureVMLxForwarding,
 613                                                          FeatureMP,
 614                                                          FeatureVFP4,
 615                                                          FeatureVirtualization]>;
 616
 617 def : ProcessorModel<"cortex-a8",   CortexA8Model,      [ARMv7a, ProcA8,
 618                                                          FeatureHasRetAddrStack,
 619                                                          FeatureNonpipelinedVFP,
 620                                                          FeatureTrustZone,
 621                                                          FeatureSlowFPBrcc,
 622                                                          FeatureHasVMLxHazards,
 623                                                          FeatureHasSlowFPVMLx,
 624                                                          FeatureVMLxForwarding]>;
 625
 626 def : ProcessorModel<"cortex-a9",   CortexA9Model,      [ARMv7a, ProcA9,
 627                                                          FeatureHasRetAddrStack,
 628                                                          FeatureTrustZone,
 629                                                          FeatureHasVMLxHazards,
 630                                                          FeatureVMLxForwarding,
 631                                                          FeatureFP16,
 632                                                          FeatureAvoidPartialCPSR,
 633                                                          FeatureExpandMLx,
 634                                                          FeaturePreferVMOVSR,
 635                                                          FeatureMuxedUnits,
 636                                                          FeatureNEONForFPMovs,
 637                                                          FeatureCheckVLDnAlign,
 638                                                          FeatureMP]>;
 639
 640 // FIXME: A12 has currently the same Schedule model as A9
 641 def : ProcessorModel<"cortex-a12",  CortexA9Model,      [ARMv7a, ProcA12,
 642                                                          FeatureHasRetAddrStack,
 643                                                          FeatureTrustZone,
 644                                                          FeatureVMLxForwarding,
 645                                                          FeatureVFP4,
 646                                                          FeatureAvoidPartialCPSR,
 647                                                          FeatureVirtualization,
 648                                                          FeatureMP]>;
 649
 650 // FIXME: A15 has currently the same Schedule model as A9.
 651 def : ProcessorModel<"cortex-a15",  CortexA9Model,      [ARMv7a, ProcA15,
 652                                                          FeatureDontWidenVMOVS,
 653                                                          FeatureHasRetAddrStack,
 654                                                          FeatureMuxedUnits,
 655                                                          FeatureTrustZone,
 656                                                          FeatureVFP4,
 657                                                          FeatureMP,
 658                                                          FeatureCheckVLDnAlign,
 659                                                          FeatureAvoidPartialCPSR,
 660                                                          FeatureVirtualization]>;
 661
 662 // FIXME: A17 has currently the same Schedule model as A9
 663 def : ProcessorModel<"cortex-a17",  CortexA9Model,      [ARMv7a, ProcA17,
 664                                                          FeatureHasRetAddrStack,
 665                                                          FeatureTrustZone,
 666                                                          FeatureMP,
 667                                                          FeatureVMLxForwarding,
 668                                                          FeatureVFP4,
 669                                                          FeatureAvoidPartialCPSR,
 670                                                          FeatureVirtualization]>;
 671
 672 // FIXME: krait has currently the same Schedule model as A9
 673 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
 674 //        division features.
 675 def : ProcessorModel<"krait",       CortexA9Model,      [ARMv7a, ProcKrait,
 676                                                          FeatureHasRetAddrStack,
 677                                                          FeatureMuxedUnits,
 678                                                          FeatureCheckVLDnAlign,
 679                                                          FeatureVMLxForwarding,
 680                                                          FeatureFP16,
 681                                                          FeatureAvoidPartialCPSR,
 682                                                          FeatureVFP4,
 683                                                          FeatureHWDivThumb,
 684                                                          FeatureHWDivARM]>;
 685
 686 def : ProcessorModel<"swift",       SwiftModel,         [ARMv7a, ProcSwift,
 687                                                          FeatureHasRetAddrStack,
 688                                                          FeatureNEONForFP,
 689                                                          FeatureVFP4,
 690                                                          FeatureMP,
 691                                                          FeatureHWDivThumb,
 692                                                          FeatureHWDivARM,
 693                                                          FeatureAvoidPartialCPSR,
 694                                                          FeatureAvoidMOVsShOp,
 695                                                          FeatureHasSlowFPVMLx,
 696                                                          FeatureHasVMLxHazards,
 697                                                          FeatureProfUnpredicate,
 698                                                          FeaturePrefISHSTBarrier,
 699                                                          FeatureSlowOddRegister,
 700                                                          FeatureSlowLoadDSubreg,
 701                                                          FeatureSlowVGETLNi32,
 702                                                          FeatureSlowVDUP32]>;
 703
 704 // FIXME: R4 has currently the same ProcessorModel as A8.
 705 def : ProcessorModel<"cortex-r4",   CortexA8Model,      [ARMv7r, ProcR4,
 706                                                          FeatureHasRetAddrStack,
 707                                                          FeatureAvoidPartialCPSR]>;
 708
 709 // FIXME: R4F has currently the same ProcessorModel as A8.
 710 def : ProcessorModel<"cortex-r4f",  CortexA8Model,      [ARMv7r, ProcR4,
 711                                                          FeatureHasRetAddrStack,
 712                                                          FeatureSlowFPBrcc,
 713                                                          FeatureHasSlowFPVMLx,
 714                                                          FeatureVFP3,
 715                                                          FeatureD16,
 716                                                          FeatureAvoidPartialCPSR]>;
 717
 718 // FIXME: R5 has currently the same ProcessorModel as A8.
 719 def : ProcessorModel<"cortex-r5",   CortexA8Model,      [ARMv7r, ProcR5,
 720                                                          FeatureHasRetAddrStack,
 721                                                          FeatureVFP3,
 722                                                          FeatureD16,
 723                                                          FeatureSlowFPBrcc,
 724                                                          FeatureHWDivARM,
 725                                                          FeatureHasSlowFPVMLx,
 726                                                          FeatureAvoidPartialCPSR]>;
 727
 728 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
 729 def : ProcessorModel<"cortex-r7",   CortexA8Model,      [ARMv7r, ProcR7,
 730                                                          FeatureHasRetAddrStack,
 731                                                          FeatureVFP3,
 732                                                          FeatureD16,
 733                                                          FeatureFP16,
 734                                                          FeatureMP,
 735                                                          FeatureSlowFPBrcc,
 736                                                          FeatureHWDivARM,
 737                                                          FeatureHasSlowFPVMLx,
 738                                                          FeatureAvoidPartialCPSR]>;
 739
 740 def : ProcessorModel<"cortex-r8",   CortexA8Model,      [ARMv7r,
 741                                                          FeatureHasRetAddrStack,
 742                                                          FeatureVFP3,
 743                                                          FeatureD16,
 744                                                          FeatureFP16,
 745                                                          FeatureMP,
 746                                                          FeatureSlowFPBrcc,
 747                                                          FeatureHWDivARM,
 748                                                          FeatureHasSlowFPVMLx,
 749                                                          FeatureAvoidPartialCPSR]>;
 750
 751 def : ProcNoItin<"cortex-m3",                           [ARMv7m, ProcM3]>;
 752 def : ProcNoItin<"sc300",                               [ARMv7m, ProcM3]>;
 753
 754 def : ProcNoItin<"cortex-m4",                           [ARMv7em,
 755                                                          FeatureVFP4,
 756                                                          FeatureVFPOnlySP,
 757                                                          FeatureD16]>;
 758
 759 def : ProcNoItin<"cortex-m7",                           [ARMv7em,
 760                                                          FeatureFPARMv8,
 761                                                          FeatureD16]>;
 762
 763 def : ProcNoItin<"cortex-m23",                          [ARMv8mBaseline,
 764                                                          FeatureNoMovt]>;
 765
 766 def : ProcNoItin<"cortex-m33",                          [ARMv8mMainline,
 767                                                          FeatureDSP,
 768                                                          FeatureFPARMv8,
 769                                                          FeatureD16,
 770                                                          FeatureVFPOnlySP]>;
 771
 772 def : ProcNoItin<"cortex-a32",                           [ARMv8a,
 773                                                          FeatureHWDivThumb,
 774                                                          FeatureHWDivARM,
 775                                                          FeatureCrypto,
 776                                                          FeatureCRC]>;
 777
 778 def : ProcNoItin<"cortex-a35",                          [ARMv8a, ProcA35,
 779                                                          FeatureHWDivThumb,
 780                                                          FeatureHWDivARM,
 781                                                          FeatureCrypto,
 782                                                          FeatureCRC]>;
 783
 784 def : ProcNoItin<"cortex-a53",                          [ARMv8a, ProcA53,
 785                                                          FeatureHWDivThumb,
 786                                                          FeatureHWDivARM,
 787                                                          FeatureCrypto,
 788                                                          FeatureCRC,
 789                                                          FeatureFPAO]>;
 790
 791 def : ProcNoItin<"cortex-a57",                          [ARMv8a, ProcA57,
 792                                                          FeatureHWDivThumb,
 793                                                          FeatureHWDivARM,
 794                                                          FeatureCrypto,
 795                                                          FeatureCRC,
 796                                                          FeatureFPAO]>;
 797
 798 def : ProcNoItin<"cortex-a72",                          [ARMv8a, ProcA72,
 799                                                          FeatureHWDivThumb,
 800                                                          FeatureHWDivARM,
 801                                                          FeatureCrypto,
 802                                                          FeatureCRC]>;
 803
 804 def : ProcNoItin<"cortex-a73",                          [ARMv8a, ProcA73,
 805                                                          FeatureHWDivThumb,
 806                                                          FeatureHWDivARM,
 807                                                          FeatureCrypto,
 808                                                          FeatureCRC]>;
 809
 810 // Cyclone is very similar to swift
 811 def : ProcessorModel<"cyclone",     SwiftModel,         [ARMv8a, ProcSwift,
 812                                                          FeatureHasRetAddrStack,
 813                                                          FeatureNEONForFP,
 814                                                          FeatureVFP4,
 815                                                          FeatureMP,
 816                                                          FeatureHWDivThumb,
 817                                                          FeatureHWDivARM,
 818                                                          FeatureAvoidPartialCPSR,
 819                                                          FeatureAvoidMOVsShOp,
 820                                                          FeatureHasSlowFPVMLx,
 821                                                          FeatureCrypto,
 822                                                          FeatureZCZeroing]>;
 823
 824 def : ProcNoItin<"exynos-m1",                           [ARMv8a, ProcExynosM1,
 825                                                          FeatureHWDivThumb,
 826                                                          FeatureHWDivARM,
 827                                                          FeatureCrypto,
 828                                                          FeatureCRC]>;
 829
 830 def : ProcNoItin<"exynos-m2",                           [ARMv8a, ProcExynosM1,
 831                                                          FeatureHWDivThumb,
 832                                                          FeatureHWDivARM,
 833                                                          FeatureCrypto,
 834                                                          FeatureCRC]>;
 835
 836 def : ProcNoItin<"exynos-m3",                           [ARMv8a, ProcExynosM1,
 837                                                          FeatureHWDivThumb,
 838                                                          FeatureHWDivARM,
 839                                                          FeatureCrypto,
 840                                                          FeatureCRC]>;
 841
 842 def : ProcNoItin<"kryo",                                [ARMv8a, ProcKryo,
 843                                                          FeatureHWDivThumb,
 844                                                          FeatureHWDivARM,
 845                                                          FeatureCrypto,
 846                                                          FeatureCRC]>;
 847
 848 def : ProcessorModel<"cortex-r52", CortexR52Model,      [ARMv8r, ProcR52,
 849                                                          FeatureFPAO]>;
 850
 851 //===----------------------------------------------------------------------===//
 852 // Register File Description
 853 //===----------------------------------------------------------------------===//
 854
 855 include "ARMRegisterInfo.td"
 856
 857 include "ARMRegisterBanks.td"
 858
 859 include "ARMCallingConv.td"
 860
 861 //===----------------------------------------------------------------------===//
 862 // Instruction Descriptions
 863 //===----------------------------------------------------------------------===//
 864
 865 include "ARMInstrInfo.td"
 866
 867 def ARMInstrInfo : InstrInfo;
 868
 869 //===----------------------------------------------------------------------===//
 870 // Declare the target which we are implementing
 871 //===----------------------------------------------------------------------===//
 872
 873 def ARMAsmWriter : AsmWriter {
 874   string AsmWriterClassName  = "InstPrinter";
 875   int PassSubtarget = 1;
 876   int Variant = 0;
 877   bit isMCAsmWriter = 1;
 878 }
 879
 880 def ARMAsmParserVariant : AsmParserVariant {
 881   int Variant = 0;
 882   string Name = "ARM";
 883   string BreakCharacters = ".";
 884 }
 885
 886 def ARM : Target {
 887   // Pull in Instruction Info:
 888   let InstructionSet = ARMInstrInfo;
 889   let AssemblyWriters = [ARMAsmWriter];
 890   let AssemblyParserVariants = [ARMAsmParserVariant];
 891 }