1 //===-- ARM.td - Describe the ARM Target Machine -----------*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 //===----------------------------------------------------------------------===//
14 // Target-independent interfaces which we are implementing
15 //===----------------------------------------------------------------------===//
17 include "llvm/Target/Target.td"
19 //===----------------------------------------------------------------------===//
20 // ARM Helper classes.
23 class ProcNoItin<string Name, list<SubtargetFeature> Features>
24 : Processor<Name, NoItineraries, Features>;
26 class Architecture<string fname, string aname, list<SubtargetFeature> features >
27 : SubtargetFeature<fname, "ARMArch", aname,
28 !strconcat(aname, " architecture"), features>;
30 //===----------------------------------------------------------------------===//
31 // ARM Subtarget state.
34 def ModeThumb : SubtargetFeature<"thumb-mode", "InThumbMode", "true",
37 def ModeSoftFloat : SubtargetFeature<"soft-float", "UseSoftFloat", "true",
38 "Use software floating point features.">;
40 //===----------------------------------------------------------------------===//
41 // ARM Subtarget features.
44 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
45 "Enable VFP2 instructions">;
46 def FeatureVFP3 : SubtargetFeature<"vfp3", "HasVFPv3", "true",
47 "Enable VFP3 instructions",
49 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
50 "Enable NEON instructions",
52 def FeatureThumb2 : SubtargetFeature<"thumb2", "HasThumb2", "true",
53 "Enable Thumb2 instructions">;
54 def FeatureNoARM : SubtargetFeature<"noarm", "NoARM", "true",
55 "Does not support ARM mode execution",
57 def FeatureFP16 : SubtargetFeature<"fp16", "HasFP16", "true",
58 "Enable half-precision floating point">;
59 def FeatureVFP4 : SubtargetFeature<"vfp4", "HasVFPv4", "true",
60 "Enable VFP4 instructions",
61 [FeatureVFP3, FeatureFP16]>;
62 def FeatureFPARMv8 : SubtargetFeature<"fp-armv8", "HasFPARMv8",
63 "true", "Enable ARMv8 FP",
65 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
66 "Enable full half-precision floating point",
68 def FeatureD16 : SubtargetFeature<"d16", "HasD16", "true",
69 "Restrict FP to 16 double registers">;
70 def FeatureHWDiv : SubtargetFeature<"hwdiv", "HasHardwareDivide", "true",
71 "Enable divide instructions">;
72 def FeatureHWDivARM : SubtargetFeature<"hwdiv-arm",
73 "HasHardwareDivideInARM", "true",
74 "Enable divide instructions in ARM mode">;
75 def FeatureT2XtPk : SubtargetFeature<"t2xtpk", "HasT2ExtractPack", "true",
76 "Enable Thumb2 extract and pack instructions">;
77 def FeatureDB : SubtargetFeature<"db", "HasDataBarrier", "true",
78 "Has data barrier (dmb / dsb) instructions">;
79 def FeatureV7Clrex : SubtargetFeature<"v7clrex", "HasV7Clrex", "true",
80 "Has v7 clrex instruction">;
81 def FeatureAcquireRelease : SubtargetFeature<"acquire-release",
82 "HasAcquireRelease", "true",
83 "Has v8 acquire/release (lda/ldaex etc) instructions">;
84 def FeatureSlowFPBrcc : SubtargetFeature<"slow-fp-brcc", "SlowFPBrcc", "true",
85 "FP compare + branch is slow">;
86 def FeatureVFPOnlySP : SubtargetFeature<"fp-only-sp", "FPOnlySP", "true",
87 "Floating point unit supports single precision only">;
88 def FeaturePerfMon : SubtargetFeature<"perfmon", "HasPerfMon", "true",
89 "Enable support for Performance Monitor extensions">;
90 def FeatureTrustZone : SubtargetFeature<"trustzone", "HasTrustZone", "true",
91 "Enable support for TrustZone security extensions">;
92 def Feature8MSecExt : SubtargetFeature<"8msecext", "Has8MSecExt", "true",
93 "Enable support for ARMv8-M Security Extensions">;
94 def FeatureCrypto : SubtargetFeature<"crypto", "HasCrypto", "true",
95 "Enable support for Cryptography extensions",
97 def FeatureCRC : SubtargetFeature<"crc", "HasCRC", "true",
98 "Enable support for CRC instructions">;
99 // Not to be confused with FeatureHasRetAddrStack (return address stack)
100 def FeatureRAS : SubtargetFeature<"ras", "HasRAS", "true",
101 "Enable Reliability, Availability and Serviceability extensions">;
104 // Cyclone has preferred instructions for zeroing VFP registers, which can
105 // execute in 0 cycles.
106 def FeatureZCZeroing : SubtargetFeature<"zcz", "HasZeroCycleZeroing", "true",
107 "Has zero-cycle zeroing instructions">;
109 // Whether or not it may be profitable to unpredicate certain instructions
110 // during if conversion.
111 def FeatureProfUnpredicate : SubtargetFeature<"prof-unpr",
112 "IsProfitableToUnpredicate",
114 "Is profitable to unpredicate">;
116 // Some targets (e.g. Swift) have microcoded VGETLNi32.
117 def FeatureSlowVGETLNi32 : SubtargetFeature<"slow-vgetlni32",
118 "HasSlowVGETLNi32", "true",
119 "Has slow VGETLNi32 - prefer VMOV">;
121 // Some targets (e.g. Swift) have microcoded VDUP32.
122 def FeatureSlowVDUP32 : SubtargetFeature<"slow-vdup32", "HasSlowVDUP32", "true",
123 "Has slow VDUP32 - prefer VMOV">;
125 // Some targets (e.g. Cortex-A9) prefer VMOVSR to VMOVDRR even when using NEON
126 // for scalar FP, as this allows more effective execution domain optimization.
127 def FeaturePreferVMOVSR : SubtargetFeature<"prefer-vmovsr", "PreferVMOVSR",
128 "true", "Prefer VMOVSR">;
130 // Swift has ISHST barriers compatible with Atomic Release semantics but weaker
132 def FeaturePrefISHSTBarrier : SubtargetFeature<"prefer-ishst", "PreferISHST",
133 "true", "Prefer ISHST barriers">;
135 // Some targets (e.g. Cortex-A9) have muxed AGU and NEON/FPU.
136 def FeatureMuxedUnits : SubtargetFeature<"muxed-units", "HasMuxedUnits", "true",
137 "Has muxed AGU and NEON/FPU">;
139 // On some targets, a VLDM/VSTM starting with an odd register number needs more
140 // microops than single VLDRS.
141 def FeatureSlowOddRegister : SubtargetFeature<"slow-odd-reg", "SlowOddRegister",
142 "true", "VLDM/VSTM starting with an odd register is slow">;
144 // Some targets have a renaming dependency when loading into D subregisters.
145 def FeatureSlowLoadDSubreg : SubtargetFeature<"slow-load-D-subreg",
146 "SlowLoadDSubregister", "true",
147 "Loading into D subregs is slow">;
148 // Some targets (e.g. Cortex-A15) never want VMOVS to be widened to VMOVD.
149 def FeatureDontWidenVMOVS : SubtargetFeature<"dont-widen-vmovs",
150 "DontWidenVMOVS", "true",
151 "Don't widen VMOVS to VMOVD">;
153 // Whether or not it is profitable to expand VFP/NEON MLA/MLS instructions.
154 def FeatureExpandMLx : SubtargetFeature<"expand-fp-mlx", "ExpandMLx", "true",
155 "Expand VFP/NEON MLA/MLS instructions">;
157 // Some targets have special RAW hazards for VFP/NEON VMLA/VMLS.
158 def FeatureHasVMLxHazards : SubtargetFeature<"vmlx-hazards", "HasVMLxHazards",
159 "true", "Has VMLx hazards">;
161 // Some targets (e.g. Cortex-A9) want to convert VMOVRS, VMOVSR and VMOVS from
162 // VFP to NEON, as an execution domain optimization.
163 def FeatureNEONForFPMovs : SubtargetFeature<"neon-fpmovs", "UseNEONForFPMovs",
164 "true", "Convert VMOVSR, VMOVRS, VMOVS to NEON">;
166 // Some processors benefit from using NEON instructions for scalar
167 // single-precision FP operations. This affects instruction selection and should
168 // only be enabled if the handling of denormals is not important.
169 def FeatureNEONForFP : SubtargetFeature<"neonfp", "UseNEONForSinglePrecisionFP",
171 "Use NEON for single precision FP">;
173 // On some processors, VLDn instructions that access unaligned data take one
174 // extra cycle. Take that into account when computing operand latencies.
175 def FeatureCheckVLDnAlign : SubtargetFeature<"vldn-align", "CheckVLDnAlign",
177 "Check for VLDn unaligned access">;
179 // Some processors have a nonpipelined VFP coprocessor.
180 def FeatureNonpipelinedVFP : SubtargetFeature<"nonpipelined-vfp",
181 "NonpipelinedVFP", "true",
182 "VFP instructions are not pipelined">;
184 // Some processors have FP multiply-accumulate instructions that don't
185 // play nicely with other VFP / NEON instructions, and it's generally better
186 // to just not use them.
187 def FeatureHasSlowFPVMLx : SubtargetFeature<"slowfpvmlx", "SlowFPVMLx", "true",
188 "Disable VFP / NEON MAC instructions">;
190 // Cortex-A8 / A9 Advanced SIMD has multiplier accumulator forwarding.
191 def FeatureVMLxForwarding : SubtargetFeature<"vmlx-forwarding",
192 "HasVMLxForwarding", "true",
193 "Has multiplier accumulator forwarding">;
195 // Disable 32-bit to 16-bit narrowing for experimentation.
196 def FeaturePref32BitThumb : SubtargetFeature<"32bit", "Pref32BitThumb", "true",
197 "Prefer 32-bit Thumb instrs">;
199 /// Some instructions update CPSR partially, which can add false dependency for
200 /// out-of-order implementation, e.g. Cortex-A9, unless each individual bit is
201 /// mapped to a separate physical register. Avoid partial CPSR update for these
203 def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
204 "AvoidCPSRPartialUpdate", "true",
205 "Avoid CPSR partial update for OOO execution">;
207 def FeatureAvoidMOVsShOp : SubtargetFeature<"avoid-movs-shop",
208 "AvoidMOVsShifterOperand", "true",
209 "Avoid movs instructions with shifter operand">;
211 // Some processors perform return stack prediction. CodeGen should avoid issue
212 // "normal" call instructions to callees which do not return.
213 def FeatureHasRetAddrStack : SubtargetFeature<"ret-addr-stack", "HasRetAddrStack", "true",
214 "Has return address stack">;
217 def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true",
218 "Supports DSP instructions in ARM and/or Thumb2">;
220 // Multiprocessing extension.
221 def FeatureMP : SubtargetFeature<"mp", "HasMPExtension", "true",
222 "Supports Multiprocessing extension">;
224 // Virtualization extension - requires HW divide (ARMv7-AR ARMARM - 4.4.8).
225 def FeatureVirtualization : SubtargetFeature<"virtualization",
226 "HasVirtualization", "true",
227 "Supports Virtualization extension",
228 [FeatureHWDiv, FeatureHWDivARM]>;
231 def FeatureMClass : SubtargetFeature<"mclass", "ARMProcClass", "MClass",
232 "Is microcontroller profile ('M' series)">;
235 def FeatureRClass : SubtargetFeature<"rclass", "ARMProcClass", "RClass",
236 "Is realtime profile ('R' series)">;
239 def FeatureAClass : SubtargetFeature<"aclass", "ARMProcClass", "AClass",
240 "Is application profile ('A' series)">;
242 // Special TRAP encoding for NaCl, which looks like a TRAP in Thumb too.
243 // See ARMInstrInfo.td for details.
244 def FeatureNaClTrap : SubtargetFeature<"nacl-trap", "UseNaClTrap", "true",
247 def FeatureStrictAlign : SubtargetFeature<"strict-align",
248 "StrictAlign", "true",
249 "Disallow all unaligned memory "
252 def FeatureLongCalls : SubtargetFeature<"long-calls", "GenLongCalls", "true",
253 "Generate calls via indirect call "
256 def FeatureReserveR9 : SubtargetFeature<"reserve-r9", "ReserveR9", "true",
257 "Reserve R9, making it unavailable as "
260 def FeatureNoMovt : SubtargetFeature<"no-movt", "NoMovt", "true",
261 "Don't use movt/movw pairs for 32-bit "
265 //===----------------------------------------------------------------------===//
269 def HasV4TOps : SubtargetFeature<"v4t", "HasV4TOps", "true",
270 "Support ARM v4T instructions">;
271 def HasV5TOps : SubtargetFeature<"v5t", "HasV5TOps", "true",
272 "Support ARM v5T instructions",
274 def HasV5TEOps : SubtargetFeature<"v5te", "HasV5TEOps", "true",
275 "Support ARM v5TE, v5TEj, and v5TExp instructions",
277 def HasV6Ops : SubtargetFeature<"v6", "HasV6Ops", "true",
278 "Support ARM v6 instructions",
280 def HasV6MOps : SubtargetFeature<"v6m", "HasV6MOps", "true",
281 "Support ARM v6M instructions",
283 def HasV8MBaselineOps : SubtargetFeature<"v8m", "HasV8MBaselineOps", "true",
284 "Support ARM v8M Baseline instructions",
286 def HasV6KOps : SubtargetFeature<"v6k", "HasV6KOps", "true",
287 "Support ARM v6k instructions",
289 def HasV6T2Ops : SubtargetFeature<"v6t2", "HasV6T2Ops", "true",
290 "Support ARM v6t2 instructions",
291 [HasV8MBaselineOps, HasV6KOps, FeatureThumb2]>;
292 def HasV7Ops : SubtargetFeature<"v7", "HasV7Ops", "true",
293 "Support ARM v7 instructions",
294 [HasV6T2Ops, FeaturePerfMon,
296 def HasV8Ops : SubtargetFeature<"v8", "HasV8Ops", "true",
297 "Support ARM v8 instructions",
298 [HasV7Ops, FeatureAcquireRelease]>;
299 def HasV8_1aOps : SubtargetFeature<"v8.1a", "HasV8_1aOps", "true",
300 "Support ARM v8.1a instructions",
302 def HasV8_2aOps : SubtargetFeature<"v8.2a", "HasV8_2aOps", "true",
303 "Support ARM v8.2a instructions",
305 def HasV8MMainlineOps : SubtargetFeature<"v8m.main", "HasV8MMainlineOps", "true",
306 "Support ARM v8M Mainline instructions",
310 //===----------------------------------------------------------------------===//
311 // ARM Processor subtarget features.
314 def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5",
315 "Cortex-A5 ARM processors", []>;
316 def ProcA7 : SubtargetFeature<"a7", "ARMProcFamily", "CortexA7",
317 "Cortex-A7 ARM processors", []>;
318 def ProcA8 : SubtargetFeature<"a8", "ARMProcFamily", "CortexA8",
319 "Cortex-A8 ARM processors", []>;
320 def ProcA9 : SubtargetFeature<"a9", "ARMProcFamily", "CortexA9",
321 "Cortex-A9 ARM processors", []>;
322 def ProcA12 : SubtargetFeature<"a12", "ARMProcFamily", "CortexA12",
323 "Cortex-A12 ARM processors", []>;
324 def ProcA15 : SubtargetFeature<"a15", "ARMProcFamily", "CortexA15",
325 "Cortex-A15 ARM processors", []>;
326 def ProcA17 : SubtargetFeature<"a17", "ARMProcFamily", "CortexA17",
327 "Cortex-A17 ARM processors", []>;
328 def ProcA32 : SubtargetFeature<"a32", "ARMProcFamily", "CortexA32",
329 "Cortex-A32 ARM processors", []>;
330 def ProcA35 : SubtargetFeature<"a35", "ARMProcFamily", "CortexA35",
331 "Cortex-A35 ARM processors", []>;
332 def ProcA53 : SubtargetFeature<"a53", "ARMProcFamily", "CortexA53",
333 "Cortex-A53 ARM processors", []>;
334 def ProcA57 : SubtargetFeature<"a57", "ARMProcFamily", "CortexA57",
335 "Cortex-A57 ARM processors", []>;
336 def ProcA72 : SubtargetFeature<"a72", "ARMProcFamily", "CortexA72",
337 "Cortex-A72 ARM processors", []>;
338 def ProcA73 : SubtargetFeature<"a73", "ARMProcFamily", "CortexA73",
339 "Cortex-A73 ARM processors", []>;
341 def ProcKrait : SubtargetFeature<"krait", "ARMProcFamily", "Krait",
342 "Qualcomm ARM processors", []>;
343 def ProcSwift : SubtargetFeature<"swift", "ARMProcFamily", "Swift",
344 "Swift ARM processors", []>;
346 def ProcExynosM1 : SubtargetFeature<"exynosm1", "ARMProcFamily", "ExynosM1",
347 "Samsung Exynos-M1 processors", []>;
349 def ProcR4 : SubtargetFeature<"r4", "ARMProcFamily", "CortexR4",
350 "Cortex-R4 ARM processors", []>;
351 def ProcR5 : SubtargetFeature<"r5", "ARMProcFamily", "CortexR5",
352 "Cortex-R5 ARM processors", []>;
353 def ProcR7 : SubtargetFeature<"r7", "ARMProcFamily", "CortexR7",
354 "Cortex-R7 ARM processors", []>;
356 def ProcM3 : SubtargetFeature<"m3", "ARMProcFamily", "CortexM3",
357 "Cortex-M3 ARM processors", []>;
359 //===----------------------------------------------------------------------===//
363 include "ARMSchedule.td"
366 //===----------------------------------------------------------------------===//
370 def ARMv2 : Architecture<"armv2", "ARMv2", []>;
372 def ARMv2a : Architecture<"armv2a", "ARMv2a", []>;
374 def ARMv3 : Architecture<"armv3", "ARMv3", []>;
376 def ARMv3m : Architecture<"armv3m", "ARMv3m", []>;
378 def ARMv4 : Architecture<"armv4", "ARMv4", []>;
380 def ARMv4t : Architecture<"armv4t", "ARMv4t", [HasV4TOps]>;
382 def ARMv5t : Architecture<"armv5t", "ARMv5t", [HasV5TOps]>;
384 def ARMv5te : Architecture<"armv5te", "ARMv5te", [HasV5TEOps]>;
386 def ARMv5tej : Architecture<"armv5tej", "ARMv5tej", [HasV5TEOps]>;
388 def ARMv6 : Architecture<"armv6", "ARMv6", [HasV6Ops]>;
390 def ARMv6t2 : Architecture<"armv6t2", "ARMv6t2", [HasV6T2Ops,
393 def ARMv6k : Architecture<"armv6k", "ARMv6k", [HasV6KOps]>;
395 def ARMv6kz : Architecture<"armv6kz", "ARMv6kz", [HasV6KOps,
398 def ARMv6m : Architecture<"armv6-m", "ARMv6m", [HasV6MOps,
403 def ARMv6sm : Architecture<"armv6s-m", "ARMv6sm", [HasV6MOps,
408 def ARMv7a : Architecture<"armv7-a", "ARMv7a", [HasV7Ops,
414 def ARMv7r : Architecture<"armv7-r", "ARMv7r", [HasV7Ops,
420 def ARMv7m : Architecture<"armv7-m", "ARMv7m", [HasV7Ops,
427 def ARMv7em : Architecture<"armv7e-m", "ARMv7em", [HasV7Ops,
436 def ARMv8a : Architecture<"armv8-a", "ARMv8a", [HasV8Ops,
444 FeatureVirtualization,
448 def ARMv81a : Architecture<"armv8.1-a", "ARMv81a", [HasV8_1aOps,
456 FeatureVirtualization,
460 def ARMv82a : Architecture<"armv8.2-a", "ARMv82a", [HasV8_2aOps,
468 FeatureVirtualization,
473 def ARMv8mBaseline : Architecture<"armv8-m.base", "ARMv8mBaseline",
480 FeatureAcquireRelease,
483 def ARMv8mMainline : Architecture<"armv8-m.main", "ARMv8mMainline",
489 FeatureAcquireRelease,
493 def IWMMXT : Architecture<"iwmmxt", "ARMv5te", [ARMv5te]>;
494 def IWMMXT2 : Architecture<"iwmmxt2", "ARMv5te", [ARMv5te]>;
495 def XScale : Architecture<"xscale", "ARMv5te", [ARMv5te]>;
496 def ARMv6j : Architecture<"armv6j", "ARMv7a", [ARMv6]>;
497 def ARMv7k : Architecture<"armv7k", "ARMv7a", [ARMv7a]>;
498 def ARMv7s : Architecture<"armv7s", "ARMv7a", [ARMv7a]>;
501 //===----------------------------------------------------------------------===//
505 // Dummy CPU, used to target architectures
506 def : ProcNoItin<"generic", []>;
508 def : ProcNoItin<"arm8", [ARMv4]>;
509 def : ProcNoItin<"arm810", [ARMv4]>;
510 def : ProcNoItin<"strongarm", [ARMv4]>;
511 def : ProcNoItin<"strongarm110", [ARMv4]>;
512 def : ProcNoItin<"strongarm1100", [ARMv4]>;
513 def : ProcNoItin<"strongarm1110", [ARMv4]>;
515 def : ProcNoItin<"arm7tdmi", [ARMv4t]>;
516 def : ProcNoItin<"arm7tdmi-s", [ARMv4t]>;
517 def : ProcNoItin<"arm710t", [ARMv4t]>;
518 def : ProcNoItin<"arm720t", [ARMv4t]>;
519 def : ProcNoItin<"arm9", [ARMv4t]>;
520 def : ProcNoItin<"arm9tdmi", [ARMv4t]>;
521 def : ProcNoItin<"arm920", [ARMv4t]>;
522 def : ProcNoItin<"arm920t", [ARMv4t]>;
523 def : ProcNoItin<"arm922t", [ARMv4t]>;
524 def : ProcNoItin<"arm940t", [ARMv4t]>;
525 def : ProcNoItin<"ep9312", [ARMv4t]>;
527 def : ProcNoItin<"arm10tdmi", [ARMv5t]>;
528 def : ProcNoItin<"arm1020t", [ARMv5t]>;
530 def : ProcNoItin<"arm9e", [ARMv5te]>;
531 def : ProcNoItin<"arm926ej-s", [ARMv5te]>;
532 def : ProcNoItin<"arm946e-s", [ARMv5te]>;
533 def : ProcNoItin<"arm966e-s", [ARMv5te]>;
534 def : ProcNoItin<"arm968e-s", [ARMv5te]>;
535 def : ProcNoItin<"arm10e", [ARMv5te]>;
536 def : ProcNoItin<"arm1020e", [ARMv5te]>;
537 def : ProcNoItin<"arm1022e", [ARMv5te]>;
538 def : ProcNoItin<"xscale", [ARMv5te]>;
539 def : ProcNoItin<"iwmmxt", [ARMv5te]>;
541 def : Processor<"arm1136j-s", ARMV6Itineraries, [ARMv6]>;
542 def : Processor<"arm1136jf-s", ARMV6Itineraries, [ARMv6,
544 FeatureHasSlowFPVMLx]>;
546 def : Processor<"cortex-m0", ARMV6Itineraries, [ARMv6m]>;
547 def : Processor<"cortex-m0plus", ARMV6Itineraries, [ARMv6m]>;
548 def : Processor<"cortex-m1", ARMV6Itineraries, [ARMv6m]>;
549 def : Processor<"sc000", ARMV6Itineraries, [ARMv6m]>;
551 def : Processor<"arm1176jz-s", ARMV6Itineraries, [ARMv6kz]>;
552 def : Processor<"arm1176jzf-s", ARMV6Itineraries, [ARMv6kz,
554 FeatureHasSlowFPVMLx]>;
556 def : Processor<"mpcorenovfp", ARMV6Itineraries, [ARMv6k]>;
557 def : Processor<"mpcore", ARMV6Itineraries, [ARMv6k,
559 FeatureHasSlowFPVMLx]>;
561 def : Processor<"arm1156t2-s", ARMV6Itineraries, [ARMv6t2]>;
562 def : Processor<"arm1156t2f-s", ARMV6Itineraries, [ARMv6t2,
564 FeatureHasSlowFPVMLx]>;
566 // FIXME: A5 has currently the same Schedule model as A8
567 def : ProcessorModel<"cortex-a5", CortexA8Model, [ARMv7a, ProcA5,
568 FeatureHasRetAddrStack,
571 FeatureHasSlowFPVMLx,
572 FeatureVMLxForwarding,
577 def : ProcessorModel<"cortex-a7", CortexA8Model, [ARMv7a, ProcA7,
578 FeatureHasRetAddrStack,
581 FeatureHasVMLxHazards,
582 FeatureHasSlowFPVMLx,
583 FeatureVMLxForwarding,
589 FeatureVirtualization]>;
591 def : ProcessorModel<"cortex-a8", CortexA8Model, [ARMv7a, ProcA8,
592 FeatureHasRetAddrStack,
593 FeatureNonpipelinedVFP,
596 FeatureHasVMLxHazards,
597 FeatureHasSlowFPVMLx,
598 FeatureVMLxForwarding,
601 def : ProcessorModel<"cortex-a9", CortexA9Model, [ARMv7a, ProcA9,
602 FeatureHasRetAddrStack,
604 FeatureHasVMLxHazards,
605 FeatureVMLxForwarding,
608 FeatureAvoidPartialCPSR,
612 FeatureNEONForFPMovs,
613 FeatureCheckVLDnAlign,
616 // FIXME: A12 has currently the same Schedule model as A9
617 def : ProcessorModel<"cortex-a12", CortexA9Model, [ARMv7a, ProcA12,
618 FeatureHasRetAddrStack,
620 FeatureVMLxForwarding,
625 FeatureAvoidPartialCPSR,
626 FeatureVirtualization,
629 // FIXME: A15 has currently the same Schedule model as A9.
630 def : ProcessorModel<"cortex-a15", CortexA9Model, [ARMv7a, ProcA15,
631 FeatureDontWidenVMOVS,
632 FeatureHasRetAddrStack,
638 FeatureCheckVLDnAlign,
641 FeatureAvoidPartialCPSR,
642 FeatureVirtualization]>;
644 // FIXME: A17 has currently the same Schedule model as A9
645 def : ProcessorModel<"cortex-a17", CortexA9Model, [ARMv7a, ProcA17,
646 FeatureHasRetAddrStack,
649 FeatureVMLxForwarding,
654 FeatureAvoidPartialCPSR,
655 FeatureVirtualization]>;
657 // FIXME: krait has currently the same Schedule model as A9
658 // FIXME: krait has currently the same features as A9 plus VFP4 and hardware
659 // division features.
660 def : ProcessorModel<"krait", CortexA9Model, [ARMv7a, ProcKrait,
661 FeatureHasRetAddrStack,
663 FeatureCheckVLDnAlign,
664 FeatureVMLxForwarding,
667 FeatureAvoidPartialCPSR,
672 def : ProcessorModel<"swift", SwiftModel, [ARMv7a, ProcSwift,
673 FeatureHasRetAddrStack,
680 FeatureAvoidPartialCPSR,
681 FeatureAvoidMOVsShOp,
682 FeatureHasSlowFPVMLx,
683 FeatureHasVMLxHazards,
684 FeatureProfUnpredicate,
685 FeaturePrefISHSTBarrier,
686 FeatureSlowOddRegister,
687 FeatureSlowLoadDSubreg,
688 FeatureSlowVGETLNi32,
691 // FIXME: R4 has currently the same ProcessorModel as A8.
692 def : ProcessorModel<"cortex-r4", CortexA8Model, [ARMv7r, ProcR4,
693 FeatureHasRetAddrStack,
694 FeatureAvoidPartialCPSR,
697 // FIXME: R4F has currently the same ProcessorModel as A8.
698 def : ProcessorModel<"cortex-r4f", CortexA8Model, [ARMv7r, ProcR4,
699 FeatureHasRetAddrStack,
701 FeatureHasSlowFPVMLx,
704 FeatureAvoidPartialCPSR,
707 // FIXME: R5 has currently the same ProcessorModel as A8.
708 def : ProcessorModel<"cortex-r5", CortexA8Model, [ARMv7r, ProcR5,
709 FeatureHasRetAddrStack,
714 FeatureHasSlowFPVMLx,
715 FeatureAvoidPartialCPSR,
718 // FIXME: R7 has currently the same ProcessorModel as A8 and is modelled as R5.
719 def : ProcessorModel<"cortex-r7", CortexA8Model, [ARMv7r, ProcR7,
720 FeatureHasRetAddrStack,
727 FeatureHasSlowFPVMLx,
728 FeatureAvoidPartialCPSR,
731 def : ProcessorModel<"cortex-r8", CortexA8Model, [ARMv7r,
732 FeatureHasRetAddrStack,
739 FeatureHasSlowFPVMLx,
740 FeatureAvoidPartialCPSR,
743 def : ProcNoItin<"cortex-m3", [ARMv7m, ProcM3]>;
744 def : ProcNoItin<"sc300", [ARMv7m, ProcM3]>;
746 def : ProcNoItin<"cortex-m4", [ARMv7em,
751 def : ProcNoItin<"cortex-m7", [ARMv7em,
755 def : ProcNoItin<"cortex-a32", [ARMv8a,
762 def : ProcNoItin<"cortex-a35", [ARMv8a, ProcA35,
769 def : ProcNoItin<"cortex-a53", [ARMv8a, ProcA53,
776 def : ProcNoItin<"cortex-a57", [ARMv8a, ProcA57,
783 def : ProcNoItin<"cortex-a72", [ARMv8a, ProcA72,
790 def : ProcNoItin<"cortex-a73", [ARMv8a, ProcA73,
797 // Cyclone is very similar to swift
798 def : ProcessorModel<"cyclone", SwiftModel, [ARMv8a, ProcSwift,
799 FeatureHasRetAddrStack,
806 FeatureAvoidPartialCPSR,
807 FeatureAvoidMOVsShOp,
808 FeatureHasSlowFPVMLx,
812 def : ProcNoItin<"exynos-m1", [ARMv8a, ProcExynosM1,
819 //===----------------------------------------------------------------------===//
820 // Register File Description
821 //===----------------------------------------------------------------------===//
823 include "ARMRegisterInfo.td"
825 include "ARMCallingConv.td"
827 //===----------------------------------------------------------------------===//
828 // Instruction Descriptions
829 //===----------------------------------------------------------------------===//
831 include "ARMInstrInfo.td"
833 def ARMInstrInfo : InstrInfo;
835 //===----------------------------------------------------------------------===//
836 // Declare the target which we are implementing
837 //===----------------------------------------------------------------------===//
839 def ARMAsmWriter : AsmWriter {
840 string AsmWriterClassName = "InstPrinter";
841 int PassSubtarget = 1;
843 bit isMCAsmWriter = 1;
846 def ARMAsmParserVariant : AsmParserVariant {
849 string BreakCharacters = ".";
853 // Pull in Instruction Info:
854 let InstructionSet = ARMInstrInfo;
855 let AssemblyWriters = [ARMAsmWriter];
856 let AssemblyParserVariants = [ARMAsmParserVariant];