1 //===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a printer that converts from our internal representation
11 // of machine-dependent LLVM code to GAS-format ARM assembly language.
13 //===----------------------------------------------------------------------===//
15 #include "ARMAsmPrinter.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMTargetMachine.h"
20 #include "ARMTargetObjectFile.h"
21 #include "InstPrinter/ARMInstPrinter.h"
22 #include "MCTargetDesc/ARMAddressingModes.h"
23 #include "MCTargetDesc/ARMMCExpr.h"
24 #include "llvm/ADT/SetVector.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/BinaryFormat/COFF.h"
27 #include "llvm/BinaryFormat/ELF.h"
28 #include "llvm/CodeGen/MachineFunctionPass.h"
29 #include "llvm/CodeGen/MachineJumpTableInfo.h"
30 #include "llvm/CodeGen/MachineModuleInfoImpls.h"
31 #include "llvm/IR/Constants.h"
32 #include "llvm/IR/DataLayout.h"
33 #include "llvm/IR/DebugInfo.h"
34 #include "llvm/IR/Mangler.h"
35 #include "llvm/IR/Module.h"
36 #include "llvm/IR/Type.h"
37 #include "llvm/MC/MCAsmInfo.h"
38 #include "llvm/MC/MCAssembler.h"
39 #include "llvm/MC/MCContext.h"
40 #include "llvm/MC/MCELFStreamer.h"
41 #include "llvm/MC/MCInst.h"
42 #include "llvm/MC/MCInstBuilder.h"
43 #include "llvm/MC/MCObjectStreamer.h"
44 #include "llvm/MC/MCSectionMachO.h"
45 #include "llvm/MC/MCStreamer.h"
46 #include "llvm/MC/MCSymbol.h"
47 #include "llvm/Support/ARMBuildAttributes.h"
48 #include "llvm/Support/Debug.h"
49 #include "llvm/Support/ErrorHandling.h"
50 #include "llvm/Support/TargetParser.h"
51 #include "llvm/Support/TargetRegistry.h"
52 #include "llvm/Support/raw_ostream.h"
53 #include "llvm/Target/TargetMachine.h"
57 #define DEBUG_TYPE "asm-printer"
59 ARMAsmPrinter::ARMAsmPrinter(TargetMachine &TM,
60 std::unique_ptr<MCStreamer> Streamer)
61 : AsmPrinter(TM, std::move(Streamer)), AFI(nullptr), MCP(nullptr),
62 InConstantPool(false), OptimizationGoals(-1) {}
64 void ARMAsmPrinter::EmitFunctionBodyEnd() {
65 // Make sure to terminate any constant pools that were at the end
69 InConstantPool = false;
70 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
73 void ARMAsmPrinter::EmitFunctionEntryLabel() {
74 if (AFI->isThumbFunction()) {
75 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
76 OutStreamer->EmitThumbFunc(CurrentFnSym);
78 OutStreamer->EmitAssemblerFlag(MCAF_Code32);
80 OutStreamer->EmitLabel(CurrentFnSym);
83 void ARMAsmPrinter::EmitXXStructor(const DataLayout &DL, const Constant *CV) {
84 uint64_t Size = getDataLayout().getTypeAllocSize(CV->getType());
85 assert(Size && "C++ constructor pointer had zero size!");
87 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
88 assert(GV && "C++ constructor pointer was not a GlobalValue!");
90 const MCExpr *E = MCSymbolRefExpr::create(GetARMGVSymbol(GV,
92 (Subtarget->isTargetELF()
93 ? MCSymbolRefExpr::VK_ARM_TARGET1
94 : MCSymbolRefExpr::VK_None),
97 OutStreamer->EmitValue(E, Size);
100 void ARMAsmPrinter::EmitGlobalVariable(const GlobalVariable *GV) {
101 if (PromotedGlobals.count(GV))
102 // The global was promoted into a constant pool. It should not be emitted.
104 AsmPrinter::EmitGlobalVariable(GV);
107 /// runOnMachineFunction - This uses the EmitInstruction()
108 /// method to print assembly for each instruction.
110 bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
111 AFI = MF.getInfo<ARMFunctionInfo>();
112 MCP = MF.getConstantPool();
113 Subtarget = &MF.getSubtarget<ARMSubtarget>();
115 SetupMachineFunction(MF);
116 const Function* F = MF.getFunction();
117 const TargetMachine& TM = MF.getTarget();
119 // Collect all globals that had their storage promoted to a constant pool.
120 // Functions are emitted before variables, so this accumulates promoted
121 // globals from all functions in PromotedGlobals.
122 for (auto *GV : AFI->getGlobalsPromotedToConstantPool())
123 PromotedGlobals.insert(GV);
125 // Calculate this function's optimization goal.
126 unsigned OptimizationGoal;
127 if (F->hasFnAttribute(Attribute::OptimizeNone))
128 // For best debugging illusion, speed and small size sacrificed
129 OptimizationGoal = 6;
130 else if (F->optForMinSize())
131 // Aggressively for small size, speed and debug illusion sacrificed
132 OptimizationGoal = 4;
133 else if (F->optForSize())
134 // For small size, but speed and debugging illusion preserved
135 OptimizationGoal = 3;
136 else if (TM.getOptLevel() == CodeGenOpt::Aggressive)
137 // Aggressively for speed, small size and debug illusion sacrificed
138 OptimizationGoal = 2;
139 else if (TM.getOptLevel() > CodeGenOpt::None)
140 // For speed, but small size and good debug illusion preserved
141 OptimizationGoal = 1;
142 else // TM.getOptLevel() == CodeGenOpt::None
143 // For good debugging, but speed and small size preserved
144 OptimizationGoal = 5;
146 // Combine a new optimization goal with existing ones.
147 if (OptimizationGoals == -1) // uninitialized goals
148 OptimizationGoals = OptimizationGoal;
149 else if (OptimizationGoals != (int)OptimizationGoal) // conflicting goals
150 OptimizationGoals = 0;
152 if (Subtarget->isTargetCOFF()) {
153 bool Internal = F->hasInternalLinkage();
154 COFF::SymbolStorageClass Scl = Internal ? COFF::IMAGE_SYM_CLASS_STATIC
155 : COFF::IMAGE_SYM_CLASS_EXTERNAL;
156 int Type = COFF::IMAGE_SYM_DTYPE_FUNCTION << COFF::SCT_COMPLEX_TYPE_SHIFT;
158 OutStreamer->BeginCOFFSymbolDef(CurrentFnSym);
159 OutStreamer->EmitCOFFSymbolStorageClass(Scl);
160 OutStreamer->EmitCOFFSymbolType(Type);
161 OutStreamer->EndCOFFSymbolDef();
164 // Emit the rest of the function body.
167 // Emit the XRay table for this function.
170 // If we need V4T thumb mode Register Indirect Jump pads, emit them.
171 // These are created per function, rather than per TU, since it's
172 // relatively easy to exceed the thumb branch range within a TU.
173 if (! ThumbIndirectPads.empty()) {
174 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
176 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
177 OutStreamer->EmitLabel(ThumbIndirectPads[i].second);
178 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
179 .addReg(ThumbIndirectPads[i].first)
180 // Add predicate operands.
184 ThumbIndirectPads.clear();
187 // We didn't modify anything.
191 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
193 const MachineOperand &MO = MI->getOperand(OpNum);
194 unsigned TF = MO.getTargetFlags();
196 switch (MO.getType()) {
197 default: llvm_unreachable("<unknown operand type>");
198 case MachineOperand::MO_Register: {
199 unsigned Reg = MO.getReg();
200 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
201 assert(!MO.getSubReg() && "Subregs should be eliminated!");
202 if(ARM::GPRPairRegClass.contains(Reg)) {
203 const MachineFunction &MF = *MI->getParent()->getParent();
204 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
205 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
207 O << ARMInstPrinter::getRegisterName(Reg);
210 case MachineOperand::MO_Immediate: {
211 int64_t Imm = MO.getImm();
213 if (TF == ARMII::MO_LO16)
215 else if (TF == ARMII::MO_HI16)
220 case MachineOperand::MO_MachineBasicBlock:
221 MO.getMBB()->getSymbol()->print(O, MAI);
223 case MachineOperand::MO_GlobalAddress: {
224 const GlobalValue *GV = MO.getGlobal();
225 if (TF & ARMII::MO_LO16)
227 else if (TF & ARMII::MO_HI16)
229 GetARMGVSymbol(GV, TF)->print(O, MAI);
231 printOffset(MO.getOffset(), O);
234 case MachineOperand::MO_ConstantPoolIndex:
235 if (Subtarget->genExecuteOnly())
236 llvm_unreachable("execute-only should not generate constant pools");
237 GetCPISymbol(MO.getIndex())->print(O, MAI);
242 //===--------------------------------------------------------------------===//
244 MCSymbol *ARMAsmPrinter::
245 GetARMJTIPICJumpTableLabel(unsigned uid) const {
246 const DataLayout &DL = getDataLayout();
247 SmallString<60> Name;
248 raw_svector_ostream(Name) << DL.getPrivateGlobalPrefix() << "JTI"
249 << getFunctionNumber() << '_' << uid;
250 return OutContext.getOrCreateSymbol(Name);
253 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
254 unsigned AsmVariant, const char *ExtraCode,
256 // Does this asm operand have a single letter operand modifier?
257 if (ExtraCode && ExtraCode[0]) {
258 if (ExtraCode[1] != 0) return true; // Unknown modifier.
260 switch (ExtraCode[0]) {
262 // See if this is a generic print operand
263 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
264 case 'a': // Print as a memory address.
265 if (MI->getOperand(OpNum).isReg()) {
267 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
272 case 'c': // Don't print "#" before an immediate operand.
273 if (!MI->getOperand(OpNum).isImm())
275 O << MI->getOperand(OpNum).getImm();
277 case 'P': // Print a VFP double precision register.
278 case 'q': // Print a NEON quad precision register.
279 printOperand(MI, OpNum, O);
281 case 'y': // Print a VFP single precision register as indexed double.
282 if (MI->getOperand(OpNum).isReg()) {
283 unsigned Reg = MI->getOperand(OpNum).getReg();
284 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
285 // Find the 'd' register that has this 's' register as a sub-register,
286 // and determine the lane number.
287 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
288 if (!ARM::DPRRegClass.contains(*SR))
290 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
291 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
296 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
297 if (!MI->getOperand(OpNum).isImm())
299 O << ~(MI->getOperand(OpNum).getImm());
301 case 'L': // The low 16 bits of an immediate constant.
302 if (!MI->getOperand(OpNum).isImm())
304 O << (MI->getOperand(OpNum).getImm() & 0xffff);
306 case 'M': { // A register range suitable for LDM/STM.
307 if (!MI->getOperand(OpNum).isReg())
309 const MachineOperand &MO = MI->getOperand(OpNum);
310 unsigned RegBegin = MO.getReg();
311 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
312 // already got the operands in registers that are operands to the
313 // inline asm statement.
315 if (ARM::GPRPairRegClass.contains(RegBegin)) {
316 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
317 unsigned Reg0 = TRI->getSubReg(RegBegin, ARM::gsub_0);
318 O << ARMInstPrinter::getRegisterName(Reg0) << ", ";
319 RegBegin = TRI->getSubReg(RegBegin, ARM::gsub_1);
321 O << ARMInstPrinter::getRegisterName(RegBegin);
323 // FIXME: The register allocator not only may not have given us the
324 // registers in sequence, but may not be in ascending registers. This
325 // will require changes in the register allocator that'll need to be
326 // propagated down here if the operands change.
327 unsigned RegOps = OpNum + 1;
328 while (MI->getOperand(RegOps).isReg()) {
330 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
338 case 'R': // The most significant register of a pair.
339 case 'Q': { // The least significant register of a pair.
342 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
343 if (!FlagsOP.isImm())
345 unsigned Flags = FlagsOP.getImm();
347 // This operand may not be the one that actually provides the register. If
348 // it's tied to a previous one then we should refer instead to that one
349 // for registers and their classes.
351 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedIdx)) {
352 for (OpNum = InlineAsm::MIOp_FirstOperand; TiedIdx; --TiedIdx) {
353 unsigned OpFlags = MI->getOperand(OpNum).getImm();
354 OpNum += InlineAsm::getNumOperandRegisters(OpFlags) + 1;
356 Flags = MI->getOperand(OpNum).getImm();
358 // Later code expects OpNum to be pointing at the register rather than
363 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
365 InlineAsm::hasRegClassConstraint(Flags, RC);
366 if (RC == ARM::GPRPairRegClassID) {
369 const MachineOperand &MO = MI->getOperand(OpNum);
372 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
373 unsigned Reg = TRI->getSubReg(MO.getReg(), ExtraCode[0] == 'Q' ?
374 ARM::gsub_0 : ARM::gsub_1);
375 O << ARMInstPrinter::getRegisterName(Reg);
380 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
381 if (RegOp >= MI->getNumOperands())
383 const MachineOperand &MO = MI->getOperand(RegOp);
386 unsigned Reg = MO.getReg();
387 O << ARMInstPrinter::getRegisterName(Reg);
391 case 'e': // The low doubleword register of a NEON quad register.
392 case 'f': { // The high doubleword register of a NEON quad register.
393 if (!MI->getOperand(OpNum).isReg())
395 unsigned Reg = MI->getOperand(OpNum).getReg();
396 if (!ARM::QPRRegClass.contains(Reg))
398 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
399 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
400 ARM::dsub_0 : ARM::dsub_1);
401 O << ARMInstPrinter::getRegisterName(SubReg);
405 // This modifier is not yet supported.
406 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
408 case 'H': { // The highest-numbered register of a pair.
409 const MachineOperand &MO = MI->getOperand(OpNum);
412 const MachineFunction &MF = *MI->getParent()->getParent();
413 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
414 unsigned Reg = MO.getReg();
415 if(!ARM::GPRPairRegClass.contains(Reg))
417 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
418 O << ARMInstPrinter::getRegisterName(Reg);
424 printOperand(MI, OpNum, O);
428 bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
429 unsigned OpNum, unsigned AsmVariant,
430 const char *ExtraCode,
432 // Does this asm operand have a single letter operand modifier?
433 if (ExtraCode && ExtraCode[0]) {
434 if (ExtraCode[1] != 0) return true; // Unknown modifier.
436 switch (ExtraCode[0]) {
437 case 'A': // A memory operand for a VLD1/VST1 instruction.
438 default: return true; // Unknown modifier.
439 case 'm': // The base register of a memory operand.
440 if (!MI->getOperand(OpNum).isReg())
442 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
447 const MachineOperand &MO = MI->getOperand(OpNum);
448 assert(MO.isReg() && "unexpected inline asm memory operand");
449 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
453 static bool isThumb(const MCSubtargetInfo& STI) {
454 return STI.getFeatureBits()[ARM::ModeThumb];
457 void ARMAsmPrinter::emitInlineAsmEnd(const MCSubtargetInfo &StartInfo,
458 const MCSubtargetInfo *EndInfo) const {
459 // If either end mode is unknown (EndInfo == NULL) or different than
460 // the start mode, then restore the start mode.
461 const bool WasThumb = isThumb(StartInfo);
462 if (!EndInfo || WasThumb != isThumb(*EndInfo)) {
463 OutStreamer->EmitAssemblerFlag(WasThumb ? MCAF_Code16 : MCAF_Code32);
467 void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
468 const Triple &TT = TM.getTargetTriple();
469 // Use unified assembler syntax.
470 OutStreamer->EmitAssemblerFlag(MCAF_SyntaxUnified);
472 // Emit ARM Build Attributes
473 if (TT.isOSBinFormatELF())
476 // Use the triple's architecture and subarchitecture to determine
477 // if we're thumb for the purposes of the top level code16 assembler
479 bool isThumb = TT.getArch() == Triple::thumb ||
480 TT.getArch() == Triple::thumbeb ||
481 TT.getSubArch() == Triple::ARMSubArch_v7m ||
482 TT.getSubArch() == Triple::ARMSubArch_v6m;
483 if (!M.getModuleInlineAsm().empty() && isThumb)
484 OutStreamer->EmitAssemblerFlag(MCAF_Code16);
488 emitNonLazySymbolPointer(MCStreamer &OutStreamer, MCSymbol *StubLabel,
489 MachineModuleInfoImpl::StubValueTy &MCSym) {
491 OutStreamer.EmitLabel(StubLabel);
492 // .indirect_symbol _foo
493 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(), MCSA_IndirectSymbol);
496 // External to current translation unit.
497 OutStreamer.EmitIntValue(0, 4/*size*/);
499 // Internal to current translation unit.
501 // When we place the LSDA into the TEXT section, the type info
502 // pointers need to be indirect and pc-rel. We accomplish this by
503 // using NLPs; however, sometimes the types are local to the file.
504 // We need to fill in the value for the NLP in those cases.
505 OutStreamer.EmitValue(
506 MCSymbolRefExpr::create(MCSym.getPointer(), OutStreamer.getContext()),
511 void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
512 const Triple &TT = TM.getTargetTriple();
513 if (TT.isOSBinFormatMachO()) {
514 // All darwin targets use mach-o.
515 const TargetLoweringObjectFileMachO &TLOFMacho =
516 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
517 MachineModuleInfoMachO &MMIMacho =
518 MMI->getObjFileInfo<MachineModuleInfoMachO>();
520 // Output non-lazy-pointers for external and common global variables.
521 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
523 if (!Stubs.empty()) {
524 // Switch with ".non_lazy_symbol_pointer" directive.
525 OutStreamer->SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
528 for (auto &Stub : Stubs)
529 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
532 OutStreamer->AddBlankLine();
535 Stubs = MMIMacho.GetThreadLocalGVStubList();
536 if (!Stubs.empty()) {
537 // Switch with ".non_lazy_symbol_pointer" directive.
538 OutStreamer->SwitchSection(TLOFMacho.getThreadLocalPointerSection());
541 for (auto &Stub : Stubs)
542 emitNonLazySymbolPointer(*OutStreamer, Stub.first, Stub.second);
545 OutStreamer->AddBlankLine();
548 // Funny Darwin hack: This flag tells the linker that no global symbols
549 // contain code that falls through to other global symbols (e.g. the obvious
550 // implementation of multiple entry points). If this doesn't occur, the
551 // linker can safely perform dead code stripping. Since LLVM never
552 // generates code that does this, it is always safe to set.
553 OutStreamer->EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
556 if (TT.isOSBinFormatCOFF()) {
558 static_cast<const TargetLoweringObjectFileCOFF &>(getObjFileLowering());
561 raw_string_ostream OS(Flags);
563 for (const auto &Function : M)
564 TLOF.emitLinkerFlagsForGlobal(OS, &Function);
565 for (const auto &Global : M.globals())
566 TLOF.emitLinkerFlagsForGlobal(OS, &Global);
567 for (const auto &Alias : M.aliases())
568 TLOF.emitLinkerFlagsForGlobal(OS, &Alias);
572 // Output collected flags
573 if (!Flags.empty()) {
574 OutStreamer->SwitchSection(TLOF.getDrectveSection());
575 OutStreamer->EmitBytes(Flags);
579 // The last attribute to be emitted is ABI_optimization_goals
580 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
581 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
583 if (OptimizationGoals > 0 &&
584 (Subtarget->isTargetAEABI() || Subtarget->isTargetGNUAEABI() ||
585 Subtarget->isTargetMuslAEABI()))
586 ATS.emitAttribute(ARMBuildAttrs::ABI_optimization_goals, OptimizationGoals);
587 OptimizationGoals = -1;
589 ATS.finishAttributeSection();
592 //===----------------------------------------------------------------------===//
593 // Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
595 // The following seem like one-off assembler flags, but they actually need
596 // to appear in the .ARM.attributes section in ELF.
597 // Instead of subclassing the MCELFStreamer, we do the work here.
599 // Returns true if all functions have the same function attribute value.
600 // It also returns true when the module has no functions.
601 static bool checkFunctionsAttributeConsistency(const Module &M, StringRef Attr,
603 return !any_of(M, [&](const Function &F) {
604 return F.getFnAttribute(Attr).getValueAsString() != Value;
608 void ARMAsmPrinter::emitAttributes() {
609 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
610 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
612 ATS.emitTextAttribute(ARMBuildAttrs::conformance, "2.09");
614 ATS.switchVendor("aeabi");
616 // Compute ARM ELF Attributes based on the default subtarget that
617 // we'd have constructed. The existing ARM behavior isn't LTO clean
619 // FIXME: For ifunc related functions we could iterate over and look
620 // for a feature string that doesn't match the default one.
621 const Triple &TT = TM.getTargetTriple();
622 StringRef CPU = TM.getTargetCPU();
623 StringRef FS = TM.getTargetFeatureString();
624 std::string ArchFS = ARM_MC::ParseARMTriple(TT, CPU);
627 ArchFS = (Twine(ArchFS) + "," + FS).str();
631 const ARMBaseTargetMachine &ATM =
632 static_cast<const ARMBaseTargetMachine &>(TM);
633 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
635 // Emit build attributes for the available hardware.
636 ATS.emitTargetAttributes(STI);
638 // RW data addressing.
639 if (isPositionIndependent()) {
640 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
641 ARMBuildAttrs::AddressRWPCRel);
642 } else if (STI.isRWPI()) {
643 // RWPI specific attributes.
644 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RW_data,
645 ARMBuildAttrs::AddressRWSBRel);
648 // RO data addressing.
649 if (isPositionIndependent() || STI.isROPI()) {
650 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_RO_data,
651 ARMBuildAttrs::AddressROPCRel);
655 if (isPositionIndependent()) {
656 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
657 ARMBuildAttrs::AddressGOT);
659 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_GOT_use,
660 ARMBuildAttrs::AddressDirect);
664 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
667 TM.Options.FPDenormalMode == FPDenormal::PreserveSign)
668 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
669 ARMBuildAttrs::PreserveFPSign);
670 else if (checkFunctionsAttributeConsistency(*MMI->getModule(),
673 TM.Options.FPDenormalMode == FPDenormal::PositiveZero)
674 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
675 ARMBuildAttrs::PositiveZero);
676 else if (!TM.Options.UnsafeFPMath)
677 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
678 ARMBuildAttrs::IEEEDenormals);
680 if (!STI.hasVFP2()) {
681 // When the target doesn't have an FPU (by design or
682 // intention), the assumptions made on the software support
683 // mirror that of the equivalent hardware support *if it
684 // existed*. For v7 and better we indicate that denormals are
685 // flushed preserving sign, and for V6 we indicate that
686 // denormals are flushed to positive zero.
688 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
689 ARMBuildAttrs::PreserveFPSign);
690 } else if (STI.hasVFP3()) {
691 // In VFPv4, VFPv4U, VFPv3, or VFPv3U, it is preserved. That is,
692 // the sign bit of the zero matches the sign bit of the input or
693 // result that is being flushed to zero.
694 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_denormal,
695 ARMBuildAttrs::PreserveFPSign);
697 // For VFPv2 implementations it is implementation defined as
698 // to whether denormals are flushed to positive zero or to
699 // whatever the sign of zero is (ARM v7AR ARM 2.7.5). Historically
700 // LLVM has chosen to flush this to positive zero (most likely for
701 // GCC compatibility), so that's the chosen value here (the
702 // absence of its emission implies zero).
705 // Set FP exceptions and rounding
706 if (checkFunctionsAttributeConsistency(*MMI->getModule(),
707 "no-trapping-math", "true") ||
708 TM.Options.NoTrappingFPMath)
709 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
710 ARMBuildAttrs::Not_Allowed);
711 else if (!TM.Options.UnsafeFPMath) {
712 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_exceptions, ARMBuildAttrs::Allowed);
714 // If the user has permitted this code to choose the IEEE 754
715 // rounding at run-time, emit the rounding attribute.
716 if (TM.Options.HonorSignDependentRoundingFPMathOption)
717 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_rounding, ARMBuildAttrs::Allowed);
720 // TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath is the
721 // equivalent of GCC's -ffinite-math-only flag.
722 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
723 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
724 ARMBuildAttrs::Allowed);
726 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_number_model,
727 ARMBuildAttrs::AllowIEEE754);
729 // FIXME: add more flags to ARMBuildAttributes.h
730 // 8-bytes alignment stuff.
731 ATS.emitAttribute(ARMBuildAttrs::ABI_align_needed, 1);
732 ATS.emitAttribute(ARMBuildAttrs::ABI_align_preserved, 1);
734 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
735 if (STI.isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard)
736 ATS.emitAttribute(ARMBuildAttrs::ABI_VFP_args, ARMBuildAttrs::HardFPAAPCS);
738 // FIXME: To support emitting this build attribute as GCC does, the
739 // -mfp16-format option and associated plumbing must be
740 // supported. For now the __fp16 type is exposed by default, so this
741 // attribute should be emitted with value 1.
742 ATS.emitAttribute(ARMBuildAttrs::ABI_FP_16bit_format,
743 ARMBuildAttrs::FP16FormatIEEE);
746 if (const Module *SourceModule = MMI->getModule()) {
747 // ABI_PCS_wchar_t to indicate wchar_t width
748 // FIXME: There is no way to emit value 0 (wchar_t prohibited).
749 if (auto WCharWidthValue = mdconst::extract_or_null<ConstantInt>(
750 SourceModule->getModuleFlag("wchar_size"))) {
751 int WCharWidth = WCharWidthValue->getZExtValue();
752 assert((WCharWidth == 2 || WCharWidth == 4) &&
753 "wchar_t width must be 2 or 4 bytes");
754 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_wchar_t, WCharWidth);
757 // ABI_enum_size to indicate enum width
758 // FIXME: There is no way to emit value 0 (enums prohibited) or value 3
759 // (all enums contain a value needing 32 bits to encode).
760 if (auto EnumWidthValue = mdconst::extract_or_null<ConstantInt>(
761 SourceModule->getModuleFlag("min_enum_size"))) {
762 int EnumWidth = EnumWidthValue->getZExtValue();
763 assert((EnumWidth == 1 || EnumWidth == 4) &&
764 "Minimum enum width must be 1 or 4 bytes");
765 int EnumBuildAttr = EnumWidth == 1 ? 1 : 2;
766 ATS.emitAttribute(ARMBuildAttrs::ABI_enum_size, EnumBuildAttr);
771 // We currently do not support using R9 as the TLS pointer.
773 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
774 ARMBuildAttrs::R9IsSB);
775 else if (STI.isR9Reserved())
776 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
777 ARMBuildAttrs::R9Reserved);
779 ATS.emitAttribute(ARMBuildAttrs::ABI_PCS_R9_use,
780 ARMBuildAttrs::R9IsGPR);
783 //===----------------------------------------------------------------------===//
785 static MCSymbol *getPICLabel(StringRef Prefix, unsigned FunctionNumber,
786 unsigned LabelId, MCContext &Ctx) {
788 MCSymbol *Label = Ctx.getOrCreateSymbol(Twine(Prefix)
789 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
793 static MCSymbolRefExpr::VariantKind
794 getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
796 case ARMCP::no_modifier:
797 return MCSymbolRefExpr::VK_None;
799 return MCSymbolRefExpr::VK_TLSGD;
801 return MCSymbolRefExpr::VK_TPOFF;
802 case ARMCP::GOTTPOFF:
803 return MCSymbolRefExpr::VK_GOTTPOFF;
805 return MCSymbolRefExpr::VK_ARM_SBREL;
806 case ARMCP::GOT_PREL:
807 return MCSymbolRefExpr::VK_ARM_GOT_PREL;
809 return MCSymbolRefExpr::VK_SECREL;
811 llvm_unreachable("Invalid ARMCPModifier!");
814 MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV,
815 unsigned char TargetFlags) {
816 if (Subtarget->isTargetMachO()) {
818 (TargetFlags & ARMII::MO_NONLAZY) && Subtarget->isGVIndirectSymbol(GV);
821 return getSymbol(GV);
823 // FIXME: Remove this when Darwin transition to @GOT like syntax.
824 MCSymbol *MCSym = getSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
825 MachineModuleInfoMachO &MMIMachO =
826 MMI->getObjFileInfo<MachineModuleInfoMachO>();
827 MachineModuleInfoImpl::StubValueTy &StubSym =
828 GV->isThreadLocal() ? MMIMachO.getThreadLocalGVStubEntry(MCSym)
829 : MMIMachO.getGVStubEntry(MCSym);
831 if (!StubSym.getPointer())
832 StubSym = MachineModuleInfoImpl::StubValueTy(getSymbol(GV),
833 !GV->hasInternalLinkage());
835 } else if (Subtarget->isTargetCOFF()) {
836 assert(Subtarget->isTargetWindows() &&
837 "Windows is the only supported COFF target");
839 bool IsIndirect = (TargetFlags & ARMII::MO_DLLIMPORT);
841 return getSymbol(GV);
843 SmallString<128> Name;
845 getNameWithPrefix(Name, GV);
847 return OutContext.getOrCreateSymbol(Name);
848 } else if (Subtarget->isTargetELF()) {
849 return getSymbol(GV);
851 llvm_unreachable("unexpected target");
855 EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
856 const DataLayout &DL = getDataLayout();
857 int Size = DL.getTypeAllocSize(MCPV->getType());
859 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
861 if (ACPV->isPromotedGlobal()) {
862 // This constant pool entry is actually a global whose storage has been
863 // promoted into the constant pool. This global may be referenced still
864 // by debug information, and due to the way AsmPrinter is set up, the debug
865 // info is immutable by the time we decide to promote globals to constant
866 // pools. Because of this, we need to ensure we emit a symbol for the global
867 // with private linkage (the default) so debug info can refer to it.
869 // However, if this global is promoted into several functions we must ensure
870 // we don't try and emit duplicate symbols!
871 auto *ACPC = cast<ARMConstantPoolConstant>(ACPV);
872 auto *GV = ACPC->getPromotedGlobal();
873 if (!EmittedPromotedGlobalLabels.count(GV)) {
874 MCSymbol *GVSym = getSymbol(GV);
875 OutStreamer->EmitLabel(GVSym);
876 EmittedPromotedGlobalLabels.insert(GV);
878 return EmitGlobalConstant(DL, ACPC->getPromotedGlobalInit());
882 if (ACPV->isLSDA()) {
883 MCSym = getCurExceptionSym();
884 } else if (ACPV->isBlockAddress()) {
885 const BlockAddress *BA =
886 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
887 MCSym = GetBlockAddressSymbol(BA);
888 } else if (ACPV->isGlobalValue()) {
889 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
891 // On Darwin, const-pool entries may get the "FOO$non_lazy_ptr" mangling, so
892 // flag the global as MO_NONLAZY.
893 unsigned char TF = Subtarget->isTargetMachO() ? ARMII::MO_NONLAZY : 0;
894 MCSym = GetARMGVSymbol(GV, TF);
895 } else if (ACPV->isMachineBasicBlock()) {
896 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
897 MCSym = MBB->getSymbol();
899 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
900 auto Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
901 MCSym = GetExternalSymbolSymbol(Sym);
904 // Create an MCSymbol for the reference.
906 MCSymbolRefExpr::create(MCSym, getModifierVariantKind(ACPV->getModifier()),
909 if (ACPV->getPCAdjustment()) {
911 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
912 ACPV->getLabelId(), OutContext);
913 const MCExpr *PCRelExpr = MCSymbolRefExpr::create(PCLabel, OutContext);
915 MCBinaryExpr::createAdd(PCRelExpr,
916 MCConstantExpr::create(ACPV->getPCAdjustment(),
919 if (ACPV->mustAddCurrentAddress()) {
920 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
921 // label, so just emit a local label end reference that instead.
922 MCSymbol *DotSym = OutContext.createTempSymbol();
923 OutStreamer->EmitLabel(DotSym);
924 const MCExpr *DotExpr = MCSymbolRefExpr::create(DotSym, OutContext);
925 PCRelExpr = MCBinaryExpr::createSub(PCRelExpr, DotExpr, OutContext);
927 Expr = MCBinaryExpr::createSub(Expr, PCRelExpr, OutContext);
929 OutStreamer->EmitValue(Expr, Size);
932 void ARMAsmPrinter::EmitJumpTableAddrs(const MachineInstr *MI) {
933 const MachineOperand &MO1 = MI->getOperand(1);
934 unsigned JTI = MO1.getIndex();
936 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
940 // Emit a label for the jump table.
941 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
942 OutStreamer->EmitLabel(JTISymbol);
944 // Mark the jump table as data-in-code.
945 OutStreamer->EmitDataRegion(MCDR_DataRegionJT32);
947 // Emit each entry of the table.
948 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
949 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
950 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
952 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
953 MachineBasicBlock *MBB = JTBBs[i];
954 // Construct an MCExpr for the entry. We want a value of the form:
955 // (BasicBlockAddr - TableBeginAddr)
957 // For example, a table with entries jumping to basic blocks BB0 and BB1
960 // .word (LBB0 - LJTI_0_0)
961 // .word (LBB1 - LJTI_0_0)
962 const MCExpr *Expr = MCSymbolRefExpr::create(MBB->getSymbol(), OutContext);
964 if (isPositionIndependent() || Subtarget->isROPI())
965 Expr = MCBinaryExpr::createSub(Expr, MCSymbolRefExpr::create(JTISymbol,
968 // If we're generating a table of Thumb addresses in static relocation
969 // model, we need to add one to keep interworking correctly.
970 else if (AFI->isThumbFunction())
971 Expr = MCBinaryExpr::createAdd(Expr, MCConstantExpr::create(1,OutContext),
973 OutStreamer->EmitValue(Expr, 4);
975 // Mark the end of jump table data-in-code region.
976 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
979 void ARMAsmPrinter::EmitJumpTableInsts(const MachineInstr *MI) {
980 const MachineOperand &MO1 = MI->getOperand(1);
981 unsigned JTI = MO1.getIndex();
983 // Make sure the Thumb jump table is 4-byte aligned. This will be a nop for
987 // Emit a label for the jump table.
988 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
989 OutStreamer->EmitLabel(JTISymbol);
991 // Emit each entry of the table.
992 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
993 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
994 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
996 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
997 MachineBasicBlock *MBB = JTBBs[i];
998 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1000 // If this isn't a TBB or TBH, the entries are direct branch instructions.
1001 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2B)
1002 .addExpr(MBBSymbolExpr)
1008 void ARMAsmPrinter::EmitJumpTableTBInst(const MachineInstr *MI,
1009 unsigned OffsetWidth) {
1010 assert((OffsetWidth == 1 || OffsetWidth == 2) && "invalid tbb/tbh width");
1011 const MachineOperand &MO1 = MI->getOperand(1);
1012 unsigned JTI = MO1.getIndex();
1014 if (Subtarget->isThumb1Only())
1017 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel(JTI);
1018 OutStreamer->EmitLabel(JTISymbol);
1020 // Emit each entry of the table.
1021 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1022 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1023 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
1025 // Mark the jump table as data-in-code.
1026 OutStreamer->EmitDataRegion(OffsetWidth == 1 ? MCDR_DataRegionJT8
1027 : MCDR_DataRegionJT16);
1029 for (auto MBB : JTBBs) {
1030 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::create(MBB->getSymbol(),
1032 // Otherwise it's an offset from the dispatch instruction. Construct an
1033 // MCExpr for the entry. We want a value of the form:
1034 // (BasicBlockAddr - TBBInstAddr + 4) / 2
1036 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1039 // .byte (LBB0 - (LCPI0_0 + 4)) / 2
1040 // .byte (LBB1 - (LCPI0_0 + 4)) / 2
1041 // where LCPI0_0 is a label defined just before the TBB instruction using
1043 MCSymbol *TBInstPC = GetCPISymbol(MI->getOperand(0).getImm());
1044 const MCExpr *Expr = MCBinaryExpr::createAdd(
1045 MCSymbolRefExpr::create(TBInstPC, OutContext),
1046 MCConstantExpr::create(4, OutContext), OutContext);
1047 Expr = MCBinaryExpr::createSub(MBBSymbolExpr, Expr, OutContext);
1048 Expr = MCBinaryExpr::createDiv(Expr, MCConstantExpr::create(2, OutContext),
1050 OutStreamer->EmitValue(Expr, OffsetWidth);
1052 // Mark the end of jump table data-in-code region. 32-bit offsets use
1053 // actual branch instructions here, so we don't mark those as a data-region
1055 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1057 // Make sure the next instruction is 2-byte aligned.
1061 void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1062 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1063 "Only instruction which are involved into frame setup code are allowed");
1065 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1066 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1067 const MachineFunction &MF = *MI->getParent()->getParent();
1068 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo();
1069 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
1071 unsigned FramePtr = RegInfo->getFrameRegister(MF);
1072 unsigned Opc = MI->getOpcode();
1073 unsigned SrcReg, DstReg;
1075 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1076 // Two special cases:
1077 // 1) tPUSH does not have src/dst regs.
1078 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1079 // load. Yes, this is pretty fragile, but for now I don't see better
1081 SrcReg = DstReg = ARM::SP;
1083 SrcReg = MI->getOperand(1).getReg();
1084 DstReg = MI->getOperand(0).getReg();
1087 // Try to figure out the unwinding opcode out of src / dst regs.
1088 if (MI->mayStore()) {
1090 assert(DstReg == ARM::SP &&
1091 "Only stack pointer as a destination reg is supported");
1093 SmallVector<unsigned, 4> RegList;
1094 // Skip src & dst reg, and pred ops.
1095 unsigned StartOp = 2 + 2;
1096 // Use all the operands.
1097 unsigned NumOffset = 0;
1102 llvm_unreachable("Unsupported opcode for unwinding information");
1104 // Special case here: no src & dst reg, but two extra imp ops.
1105 StartOp = 2; NumOffset = 2;
1107 case ARM::STMDB_UPD:
1108 case ARM::t2STMDB_UPD:
1109 case ARM::VSTMDDB_UPD:
1110 assert(SrcReg == ARM::SP &&
1111 "Only stack pointer as a source reg is supported");
1112 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
1114 const MachineOperand &MO = MI->getOperand(i);
1115 // Actually, there should never be any impdef stuff here. Skip it
1116 // temporary to workaround PR11902.
1117 if (MO.isImplicit())
1119 RegList.push_back(MO.getReg());
1122 case ARM::STR_PRE_IMM:
1123 case ARM::STR_PRE_REG:
1124 case ARM::t2STR_PRE:
1125 assert(MI->getOperand(2).getReg() == ARM::SP &&
1126 "Only stack pointer as a source reg is supported");
1127 RegList.push_back(SrcReg);
1130 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM)
1131 ATS.emitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1133 // Changes of stack / frame pointer.
1134 if (SrcReg == ARM::SP) {
1139 llvm_unreachable("Unsupported opcode for unwinding information");
1146 Offset = -MI->getOperand(2).getImm();
1150 Offset = MI->getOperand(2).getImm();
1153 Offset = MI->getOperand(2).getImm()*4;
1157 Offset = -MI->getOperand(2).getImm()*4;
1159 case ARM::tLDRpci: {
1160 // Grab the constpool index and check, whether it corresponds to
1161 // original or cloned constpool entry.
1162 unsigned CPI = MI->getOperand(1).getIndex();
1163 const MachineConstantPool *MCP = MF.getConstantPool();
1164 if (CPI >= MCP->getConstants().size())
1165 CPI = AFI.getOriginalCPIdx(CPI);
1166 assert(CPI != -1U && "Invalid constpool index");
1168 // Derive the actual offset.
1169 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1170 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1171 // FIXME: Check for user, it should be "add" instruction!
1172 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
1177 if (MAI->getExceptionHandlingType() == ExceptionHandling::ARM) {
1178 if (DstReg == FramePtr && FramePtr != ARM::SP)
1179 // Set-up of the frame pointer. Positive values correspond to "add"
1181 ATS.emitSetFP(FramePtr, ARM::SP, -Offset);
1182 else if (DstReg == ARM::SP) {
1183 // Change of SP by an offset. Positive values correspond to "sub"
1185 ATS.emitPad(Offset);
1187 // Move of SP to a register. Positive values correspond to an "add"
1189 ATS.emitMovSP(DstReg, -Offset);
1192 } else if (DstReg == ARM::SP) {
1194 llvm_unreachable("Unsupported opcode for unwinding information");
1198 llvm_unreachable("Unsupported opcode for unwinding information");
1203 // Simple pseudo-instructions have their lowering (with expansion to real
1204 // instructions) auto-generated.
1205 #include "ARMGenMCPseudoLowering.inc"
1207 void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
1208 const DataLayout &DL = getDataLayout();
1209 MCTargetStreamer &TS = *OutStreamer->getTargetStreamer();
1210 ARMTargetStreamer &ATS = static_cast<ARMTargetStreamer &>(TS);
1212 // If we just ended a constant pool, mark it as such.
1213 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1214 OutStreamer->EmitDataRegion(MCDR_DataRegionEnd);
1215 InConstantPool = false;
1218 // Emit unwinding stuff for frame-related instructions
1219 if (Subtarget->isTargetEHABICompatible() &&
1220 MI->getFlag(MachineInstr::FrameSetup))
1221 EmitUnwindingInstruction(MI);
1223 // Do any auto-generated pseudo lowerings.
1224 if (emitPseudoExpansionLowering(*OutStreamer, MI))
1227 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1228 "Pseudo flag setting opcode should be expanded early");
1230 // Check for manual lowerings.
1231 unsigned Opc = MI->getOpcode();
1233 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
1234 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
1236 case ARM::tLEApcrel:
1237 case ARM::t2LEApcrel: {
1238 // FIXME: Need to also handle globals and externals
1239 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
1240 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1241 ARM::t2LEApcrel ? ARM::t2ADR
1242 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1244 .addReg(MI->getOperand(0).getReg())
1245 .addExpr(MCSymbolRefExpr::create(CPISymbol, OutContext))
1246 // Add predicate operands.
1247 .addImm(MI->getOperand(2).getImm())
1248 .addReg(MI->getOperand(3).getReg()));
1251 case ARM::LEApcrelJT:
1252 case ARM::tLEApcrelJT:
1253 case ARM::t2LEApcrelJT: {
1254 MCSymbol *JTIPICSymbol =
1255 GetARMJTIPICJumpTableLabel(MI->getOperand(1).getIndex());
1256 EmitToStreamer(*OutStreamer, MCInstBuilder(MI->getOpcode() ==
1257 ARM::t2LEApcrelJT ? ARM::t2ADR
1258 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1260 .addReg(MI->getOperand(0).getReg())
1261 .addExpr(MCSymbolRefExpr::create(JTIPICSymbol, OutContext))
1262 // Add predicate operands.
1263 .addImm(MI->getOperand(2).getImm())
1264 .addReg(MI->getOperand(3).getReg()));
1267 // Darwin call instructions are just normal call instructions with different
1268 // clobber semantics (they clobber R9).
1269 case ARM::BX_CALL: {
1270 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1273 // Add predicate operands.
1276 // Add 's' bit operand (always reg0 for this)
1279 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1280 .addReg(MI->getOperand(0).getReg()));
1283 case ARM::tBX_CALL: {
1284 if (Subtarget->hasV5TOps())
1285 llvm_unreachable("Expected BLX to be selected for v5t+");
1287 // On ARM v4t, when doing a call from thumb mode, we need to ensure
1288 // that the saved lr has its LSB set correctly (the arch doesn't
1290 // So here we generate a bl to a small jump pad that does bx rN.
1291 // The jump pads are emitted after the function body.
1293 unsigned TReg = MI->getOperand(0).getReg();
1294 MCSymbol *TRegSym = nullptr;
1295 for (unsigned i = 0, e = ThumbIndirectPads.size(); i < e; i++) {
1296 if (ThumbIndirectPads[i].first == TReg) {
1297 TRegSym = ThumbIndirectPads[i].second;
1303 TRegSym = OutContext.createTempSymbol();
1304 ThumbIndirectPads.push_back(std::make_pair(TReg, TRegSym));
1307 // Create a link-saving branch to the Reg Indirect Jump Pad.
1308 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBL)
1309 // Predicate comes first here.
1310 .addImm(ARMCC::AL).addReg(0)
1311 .addExpr(MCSymbolRefExpr::create(TRegSym, OutContext)));
1314 case ARM::BMOVPCRX_CALL: {
1315 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1318 // Add predicate operands.
1321 // Add 's' bit operand (always reg0 for this)
1324 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1326 .addReg(MI->getOperand(0).getReg())
1327 // Add predicate operands.
1330 // Add 's' bit operand (always reg0 for this)
1334 case ARM::BMOVPCB_CALL: {
1335 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVr)
1338 // Add predicate operands.
1341 // Add 's' bit operand (always reg0 for this)
1344 const MachineOperand &Op = MI->getOperand(0);
1345 const GlobalValue *GV = Op.getGlobal();
1346 const unsigned TF = Op.getTargetFlags();
1347 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1348 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1349 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::Bcc)
1351 // Add predicate operands.
1356 case ARM::MOVi16_ga_pcrel:
1357 case ARM::t2MOVi16_ga_pcrel: {
1359 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
1360 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1362 unsigned TF = MI->getOperand(1).getTargetFlags();
1363 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1364 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1365 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1367 MCSymbol *LabelSym =
1368 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1369 MI->getOperand(2).getImm(), OutContext);
1370 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1371 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1372 const MCExpr *PCRelExpr =
1373 ARMMCExpr::createLower16(MCBinaryExpr::createSub(GVSymExpr,
1374 MCBinaryExpr::createAdd(LabelSymExpr,
1375 MCConstantExpr::create(PCAdj, OutContext),
1376 OutContext), OutContext), OutContext);
1377 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1379 // Add predicate operands.
1380 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1381 TmpInst.addOperand(MCOperand::createReg(0));
1382 // Add 's' bit operand (always reg0 for this)
1383 TmpInst.addOperand(MCOperand::createReg(0));
1384 EmitToStreamer(*OutStreamer, TmpInst);
1387 case ARM::MOVTi16_ga_pcrel:
1388 case ARM::t2MOVTi16_ga_pcrel: {
1390 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1391 ? ARM::MOVTi16 : ARM::t2MOVTi16);
1392 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1393 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1395 unsigned TF = MI->getOperand(2).getTargetFlags();
1396 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1397 MCSymbol *GVSym = GetARMGVSymbol(GV, TF);
1398 const MCExpr *GVSymExpr = MCSymbolRefExpr::create(GVSym, OutContext);
1400 MCSymbol *LabelSym =
1401 getPICLabel(DL.getPrivateGlobalPrefix(), getFunctionNumber(),
1402 MI->getOperand(3).getImm(), OutContext);
1403 const MCExpr *LabelSymExpr= MCSymbolRefExpr::create(LabelSym, OutContext);
1404 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1405 const MCExpr *PCRelExpr =
1406 ARMMCExpr::createUpper16(MCBinaryExpr::createSub(GVSymExpr,
1407 MCBinaryExpr::createAdd(LabelSymExpr,
1408 MCConstantExpr::create(PCAdj, OutContext),
1409 OutContext), OutContext), OutContext);
1410 TmpInst.addOperand(MCOperand::createExpr(PCRelExpr));
1411 // Add predicate operands.
1412 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1413 TmpInst.addOperand(MCOperand::createReg(0));
1414 // Add 's' bit operand (always reg0 for this)
1415 TmpInst.addOperand(MCOperand::createReg(0));
1416 EmitToStreamer(*OutStreamer, TmpInst);
1419 case ARM::tPICADD: {
1420 // This is a pseudo op for a label + instruction sequence, which looks like:
1423 // This adds the address of LPC0 to r0.
1426 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1427 getFunctionNumber(),
1428 MI->getOperand(2).getImm(), OutContext));
1430 // Form and emit the add.
1431 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1432 .addReg(MI->getOperand(0).getReg())
1433 .addReg(MI->getOperand(0).getReg())
1435 // Add predicate operands.
1441 // This is a pseudo op for a label + instruction sequence, which looks like:
1444 // This adds the address of LPC0 to r0.
1447 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1448 getFunctionNumber(),
1449 MI->getOperand(2).getImm(), OutContext));
1451 // Form and emit the add.
1452 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1453 .addReg(MI->getOperand(0).getReg())
1455 .addReg(MI->getOperand(1).getReg())
1456 // Add predicate operands.
1457 .addImm(MI->getOperand(3).getImm())
1458 .addReg(MI->getOperand(4).getReg())
1459 // Add 's' bit operand (always reg0 for this)
1470 case ARM::PICLDRSH: {
1471 // This is a pseudo op for a label + instruction sequence, which looks like:
1474 // The LCP0 label is referenced by a constant pool entry in order to get
1475 // a PC-relative address at the ldr instruction.
1478 OutStreamer->EmitLabel(getPICLabel(DL.getPrivateGlobalPrefix(),
1479 getFunctionNumber(),
1480 MI->getOperand(2).getImm(), OutContext));
1482 // Form and emit the load
1484 switch (MI->getOpcode()) {
1486 llvm_unreachable("Unexpected opcode!");
1487 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1488 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
1489 case ARM::PICSTRH: Opcode = ARM::STRH; break;
1490 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
1491 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
1492 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1493 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1494 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1496 EmitToStreamer(*OutStreamer, MCInstBuilder(Opcode)
1497 .addReg(MI->getOperand(0).getReg())
1499 .addReg(MI->getOperand(1).getReg())
1501 // Add predicate operands.
1502 .addImm(MI->getOperand(3).getImm())
1503 .addReg(MI->getOperand(4).getReg()));
1507 case ARM::CONSTPOOL_ENTRY: {
1508 if (Subtarget->genExecuteOnly())
1509 llvm_unreachable("execute-only should not generate constant pools");
1511 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1512 /// in the function. The first operand is the ID# for this instruction, the
1513 /// second is the index into the MachineConstantPool that this is, the third
1514 /// is the size in bytes of this constant pool entry.
1515 /// The required alignment is specified on the basic block holding this MI.
1516 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1517 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1519 // If this is the first entry of the pool, mark it.
1520 if (!InConstantPool) {
1521 OutStreamer->EmitDataRegion(MCDR_DataRegion);
1522 InConstantPool = true;
1525 OutStreamer->EmitLabel(GetCPISymbol(LabelId));
1527 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1528 if (MCPE.isMachineConstantPoolEntry())
1529 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1531 EmitGlobalConstant(DL, MCPE.Val.ConstVal);
1534 case ARM::JUMPTABLE_ADDRS:
1535 EmitJumpTableAddrs(MI);
1537 case ARM::JUMPTABLE_INSTS:
1538 EmitJumpTableInsts(MI);
1540 case ARM::JUMPTABLE_TBB:
1541 case ARM::JUMPTABLE_TBH:
1542 EmitJumpTableTBInst(MI, MI->getOpcode() == ARM::JUMPTABLE_TBB ? 1 : 2);
1544 case ARM::t2BR_JT: {
1545 // Lower and emit the instruction itself, then the jump table following it.
1546 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1548 .addReg(MI->getOperand(0).getReg())
1549 // Add predicate operands.
1555 case ARM::t2TBH_JT: {
1556 unsigned Opc = MI->getOpcode() == ARM::t2TBB_JT ? ARM::t2TBB : ARM::t2TBH;
1557 // Lower and emit the PC label, then the instruction itself.
1558 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1559 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1560 .addReg(MI->getOperand(0).getReg())
1561 .addReg(MI->getOperand(1).getReg())
1562 // Add predicate operands.
1568 case ARM::tTBH_JT: {
1570 bool Is8Bit = MI->getOpcode() == ARM::tTBB_JT;
1571 unsigned Base = MI->getOperand(0).getReg();
1572 unsigned Idx = MI->getOperand(1).getReg();
1573 assert(MI->getOperand(1).isKill() && "We need the index register as scratch!");
1575 // Multiply up idx if necessary.
1577 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1582 // Add predicate operands.
1586 if (Base == ARM::PC) {
1587 // TBB [base, idx] =
1588 // ADDS idx, idx, base
1589 // LDRB idx, [idx, #4] ; or LDRH if TBH
1593 // When using PC as the base, it's important that there is no padding
1594 // between the last ADDS and the start of the jump table. The jump table
1595 // is 4-byte aligned, so we ensure we're 4 byte aligned here too.
1597 // FIXME: Ideally we could vary the LDRB index based on the padding
1598 // between the sequence and jump table, however that relies on MCExprs
1599 // for load indexes which are currently not supported.
1600 OutStreamer->EmitCodeAlignment(4);
1601 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1605 // Add predicate operands.
1609 unsigned Opc = Is8Bit ? ARM::tLDRBi : ARM::tLDRHi;
1610 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1613 .addImm(Is8Bit ? 4 : 2)
1614 // Add predicate operands.
1618 // TBB [base, idx] =
1619 // LDRB idx, [base, idx] ; or LDRH if TBH
1623 unsigned Opc = Is8Bit ? ARM::tLDRBr : ARM::tLDRHr;
1624 EmitToStreamer(*OutStreamer, MCInstBuilder(Opc)
1628 // Add predicate operands.
1633 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLSLri)
1638 // Add predicate operands.
1642 OutStreamer->EmitLabel(GetCPISymbol(MI->getOperand(3).getImm()));
1643 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDhirr)
1647 // Add predicate operands.
1654 // Lower and emit the instruction itself, then the jump table following it.
1657 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
1658 ARM::MOVr : ARM::tMOVr;
1659 TmpInst.setOpcode(Opc);
1660 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1661 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1662 // Add predicate operands.
1663 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1664 TmpInst.addOperand(MCOperand::createReg(0));
1665 // Add 's' bit operand (always reg0 for this)
1666 if (Opc == ARM::MOVr)
1667 TmpInst.addOperand(MCOperand::createReg(0));
1668 EmitToStreamer(*OutStreamer, TmpInst);
1672 // Lower and emit the instruction itself, then the jump table following it.
1675 if (MI->getOperand(1).getReg() == 0) {
1677 TmpInst.setOpcode(ARM::LDRi12);
1678 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1679 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1680 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(2).getImm()));
1682 TmpInst.setOpcode(ARM::LDRrs);
1683 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
1684 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1685 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(1).getReg()));
1686 TmpInst.addOperand(MCOperand::createImm(0));
1688 // Add predicate operands.
1689 TmpInst.addOperand(MCOperand::createImm(ARMCC::AL));
1690 TmpInst.addOperand(MCOperand::createReg(0));
1691 EmitToStreamer(*OutStreamer, TmpInst);
1694 case ARM::BR_JTadd: {
1695 // Lower and emit the instruction itself, then the jump table following it.
1696 // add pc, target, idx
1697 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDrr)
1699 .addReg(MI->getOperand(0).getReg())
1700 .addReg(MI->getOperand(1).getReg())
1701 // Add predicate operands.
1704 // Add 's' bit operand (always reg0 for this)
1709 OutStreamer->EmitZeros(MI->getOperand(1).getImm());
1712 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1713 // FIXME: Remove this special case when they do.
1714 if (!Subtarget->isTargetMachO()) {
1715 uint32_t Val = 0xe7ffdefeUL;
1716 OutStreamer->AddComment("trap");
1722 case ARM::TRAPNaCl: {
1723 uint32_t Val = 0xe7fedef0UL;
1724 OutStreamer->AddComment("trap");
1729 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1730 // FIXME: Remove this special case when they do.
1731 if (!Subtarget->isTargetMachO()) {
1732 uint16_t Val = 0xdefe;
1733 OutStreamer->AddComment("trap");
1734 ATS.emitInst(Val, 'n');
1739 case ARM::t2Int_eh_sjlj_setjmp:
1740 case ARM::t2Int_eh_sjlj_setjmp_nofp:
1741 case ARM::tInt_eh_sjlj_setjmp: {
1742 // Two incoming args: GPR:$src, GPR:$val
1745 // str $val, [$src, #4]
1750 unsigned SrcReg = MI->getOperand(0).getReg();
1751 unsigned ValReg = MI->getOperand(1).getReg();
1752 MCSymbol *Label = OutContext.createTempSymbol("SJLJEH", false, true);
1753 OutStreamer->AddComment("eh_setjmp begin");
1754 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1761 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tADDi3)
1771 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tSTRi)
1774 // The offset immediate is #4. The operand value is scaled by 4 for the
1775 // tSTR instruction.
1781 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1789 const MCExpr *SymbolExpr = MCSymbolRefExpr::create(Label, OutContext);
1790 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tB)
1791 .addExpr(SymbolExpr)
1795 OutStreamer->AddComment("eh_setjmp end");
1796 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVi8)
1804 OutStreamer->EmitLabel(Label);
1808 case ARM::Int_eh_sjlj_setjmp_nofp:
1809 case ARM::Int_eh_sjlj_setjmp: {
1810 // Two incoming args: GPR:$src, GPR:$val
1812 // str $val, [$src, #+4]
1816 unsigned SrcReg = MI->getOperand(0).getReg();
1817 unsigned ValReg = MI->getOperand(1).getReg();
1819 OutStreamer->AddComment("eh_setjmp begin");
1820 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1827 // 's' bit operand (always reg0 for this).
1830 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::STRi12)
1838 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1844 // 's' bit operand (always reg0 for this).
1847 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::ADDri)
1854 // 's' bit operand (always reg0 for this).
1857 OutStreamer->AddComment("eh_setjmp end");
1858 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::MOVi)
1864 // 's' bit operand (always reg0 for this).
1868 case ARM::Int_eh_sjlj_longjmp: {
1869 // ldr sp, [$src, #8]
1870 // ldr $scratch, [$src, #4]
1873 unsigned SrcReg = MI->getOperand(0).getReg();
1874 unsigned ScratchReg = MI->getOperand(1).getReg();
1875 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1883 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1891 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::LDRi12)
1899 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::BX)
1906 case ARM::tInt_eh_sjlj_longjmp: {
1907 // ldr $scratch, [$src, #8]
1909 // ldr $scratch, [$src, #4]
1912 unsigned SrcReg = MI->getOperand(0).getReg();
1913 unsigned ScratchReg = MI->getOperand(1).getReg();
1915 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1918 // The offset immediate is #8. The operand value is scaled by 4 for the
1919 // tLDR instruction.
1925 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tMOVr)
1932 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1940 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tLDRi)
1948 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::tBX)
1955 case ARM::tInt_WIN_eh_sjlj_longjmp: {
1956 // ldr.w r11, [$src, #0]
1957 // ldr.w sp, [$src, #8]
1958 // ldr.w pc, [$src, #4]
1960 unsigned SrcReg = MI->getOperand(0).getReg();
1962 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
1969 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
1976 EmitToStreamer(*OutStreamer, MCInstBuilder(ARM::t2LDRi12)
1985 case ARM::PATCHABLE_FUNCTION_ENTER:
1986 LowerPATCHABLE_FUNCTION_ENTER(*MI);
1988 case ARM::PATCHABLE_FUNCTION_EXIT:
1989 LowerPATCHABLE_FUNCTION_EXIT(*MI);
1991 case ARM::PATCHABLE_TAIL_CALL:
1992 LowerPATCHABLE_TAIL_CALL(*MI);
1997 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
1999 EmitToStreamer(*OutStreamer, TmpInst);
2002 //===----------------------------------------------------------------------===//
2003 // Target Registry Stuff
2004 //===----------------------------------------------------------------------===//
2006 // Force static initialization.
2007 extern "C" void LLVMInitializeARMAsmPrinter() {
2008 RegisterAsmPrinter<ARMAsmPrinter> X(getTheARMLETarget());
2009 RegisterAsmPrinter<ARMAsmPrinter> Y(getTheARMBETarget());
2010 RegisterAsmPrinter<ARMAsmPrinter> A(getTheThumbLETarget());
2011 RegisterAsmPrinter<ARMAsmPrinter> B(getTheThumbBETarget());