1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMFeatures.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "MCTargetDesc/ARMBaseInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallSet.h"
26 #include "llvm/ADT/SmallVector.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineMemOperand.h"
36 #include "llvm/CodeGen/MachineOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
39 #include "llvm/CodeGen/SelectionDAGNodes.h"
40 #include "llvm/CodeGen/TargetInstrInfo.h"
41 #include "llvm/CodeGen/TargetRegisterInfo.h"
42 #include "llvm/CodeGen/TargetSchedule.h"
43 #include "llvm/IR/Attributes.h"
44 #include "llvm/IR/Constants.h"
45 #include "llvm/IR/DebugLoc.h"
46 #include "llvm/IR/Function.h"
47 #include "llvm/IR/GlobalValue.h"
48 #include "llvm/MC/MCAsmInfo.h"
49 #include "llvm/MC/MCInstrDesc.h"
50 #include "llvm/MC/MCInstrItineraries.h"
51 #include "llvm/Support/BranchProbability.h"
52 #include "llvm/Support/Casting.h"
53 #include "llvm/Support/CommandLine.h"
54 #include "llvm/Support/Compiler.h"
55 #include "llvm/Support/Debug.h"
56 #include "llvm/Support/ErrorHandling.h"
57 #include "llvm/Support/raw_ostream.h"
58 #include "llvm/Target/TargetMachine.h"
69 #define DEBUG_TYPE "arm-instrinfo"
71 #define GET_INSTRINFO_CTOR_DTOR
72 #include "ARMGenInstrInfo.inc"
75 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
76 cl::desc("Enable ARM 2-addr to 3-addr conv"));
78 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
80 uint16_t MLxOpc; // MLA / MLS opcode
81 uint16_t MulOpc; // Expanded multiplication opcode
82 uint16_t AddSubOpc; // Expanded add / sub opcode
83 bool NegAcc; // True if the acc is negated before the add / sub.
84 bool HasLane; // True if instruction has an extra "lane" operand.
87 static const ARM_MLxEntry ARM_MLxTable[] = {
88 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
90 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
91 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
92 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
93 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
94 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
96 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
97 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
100 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
101 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
102 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
103 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
104 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
105 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
106 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
107 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
110 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
111 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
113 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
114 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
115 llvm_unreachable("Duplicated entries?");
116 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
117 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
121 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
122 // currently defaults to no prepass hazard recognizer.
123 ScheduleHazardRecognizer *
124 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
125 const ScheduleDAG *DAG) const {
126 if (usePreRAHazardRecognizer()) {
127 const InstrItineraryData *II =
128 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
129 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
131 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
134 ScheduleHazardRecognizer *ARMBaseInstrInfo::
135 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
136 const ScheduleDAG *DAG) const {
137 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
138 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
139 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
142 MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(
143 MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
144 // FIXME: Thumb2 support.
149 MachineFunction &MF = *MI.getParent()->getParent();
150 uint64_t TSFlags = MI.getDesc().TSFlags;
152 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
153 default: return nullptr;
154 case ARMII::IndexModePre:
157 case ARMII::IndexModePost:
161 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
163 unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
167 MachineInstr *UpdateMI = nullptr;
168 MachineInstr *MemMI = nullptr;
169 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
170 const MCInstrDesc &MCID = MI.getDesc();
171 unsigned NumOps = MCID.getNumOperands();
172 bool isLoad = !MI.mayStore();
173 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
174 const MachineOperand &Base = MI.getOperand(2);
175 const MachineOperand &Offset = MI.getOperand(NumOps - 3);
176 unsigned WBReg = WB.getReg();
177 unsigned BaseReg = Base.getReg();
178 unsigned OffReg = Offset.getReg();
179 unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
180 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
182 default: llvm_unreachable("Unknown indexed op!");
183 case ARMII::AddrMode2: {
184 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
185 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
187 if (ARM_AM::getSOImmVal(Amt) == -1)
188 // Can't encode it in a so_imm operand. This transformation will
189 // add more than 1 instruction. Abandon!
191 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
197 } else if (Amt != 0) {
198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
199 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
200 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
201 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
209 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
210 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
217 case ARMII::AddrMode3 : {
218 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
219 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
221 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
222 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
223 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
229 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
230 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
239 std::vector<MachineInstr*> NewMIs;
243 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
248 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
249 .addReg(MI.getOperand(1).getReg())
254 NewMIs.push_back(MemMI);
255 NewMIs.push_back(UpdateMI);
259 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
264 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
265 .addReg(MI.getOperand(1).getReg())
271 UpdateMI->getOperand(0).setIsDead();
272 NewMIs.push_back(UpdateMI);
273 NewMIs.push_back(MemMI);
276 // Transfer LiveVariables states, kill / dead info.
278 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
279 MachineOperand &MO = MI.getOperand(i);
280 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
281 unsigned Reg = MO.getReg();
283 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
285 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
287 LV->addVirtualRegisterDead(Reg, *NewMI);
289 if (MO.isUse() && MO.isKill()) {
290 for (unsigned j = 0; j < 2; ++j) {
291 // Look at the two new MI's in reverse order.
292 MachineInstr *NewMI = NewMIs[j];
293 if (!NewMI->readsRegister(Reg))
295 LV->addVirtualRegisterKilled(Reg, *NewMI);
296 if (VI.removeKill(MI))
297 VI.Kills.push_back(NewMI);
305 MachineBasicBlock::iterator MBBI = MI.getIterator();
306 MFI->insert(MBBI, NewMIs[1]);
307 MFI->insert(MBBI, NewMIs[0]);
312 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
313 MachineBasicBlock *&TBB,
314 MachineBasicBlock *&FBB,
315 SmallVectorImpl<MachineOperand> &Cond,
316 bool AllowModify) const {
320 MachineBasicBlock::iterator I = MBB.end();
321 if (I == MBB.begin())
322 return false; // Empty blocks are easy.
325 // Walk backwards from the end of the basic block until the branch is
326 // analyzed or we give up.
327 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
328 // Flag to be raised on unanalyzeable instructions. This is useful in cases
329 // where we want to clean up on the end of the basic block before we bail
331 bool CantAnalyze = false;
333 // Skip over DEBUG values and predicated nonterminators.
334 while (I->isDebugValue() || !I->isTerminator()) {
335 if (I == MBB.begin())
340 if (isIndirectBranchOpcode(I->getOpcode()) ||
341 isJumpTableBranchOpcode(I->getOpcode())) {
342 // Indirect branches and jump tables can't be analyzed, but we still want
343 // to clean up any instructions at the tail of the basic block.
345 } else if (isUncondBranchOpcode(I->getOpcode())) {
346 TBB = I->getOperand(0).getMBB();
347 } else if (isCondBranchOpcode(I->getOpcode())) {
348 // Bail out if we encounter multiple conditional branches.
352 assert(!FBB && "FBB should have been null.");
354 TBB = I->getOperand(0).getMBB();
355 Cond.push_back(I->getOperand(1));
356 Cond.push_back(I->getOperand(2));
357 } else if (I->isReturn()) {
358 // Returns can't be analyzed, but we should run cleanup.
359 CantAnalyze = !isPredicated(*I);
361 // We encountered other unrecognized terminator. Bail out immediately.
365 // Cleanup code - to be run for unpredicated unconditional branches and
367 if (!isPredicated(*I) &&
368 (isUncondBranchOpcode(I->getOpcode()) ||
369 isIndirectBranchOpcode(I->getOpcode()) ||
370 isJumpTableBranchOpcode(I->getOpcode()) ||
372 // Forget any previous condition branch information - it no longer applies.
376 // If we can modify the function, delete everything below this
377 // unconditional branch.
379 MachineBasicBlock::iterator DI = std::next(I);
380 while (DI != MBB.end()) {
381 MachineInstr &InstToDelete = *DI;
383 InstToDelete.eraseFromParent();
391 if (I == MBB.begin())
397 // We made it past the terminators without bailing out - we must have
398 // analyzed this branch successfully.
402 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
403 int *BytesRemoved) const {
404 assert(!BytesRemoved && "code size not handled");
406 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
410 if (!isUncondBranchOpcode(I->getOpcode()) &&
411 !isCondBranchOpcode(I->getOpcode()))
414 // Remove the branch.
415 I->eraseFromParent();
419 if (I == MBB.begin()) return 1;
421 if (!isCondBranchOpcode(I->getOpcode()))
424 // Remove the branch.
425 I->eraseFromParent();
429 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
430 MachineBasicBlock *TBB,
431 MachineBasicBlock *FBB,
432 ArrayRef<MachineOperand> Cond,
434 int *BytesAdded) const {
435 assert(!BytesAdded && "code size not handled");
436 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
437 int BOpc = !AFI->isThumbFunction()
438 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
439 int BccOpc = !AFI->isThumbFunction()
440 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
441 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
443 // Shouldn't be a fall through.
444 assert(TBB && "insertBranch must not be told to insert a fallthrough");
445 assert((Cond.size() == 2 || Cond.size() == 0) &&
446 "ARM branch conditions have two components!");
448 // For conditional branches, we use addOperand to preserve CPSR flags.
451 if (Cond.empty()) { // Unconditional branch?
453 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
455 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
457 BuildMI(&MBB, DL, get(BccOpc))
459 .addImm(Cond[0].getImm())
464 // Two-way conditional branch.
465 BuildMI(&MBB, DL, get(BccOpc))
467 .addImm(Cond[0].getImm())
470 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
472 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
476 bool ARMBaseInstrInfo::
477 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
478 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
479 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
485 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
486 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
487 while (++I != E && I->isInsideBundle()) {
488 int PIdx = I->findFirstPredOperandIdx();
489 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
495 int PIdx = MI.findFirstPredOperandIdx();
496 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
499 bool ARMBaseInstrInfo::PredicateInstruction(
500 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
501 unsigned Opc = MI.getOpcode();
502 if (isUncondBranchOpcode(Opc)) {
503 MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
504 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
505 .addImm(Pred[0].getImm())
506 .addReg(Pred[1].getReg());
510 int PIdx = MI.findFirstPredOperandIdx();
512 MachineOperand &PMO = MI.getOperand(PIdx);
513 PMO.setImm(Pred[0].getImm());
514 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
520 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
521 ArrayRef<MachineOperand> Pred2) const {
522 if (Pred1.size() > 2 || Pred2.size() > 2)
525 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
526 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
536 return CC2 == ARMCC::HI;
538 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
540 return CC2 == ARMCC::GT;
542 return CC2 == ARMCC::LT;
546 bool ARMBaseInstrInfo::DefinesPredicate(
547 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
549 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
550 const MachineOperand &MO = MI.getOperand(i);
551 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
552 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
561 bool ARMBaseInstrInfo::isCPSRDefined(const MachineInstr &MI) {
562 for (const auto &MO : MI.operands())
563 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
568 bool ARMBaseInstrInfo::isAddrMode3OpImm(const MachineInstr &MI,
570 const MachineOperand &Offset = MI.getOperand(Op + 1);
571 return Offset.getReg() != 0;
574 // Load with negative register offset requires additional 1cyc and +I unit
576 bool ARMBaseInstrInfo::isAddrMode3OpMinusReg(const MachineInstr &MI,
578 const MachineOperand &Offset = MI.getOperand(Op + 1);
579 const MachineOperand &Opc = MI.getOperand(Op + 2);
581 assert(Offset.isReg());
582 int64_t OpcImm = Opc.getImm();
584 bool isSub = ARM_AM::getAM3Op(OpcImm) == ARM_AM::sub;
585 return (isSub && Offset.getReg() != 0);
588 bool ARMBaseInstrInfo::isLdstScaledReg(const MachineInstr &MI,
590 const MachineOperand &Opc = MI.getOperand(Op + 2);
591 unsigned OffImm = Opc.getImm();
592 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
595 // Load, scaled register offset, not plus LSL2
596 bool ARMBaseInstrInfo::isLdstScaledRegNotPlusLsl2(const MachineInstr &MI,
598 const MachineOperand &Opc = MI.getOperand(Op + 2);
599 unsigned OffImm = Opc.getImm();
601 bool isAdd = ARM_AM::getAM2Op(OffImm) == ARM_AM::add;
602 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
603 ARM_AM::ShiftOpc ShiftOpc = ARM_AM::getAM2ShiftOpc(OffImm);
604 if (ShiftOpc == ARM_AM::no_shift) return false; // not scaled
605 bool SimpleScaled = (isAdd && ShiftOpc == ARM_AM::lsl && Amt == 2);
606 return !SimpleScaled;
609 // Minus reg for ldstso addr mode
610 bool ARMBaseInstrInfo::isLdstSoMinusReg(const MachineInstr &MI,
612 unsigned OffImm = MI.getOperand(Op + 2).getImm();
613 return ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
616 // Load, scaled register offset
617 bool ARMBaseInstrInfo::isAm2ScaledReg(const MachineInstr &MI,
619 unsigned OffImm = MI.getOperand(Op + 2).getImm();
620 return ARM_AM::getAM2ShiftOpc(OffImm) != ARM_AM::no_shift;
623 static bool isEligibleForITBlock(const MachineInstr *MI) {
624 switch (MI->getOpcode()) {
625 default: return true;
626 case ARM::tADC: // ADC (register) T1
627 case ARM::tADDi3: // ADD (immediate) T1
628 case ARM::tADDi8: // ADD (immediate) T2
629 case ARM::tADDrr: // ADD (register) T1
630 case ARM::tAND: // AND (register) T1
631 case ARM::tASRri: // ASR (immediate) T1
632 case ARM::tASRrr: // ASR (register) T1
633 case ARM::tBIC: // BIC (register) T1
634 case ARM::tEOR: // EOR (register) T1
635 case ARM::tLSLri: // LSL (immediate) T1
636 case ARM::tLSLrr: // LSL (register) T1
637 case ARM::tLSRri: // LSR (immediate) T1
638 case ARM::tLSRrr: // LSR (register) T1
639 case ARM::tMUL: // MUL T1
640 case ARM::tMVN: // MVN (register) T1
641 case ARM::tORR: // ORR (register) T1
642 case ARM::tROR: // ROR (register) T1
643 case ARM::tRSB: // RSB (immediate) T1
644 case ARM::tSBC: // SBC (register) T1
645 case ARM::tSUBi3: // SUB (immediate) T1
646 case ARM::tSUBi8: // SUB (immediate) T2
647 case ARM::tSUBrr: // SUB (register) T1
648 return !ARMBaseInstrInfo::isCPSRDefined(*MI);
652 /// isPredicable - Return true if the specified instruction can be predicated.
653 /// By default, this returns true for every instruction with a
654 /// PredicateOperand.
655 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
656 if (!MI.isPredicable())
662 if (!isEligibleForITBlock(&MI))
665 const ARMFunctionInfo *AFI =
666 MI.getParent()->getParent()->getInfo<ARMFunctionInfo>();
668 // Neon instructions in Thumb2 IT blocks are deprecated, see ARMARM.
669 // In their ARM encoding, they can't be encoded in a conditional form.
670 if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
673 if (AFI->isThumb2Function()) {
674 if (getSubtarget().restrictIT())
675 return isV8EligibleForIT(&MI);
683 template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
684 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
685 const MachineOperand &MO = MI->getOperand(i);
686 if (!MO.isReg() || MO.isUndef() || MO.isUse())
688 if (MO.getReg() != ARM::CPSR)
693 // all definitions of CPSR are dead
697 } // end namespace llvm
699 /// GetInstSize - Return the size of the specified MachineInstr.
701 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
702 const MachineBasicBlock &MBB = *MI.getParent();
703 const MachineFunction *MF = MBB.getParent();
704 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
706 const MCInstrDesc &MCID = MI.getDesc();
708 return MCID.getSize();
710 // If this machine instr is an inline asm, measure it.
711 if (MI.getOpcode() == ARM::INLINEASM)
712 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
713 unsigned Opc = MI.getOpcode();
716 // pseudo-instruction sizes are zero.
718 case TargetOpcode::BUNDLE:
719 return getInstBundleLength(MI);
720 case ARM::MOVi16_ga_pcrel:
721 case ARM::MOVTi16_ga_pcrel:
722 case ARM::t2MOVi16_ga_pcrel:
723 case ARM::t2MOVTi16_ga_pcrel:
726 case ARM::t2MOVi32imm:
728 case ARM::CONSTPOOL_ENTRY:
729 case ARM::JUMPTABLE_INSTS:
730 case ARM::JUMPTABLE_ADDRS:
731 case ARM::JUMPTABLE_TBB:
732 case ARM::JUMPTABLE_TBH:
733 // If this machine instr is a constant pool entry, its size is recorded as
735 return MI.getOperand(2).getImm();
736 case ARM::Int_eh_sjlj_longjmp:
738 case ARM::tInt_eh_sjlj_longjmp:
740 case ARM::tInt_WIN_eh_sjlj_longjmp:
742 case ARM::Int_eh_sjlj_setjmp:
743 case ARM::Int_eh_sjlj_setjmp_nofp:
745 case ARM::tInt_eh_sjlj_setjmp:
746 case ARM::t2Int_eh_sjlj_setjmp:
747 case ARM::t2Int_eh_sjlj_setjmp_nofp:
750 return MI.getOperand(1).getImm();
754 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
756 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
757 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
758 while (++I != E && I->isInsideBundle()) {
759 assert(!I->isBundle() && "No nested bundle!");
760 Size += getInstSizeInBytes(*I);
765 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
766 MachineBasicBlock::iterator I,
767 unsigned DestReg, bool KillSrc,
768 const ARMSubtarget &Subtarget) const {
769 unsigned Opc = Subtarget.isThumb()
770 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
773 MachineInstrBuilder MIB =
774 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
776 // There is only 1 A/R class MRS instruction, and it always refers to
777 // APSR. However, there are lots of other possibilities on M-class cores.
778 if (Subtarget.isMClass())
781 MIB.add(predOps(ARMCC::AL))
782 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
785 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
786 MachineBasicBlock::iterator I,
787 unsigned SrcReg, bool KillSrc,
788 const ARMSubtarget &Subtarget) const {
789 unsigned Opc = Subtarget.isThumb()
790 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
793 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
795 if (Subtarget.isMClass())
800 MIB.addReg(SrcReg, getKillRegState(KillSrc))
801 .add(predOps(ARMCC::AL))
802 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
805 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
806 MachineBasicBlock::iterator I,
807 const DebugLoc &DL, unsigned DestReg,
808 unsigned SrcReg, bool KillSrc) const {
809 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
810 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
812 if (GPRDest && GPRSrc) {
813 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
814 .addReg(SrcReg, getKillRegState(KillSrc))
815 .add(predOps(ARMCC::AL))
820 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
821 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
824 if (SPRDest && SPRSrc)
826 else if (GPRDest && SPRSrc)
828 else if (SPRDest && GPRSrc)
830 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
832 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
836 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
837 MIB.addReg(SrcReg, getKillRegState(KillSrc));
838 if (Opc == ARM::VORRq)
839 MIB.addReg(SrcReg, getKillRegState(KillSrc));
840 MIB.add(predOps(ARMCC::AL));
844 // Handle register classes that require multiple instructions.
845 unsigned BeginIdx = 0;
846 unsigned SubRegs = 0;
849 // Use VORRq when possible.
850 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
852 BeginIdx = ARM::qsub_0;
854 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
856 BeginIdx = ARM::qsub_0;
858 // Fall back to VMOVD.
859 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
861 BeginIdx = ARM::dsub_0;
863 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
865 BeginIdx = ARM::dsub_0;
867 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
869 BeginIdx = ARM::dsub_0;
871 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
872 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
873 BeginIdx = ARM::gsub_0;
875 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
877 BeginIdx = ARM::dsub_0;
880 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
882 BeginIdx = ARM::dsub_0;
885 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
887 BeginIdx = ARM::dsub_0;
890 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
892 BeginIdx = ARM::ssub_0;
894 } else if (SrcReg == ARM::CPSR) {
895 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
897 } else if (DestReg == ARM::CPSR) {
898 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
902 assert(Opc && "Impossible reg-to-reg copy");
904 const TargetRegisterInfo *TRI = &getRegisterInfo();
905 MachineInstrBuilder Mov;
907 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
908 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
909 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
913 SmallSet<unsigned, 4> DstRegs;
915 for (unsigned i = 0; i != SubRegs; ++i) {
916 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
917 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
918 assert(Dst && Src && "Bad sub-register");
920 assert(!DstRegs.count(Src) && "destructive vector copy");
923 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
924 // VORR takes two source operands.
925 if (Opc == ARM::VORRq)
927 Mov = Mov.add(predOps(ARMCC::AL));
929 if (Opc == ARM::MOVr)
930 Mov = Mov.add(condCodeOp());
932 // Add implicit super-register defs and kills to the last instruction.
933 Mov->addRegisterDefined(DestReg, TRI);
935 Mov->addRegisterKilled(SrcReg, TRI);
938 const MachineInstrBuilder &
939 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
940 unsigned SubIdx, unsigned State,
941 const TargetRegisterInfo *TRI) const {
943 return MIB.addReg(Reg, State);
945 if (TargetRegisterInfo::isPhysicalRegister(Reg))
946 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
947 return MIB.addReg(Reg, State, SubIdx);
950 void ARMBaseInstrInfo::
951 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
952 unsigned SrcReg, bool isKill, int FI,
953 const TargetRegisterClass *RC,
954 const TargetRegisterInfo *TRI) const {
956 if (I != MBB.end()) DL = I->getDebugLoc();
957 MachineFunction &MF = *MBB.getParent();
958 MachineFrameInfo &MFI = MF.getFrameInfo();
959 unsigned Align = MFI.getObjectAlignment(FI);
961 MachineMemOperand *MMO = MF.getMachineMemOperand(
962 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
963 MFI.getObjectSize(FI), Align);
965 switch (TRI->getSpillSize(*RC)) {
967 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
968 BuildMI(MBB, I, DL, get(ARM::STRi12))
969 .addReg(SrcReg, getKillRegState(isKill))
973 .add(predOps(ARMCC::AL));
974 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
975 BuildMI(MBB, I, DL, get(ARM::VSTRS))
976 .addReg(SrcReg, getKillRegState(isKill))
980 .add(predOps(ARMCC::AL));
982 llvm_unreachable("Unknown reg class!");
985 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
986 BuildMI(MBB, I, DL, get(ARM::VSTRD))
987 .addReg(SrcReg, getKillRegState(isKill))
991 .add(predOps(ARMCC::AL));
992 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
993 if (Subtarget.hasV5TEOps()) {
994 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
995 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
996 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
997 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
998 .add(predOps(ARMCC::AL));
1000 // Fallback to STM instruction, which has existed since the dawn of
1002 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STMIA))
1005 .add(predOps(ARMCC::AL));
1006 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
1007 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
1010 llvm_unreachable("Unknown reg class!");
1013 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1014 // Use aligned spills if the stack can be realigned.
1015 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1016 BuildMI(MBB, I, DL, get(ARM::VST1q64))
1019 .addReg(SrcReg, getKillRegState(isKill))
1021 .add(predOps(ARMCC::AL));
1023 BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
1024 .addReg(SrcReg, getKillRegState(isKill))
1027 .add(predOps(ARMCC::AL));
1030 llvm_unreachable("Unknown reg class!");
1033 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1034 // Use aligned spills if the stack can be realigned.
1035 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1036 BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
1039 .addReg(SrcReg, getKillRegState(isKill))
1041 .add(predOps(ARMCC::AL));
1043 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
1045 .add(predOps(ARMCC::AL))
1046 .addMemOperand(MMO);
1047 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1048 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1049 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1052 llvm_unreachable("Unknown reg class!");
1055 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1056 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1057 // FIXME: It's possible to only store part of the QQ register if the
1058 // spilled def has a sub-register index.
1059 BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
1062 .addReg(SrcReg, getKillRegState(isKill))
1064 .add(predOps(ARMCC::AL));
1066 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
1068 .add(predOps(ARMCC::AL))
1069 .addMemOperand(MMO);
1070 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1071 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1072 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1073 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1076 llvm_unreachable("Unknown reg class!");
1079 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1080 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
1082 .add(predOps(ARMCC::AL))
1083 .addMemOperand(MMO);
1084 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1085 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1086 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1087 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1088 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1089 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1090 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1091 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1093 llvm_unreachable("Unknown reg class!");
1096 llvm_unreachable("Unknown reg class!");
1100 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1101 int &FrameIndex) const {
1102 switch (MI.getOpcode()) {
1105 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1106 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1107 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1108 MI.getOperand(3).getImm() == 0) {
1109 FrameIndex = MI.getOperand(1).getIndex();
1110 return MI.getOperand(0).getReg();
1118 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1119 MI.getOperand(2).getImm() == 0) {
1120 FrameIndex = MI.getOperand(1).getIndex();
1121 return MI.getOperand(0).getReg();
1125 case ARM::VST1d64TPseudo:
1126 case ARM::VST1d64QPseudo:
1127 if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1128 FrameIndex = MI.getOperand(0).getIndex();
1129 return MI.getOperand(2).getReg();
1133 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1134 FrameIndex = MI.getOperand(1).getIndex();
1135 return MI.getOperand(0).getReg();
1143 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1144 int &FrameIndex) const {
1145 const MachineMemOperand *Dummy;
1146 return MI.mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1149 void ARMBaseInstrInfo::
1150 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1151 unsigned DestReg, int FI,
1152 const TargetRegisterClass *RC,
1153 const TargetRegisterInfo *TRI) const {
1155 if (I != MBB.end()) DL = I->getDebugLoc();
1156 MachineFunction &MF = *MBB.getParent();
1157 MachineFrameInfo &MFI = MF.getFrameInfo();
1158 unsigned Align = MFI.getObjectAlignment(FI);
1159 MachineMemOperand *MMO = MF.getMachineMemOperand(
1160 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
1161 MFI.getObjectSize(FI), Align);
1163 switch (TRI->getSpillSize(*RC)) {
1165 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1166 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1170 .add(predOps(ARMCC::AL));
1172 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1173 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1177 .add(predOps(ARMCC::AL));
1179 llvm_unreachable("Unknown reg class!");
1182 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1183 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1187 .add(predOps(ARMCC::AL));
1188 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1189 MachineInstrBuilder MIB;
1191 if (Subtarget.hasV5TEOps()) {
1192 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1193 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1194 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1195 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1196 .add(predOps(ARMCC::AL));
1198 // Fallback to LDM instruction, which has existed since the dawn of
1200 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1203 .add(predOps(ARMCC::AL));
1204 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1205 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1208 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1209 MIB.addReg(DestReg, RegState::ImplicitDefine);
1211 llvm_unreachable("Unknown reg class!");
1214 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1215 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1216 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1220 .add(predOps(ARMCC::AL));
1222 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1225 .add(predOps(ARMCC::AL));
1228 llvm_unreachable("Unknown reg class!");
1231 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1232 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1233 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1237 .add(predOps(ARMCC::AL));
1239 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1242 .add(predOps(ARMCC::AL));
1243 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1244 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1245 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1246 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1247 MIB.addReg(DestReg, RegState::ImplicitDefine);
1250 llvm_unreachable("Unknown reg class!");
1253 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1254 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1255 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1259 .add(predOps(ARMCC::AL));
1261 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1263 .add(predOps(ARMCC::AL))
1264 .addMemOperand(MMO);
1265 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1266 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1267 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1268 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1269 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1270 MIB.addReg(DestReg, RegState::ImplicitDefine);
1273 llvm_unreachable("Unknown reg class!");
1276 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1277 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1279 .add(predOps(ARMCC::AL))
1280 .addMemOperand(MMO);
1281 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1282 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1283 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1284 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1285 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1286 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1287 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1288 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1289 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1290 MIB.addReg(DestReg, RegState::ImplicitDefine);
1292 llvm_unreachable("Unknown reg class!");
1295 llvm_unreachable("Unknown regclass!");
1299 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1300 int &FrameIndex) const {
1301 switch (MI.getOpcode()) {
1304 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1305 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1306 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1307 MI.getOperand(3).getImm() == 0) {
1308 FrameIndex = MI.getOperand(1).getIndex();
1309 return MI.getOperand(0).getReg();
1317 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1318 MI.getOperand(2).getImm() == 0) {
1319 FrameIndex = MI.getOperand(1).getIndex();
1320 return MI.getOperand(0).getReg();
1324 case ARM::VLD1d64TPseudo:
1325 case ARM::VLD1d64QPseudo:
1326 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1327 FrameIndex = MI.getOperand(1).getIndex();
1328 return MI.getOperand(0).getReg();
1332 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1333 FrameIndex = MI.getOperand(1).getIndex();
1334 return MI.getOperand(0).getReg();
1342 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1343 int &FrameIndex) const {
1344 const MachineMemOperand *Dummy;
1345 return MI.mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1348 /// \brief Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1349 /// depending on whether the result is used.
1350 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1351 bool isThumb1 = Subtarget.isThumb1Only();
1352 bool isThumb2 = Subtarget.isThumb2();
1353 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1355 DebugLoc dl = MI->getDebugLoc();
1356 MachineBasicBlock *BB = MI->getParent();
1358 MachineInstrBuilder LDM, STM;
1359 if (isThumb1 || !MI->getOperand(1).isDead()) {
1360 MachineOperand LDWb(MI->getOperand(1));
1361 LDWb.setIsRenamable(false);
1362 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1363 : isThumb1 ? ARM::tLDMIA_UPD
1367 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1370 if (isThumb1 || !MI->getOperand(0).isDead()) {
1371 MachineOperand STWb(MI->getOperand(0));
1372 STWb.setIsRenamable(false);
1373 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1374 : isThumb1 ? ARM::tSTMIA_UPD
1378 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1381 MachineOperand LDBase(MI->getOperand(3));
1382 LDBase.setIsRenamable(false);
1383 LDM.add(LDBase).add(predOps(ARMCC::AL));
1385 MachineOperand STBase(MI->getOperand(2));
1386 STBase.setIsRenamable(false);
1387 STM.add(STBase).add(predOps(ARMCC::AL));
1389 // Sort the scratch registers into ascending order.
1390 const TargetRegisterInfo &TRI = getRegisterInfo();
1391 SmallVector<unsigned, 6> ScratchRegs;
1392 for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1393 ScratchRegs.push_back(MI->getOperand(I).getReg());
1394 std::sort(ScratchRegs.begin(), ScratchRegs.end(),
1395 [&TRI](const unsigned &Reg1,
1396 const unsigned &Reg2) -> bool {
1397 return TRI.getEncodingValue(Reg1) <
1398 TRI.getEncodingValue(Reg2);
1401 for (const auto &Reg : ScratchRegs) {
1402 LDM.addReg(Reg, RegState::Define);
1403 STM.addReg(Reg, RegState::Kill);
1409 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1410 if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1411 assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1412 "LOAD_STACK_GUARD currently supported only for MachO.");
1413 expandLoadStackGuard(MI);
1414 MI.getParent()->erase(MI);
1418 if (MI.getOpcode() == ARM::MEMCPY) {
1423 // This hook gets to expand COPY instructions before they become
1424 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1425 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1426 // changed into a VORR that can go down the NEON pipeline.
1427 if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || Subtarget.isFPOnlySP())
1430 // Look for a copy between even S-registers. That is where we keep floats
1431 // when using NEON v2f32 instructions for f32 arithmetic.
1432 unsigned DstRegS = MI.getOperand(0).getReg();
1433 unsigned SrcRegS = MI.getOperand(1).getReg();
1434 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1437 const TargetRegisterInfo *TRI = &getRegisterInfo();
1438 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1440 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1442 if (!DstRegD || !SrcRegD)
1445 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1446 // legal if the COPY already defines the full DstRegD, and it isn't a
1447 // sub-register insertion.
1448 if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
1451 // A dead copy shouldn't show up here, but reject it just in case.
1452 if (MI.getOperand(0).isDead())
1455 // All clear, widen the COPY.
1456 DEBUG(dbgs() << "widening: " << MI);
1457 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1459 // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg
1460 // or some other super-register.
1461 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
1462 if (ImpDefIdx != -1)
1463 MI.RemoveOperand(ImpDefIdx);
1465 // Change the opcode and operands.
1466 MI.setDesc(get(ARM::VMOVD));
1467 MI.getOperand(0).setReg(DstRegD);
1468 MI.getOperand(1).setReg(SrcRegD);
1469 MIB.add(predOps(ARMCC::AL));
1471 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1472 // register scavenger and machine verifier, so we need to indicate that we
1473 // are reading an undefined value from SrcRegD, but a proper value from
1475 MI.getOperand(1).setIsUndef();
1476 MIB.addReg(SrcRegS, RegState::Implicit);
1478 // SrcRegD may actually contain an unrelated value in the ssub_1
1479 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1480 if (MI.getOperand(1).isKill()) {
1481 MI.getOperand(1).setIsKill(false);
1482 MI.addRegisterKilled(SrcRegS, TRI, true);
1485 DEBUG(dbgs() << "replaced by: " << MI);
1489 /// Create a copy of a const pool value. Update CPI to the new index and return
1491 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1492 MachineConstantPool *MCP = MF.getConstantPool();
1493 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1495 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1496 assert(MCPE.isMachineConstantPoolEntry() &&
1497 "Expecting a machine constantpool entry!");
1498 ARMConstantPoolValue *ACPV =
1499 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1501 unsigned PCLabelId = AFI->createPICLabelUId();
1502 ARMConstantPoolValue *NewCPV = nullptr;
1504 // FIXME: The below assumes PIC relocation model and that the function
1505 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1506 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1507 // instructions, so that's probably OK, but is PIC always correct when
1509 if (ACPV->isGlobalValue())
1510 NewCPV = ARMConstantPoolConstant::Create(
1511 cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1512 4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1513 else if (ACPV->isExtSymbol())
1514 NewCPV = ARMConstantPoolSymbol::
1515 Create(MF.getFunction().getContext(),
1516 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1517 else if (ACPV->isBlockAddress())
1518 NewCPV = ARMConstantPoolConstant::
1519 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1520 ARMCP::CPBlockAddress, 4);
1521 else if (ACPV->isLSDA())
1522 NewCPV = ARMConstantPoolConstant::Create(&MF.getFunction(), PCLabelId,
1524 else if (ACPV->isMachineBasicBlock())
1525 NewCPV = ARMConstantPoolMBB::
1526 Create(MF.getFunction().getContext(),
1527 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1529 llvm_unreachable("Unexpected ARM constantpool value type!!");
1530 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1534 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
1535 MachineBasicBlock::iterator I,
1536 unsigned DestReg, unsigned SubIdx,
1537 const MachineInstr &Orig,
1538 const TargetRegisterInfo &TRI) const {
1539 unsigned Opcode = Orig.getOpcode();
1542 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1543 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1547 case ARM::tLDRpci_pic:
1548 case ARM::t2LDRpci_pic: {
1549 MachineFunction &MF = *MBB.getParent();
1550 unsigned CPI = Orig.getOperand(1).getIndex();
1551 unsigned PCLabelId = duplicateCPV(MF, CPI);
1552 MachineInstrBuilder MIB =
1553 BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
1554 .addConstantPoolIndex(CPI)
1556 MIB->setMemRefs(Orig.memoperands_begin(), Orig.memoperands_end());
1563 ARMBaseInstrInfo::duplicate(MachineBasicBlock &MBB,
1564 MachineBasicBlock::iterator InsertBefore,
1565 const MachineInstr &Orig) const {
1566 MachineInstr &Cloned = TargetInstrInfo::duplicate(MBB, InsertBefore, Orig);
1567 MachineBasicBlock::instr_iterator I = Cloned.getIterator();
1569 switch (I->getOpcode()) {
1570 case ARM::tLDRpci_pic:
1571 case ARM::t2LDRpci_pic: {
1572 MachineFunction &MF = *MBB.getParent();
1573 unsigned CPI = I->getOperand(1).getIndex();
1574 unsigned PCLabelId = duplicateCPV(MF, CPI);
1575 I->getOperand(1).setIndex(CPI);
1576 I->getOperand(2).setImm(PCLabelId);
1580 if (!I->isBundledWithSucc())
1587 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
1588 const MachineInstr &MI1,
1589 const MachineRegisterInfo *MRI) const {
1590 unsigned Opcode = MI0.getOpcode();
1591 if (Opcode == ARM::t2LDRpci ||
1592 Opcode == ARM::t2LDRpci_pic ||
1593 Opcode == ARM::tLDRpci ||
1594 Opcode == ARM::tLDRpci_pic ||
1595 Opcode == ARM::LDRLIT_ga_pcrel ||
1596 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1597 Opcode == ARM::tLDRLIT_ga_pcrel ||
1598 Opcode == ARM::MOV_ga_pcrel ||
1599 Opcode == ARM::MOV_ga_pcrel_ldr ||
1600 Opcode == ARM::t2MOV_ga_pcrel) {
1601 if (MI1.getOpcode() != Opcode)
1603 if (MI0.getNumOperands() != MI1.getNumOperands())
1606 const MachineOperand &MO0 = MI0.getOperand(1);
1607 const MachineOperand &MO1 = MI1.getOperand(1);
1608 if (MO0.getOffset() != MO1.getOffset())
1611 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1612 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1613 Opcode == ARM::tLDRLIT_ga_pcrel ||
1614 Opcode == ARM::MOV_ga_pcrel ||
1615 Opcode == ARM::MOV_ga_pcrel_ldr ||
1616 Opcode == ARM::t2MOV_ga_pcrel)
1617 // Ignore the PC labels.
1618 return MO0.getGlobal() == MO1.getGlobal();
1620 const MachineFunction *MF = MI0.getParent()->getParent();
1621 const MachineConstantPool *MCP = MF->getConstantPool();
1622 int CPI0 = MO0.getIndex();
1623 int CPI1 = MO1.getIndex();
1624 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1625 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1626 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1627 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1628 if (isARMCP0 && isARMCP1) {
1629 ARMConstantPoolValue *ACPV0 =
1630 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1631 ARMConstantPoolValue *ACPV1 =
1632 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1633 return ACPV0->hasSameValue(ACPV1);
1634 } else if (!isARMCP0 && !isARMCP1) {
1635 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1638 } else if (Opcode == ARM::PICLDR) {
1639 if (MI1.getOpcode() != Opcode)
1641 if (MI0.getNumOperands() != MI1.getNumOperands())
1644 unsigned Addr0 = MI0.getOperand(1).getReg();
1645 unsigned Addr1 = MI1.getOperand(1).getReg();
1646 if (Addr0 != Addr1) {
1648 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1649 !TargetRegisterInfo::isVirtualRegister(Addr1))
1652 // This assumes SSA form.
1653 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1654 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1655 // Check if the loaded value, e.g. a constantpool of a global address, are
1657 if (!produceSameValue(*Def0, *Def1, MRI))
1661 for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
1662 // %12 = PICLDR %11, 0, pred:14, pred:%noreg
1663 const MachineOperand &MO0 = MI0.getOperand(i);
1664 const MachineOperand &MO1 = MI1.getOperand(i);
1665 if (!MO0.isIdenticalTo(MO1))
1671 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1674 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1675 /// determine if two loads are loading from the same base address. It should
1676 /// only return true if the base pointers are the same and the only differences
1677 /// between the two addresses is the offset. It also returns the offsets by
1680 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1681 /// is permanently disabled.
1682 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1684 int64_t &Offset2) const {
1685 // Don't worry about Thumb: just ARM and Thumb2.
1686 if (Subtarget.isThumb1Only()) return false;
1688 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1691 switch (Load1->getMachineOpcode()) {
1705 case ARM::t2LDRSHi8:
1707 case ARM::t2LDRBi12:
1708 case ARM::t2LDRSHi12:
1712 switch (Load2->getMachineOpcode()) {
1725 case ARM::t2LDRSHi8:
1727 case ARM::t2LDRBi12:
1728 case ARM::t2LDRSHi12:
1732 // Check if base addresses and chain operands match.
1733 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1734 Load1->getOperand(4) != Load2->getOperand(4))
1737 // Index should be Reg0.
1738 if (Load1->getOperand(3) != Load2->getOperand(3))
1741 // Determine the offsets.
1742 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1743 isa<ConstantSDNode>(Load2->getOperand(1))) {
1744 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1745 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1752 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1753 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1754 /// be scheduled togther. On some targets if two loads are loading from
1755 /// addresses in the same cache line, it's better if they are scheduled
1756 /// together. This function takes two integers that represent the load offsets
1757 /// from the common base address. It returns true if it decides it's desirable
1758 /// to schedule the two loads together. "NumLoads" is the number of loads that
1759 /// have already been scheduled after Load1.
1761 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1762 /// is permanently disabled.
1763 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1764 int64_t Offset1, int64_t Offset2,
1765 unsigned NumLoads) const {
1766 // Don't worry about Thumb: just ARM and Thumb2.
1767 if (Subtarget.isThumb1Only()) return false;
1769 assert(Offset2 > Offset1);
1771 if ((Offset2 - Offset1) / 8 > 64)
1774 // Check if the machine opcodes are different. If they are different
1775 // then we consider them to not be of the same base address,
1776 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1777 // In this case, they are considered to be the same because they are different
1778 // encoding forms of the same basic instruction.
1779 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1780 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1781 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1782 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1783 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1784 return false; // FIXME: overly conservative?
1786 // Four loads in a row should be sufficient.
1793 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1794 const MachineBasicBlock *MBB,
1795 const MachineFunction &MF) const {
1796 // Debug info is never a scheduling boundary. It's necessary to be explicit
1797 // due to the special treatment of IT instructions below, otherwise a
1798 // dbg_value followed by an IT will result in the IT instruction being
1799 // considered a scheduling hazard, which is wrong. It should be the actual
1800 // instruction preceding the dbg_value instruction(s), just like it is
1801 // when debug info is not present.
1802 if (MI.isDebugValue())
1805 // Terminators and labels can't be scheduled around.
1806 if (MI.isTerminator() || MI.isPosition())
1809 // Treat the start of the IT block as a scheduling boundary, but schedule
1810 // t2IT along with all instructions following it.
1811 // FIXME: This is a big hammer. But the alternative is to add all potential
1812 // true and anti dependencies to IT block instructions as implicit operands
1813 // to the t2IT instruction. The added compile time and complexity does not
1815 MachineBasicBlock::const_iterator I = MI;
1816 // Make sure to skip any dbg_value instructions
1817 while (++I != MBB->end() && I->isDebugValue())
1819 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1822 // Don't attempt to schedule around any instruction that defines
1823 // a stack-oriented pointer, as it's unlikely to be profitable. This
1824 // saves compile time, because it doesn't require every single
1825 // stack slot reference to depend on the instruction that does the
1827 // Calls don't actually change the stack pointer, even if they have imp-defs.
1828 // No ARM calling conventions change the stack pointer. (X86 calling
1829 // conventions sometimes do).
1830 if (!MI.isCall() && MI.definesRegister(ARM::SP))
1836 bool ARMBaseInstrInfo::
1837 isProfitableToIfCvt(MachineBasicBlock &MBB,
1838 unsigned NumCycles, unsigned ExtraPredCycles,
1839 BranchProbability Probability) const {
1843 // If we are optimizing for size, see if the branch in the predecessor can be
1844 // lowered to cbn?z by the constant island lowering pass, and return false if
1845 // so. This results in a shorter instruction sequence.
1846 if (MBB.getParent()->getFunction().optForSize()) {
1847 MachineBasicBlock *Pred = *MBB.pred_begin();
1848 if (!Pred->empty()) {
1849 MachineInstr *LastMI = &*Pred->rbegin();
1850 if (LastMI->getOpcode() == ARM::t2Bcc) {
1851 MachineBasicBlock::iterator CmpMI = LastMI;
1852 if (CmpMI != Pred->begin()) {
1854 if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1855 CmpMI->getOpcode() == ARM::t2CMPri) {
1856 unsigned Reg = CmpMI->getOperand(0).getReg();
1857 unsigned PredReg = 0;
1858 ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg);
1859 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1860 isARMLowRegister(Reg))
1867 return isProfitableToIfCvt(MBB, NumCycles, ExtraPredCycles,
1868 MBB, 0, 0, Probability);
1871 bool ARMBaseInstrInfo::
1872 isProfitableToIfCvt(MachineBasicBlock &TBB,
1873 unsigned TCycles, unsigned TExtra,
1874 MachineBasicBlock &FBB,
1875 unsigned FCycles, unsigned FExtra,
1876 BranchProbability Probability) const {
1880 // Attempt to estimate the relative costs of predication versus branching.
1881 // Here we scale up each component of UnpredCost to avoid precision issue when
1882 // scaling TCycles/FCycles by Probability.
1883 const unsigned ScalingUpFactor = 1024;
1885 unsigned PredCost = (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor;
1886 unsigned UnpredCost;
1887 if (!Subtarget.hasBranchPredictor()) {
1888 // When we don't have a branch predictor it's always cheaper to not take a
1889 // branch than take it, so we have to take that into account.
1890 unsigned NotTakenBranchCost = 1;
1891 unsigned TakenBranchCost = Subtarget.getMispredictionPenalty();
1892 unsigned TUnpredCycles, FUnpredCycles;
1894 // Triangle: TBB is the fallthrough
1895 TUnpredCycles = TCycles + NotTakenBranchCost;
1896 FUnpredCycles = TakenBranchCost;
1898 // Diamond: TBB is the block that is branched to, FBB is the fallthrough
1899 TUnpredCycles = TCycles + TakenBranchCost;
1900 FUnpredCycles = FCycles + NotTakenBranchCost;
1901 // The branch at the end of FBB will disappear when it's predicated, so
1902 // discount it from PredCost.
1903 PredCost -= 1 * ScalingUpFactor;
1905 // The total cost is the cost of each path scaled by their probabilites
1906 unsigned TUnpredCost = Probability.scale(TUnpredCycles * ScalingUpFactor);
1907 unsigned FUnpredCost = Probability.getCompl().scale(FUnpredCycles * ScalingUpFactor);
1908 UnpredCost = TUnpredCost + FUnpredCost;
1909 // When predicating assume that the first IT can be folded away but later
1910 // ones cost one cycle each
1911 if (Subtarget.isThumb2() && TCycles + FCycles > 4) {
1912 PredCost += ((TCycles + FCycles - 4) / 4) * ScalingUpFactor;
1915 unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
1916 unsigned FUnpredCost =
1917 Probability.getCompl().scale(FCycles * ScalingUpFactor);
1918 UnpredCost = TUnpredCost + FUnpredCost;
1919 UnpredCost += 1 * ScalingUpFactor; // The branch itself
1920 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1923 return PredCost <= UnpredCost;
1927 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1928 MachineBasicBlock &FMBB) const {
1929 // Reduce false anti-dependencies to let the target's out-of-order execution
1930 // engine do its thing.
1931 return Subtarget.isProfitableToUnpredicate();
1934 /// getInstrPredicate - If instruction is predicated, returns its predicate
1935 /// condition, otherwise returns AL. It also returns the condition code
1936 /// register by reference.
1937 ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI,
1938 unsigned &PredReg) {
1939 int PIdx = MI.findFirstPredOperandIdx();
1945 PredReg = MI.getOperand(PIdx+1).getReg();
1946 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1949 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1954 if (Opc == ARM::t2B)
1957 llvm_unreachable("Unknown unconditional branch opcode!");
1960 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,
1963 unsigned OpIdx2) const {
1964 switch (MI.getOpcode()) {
1966 case ARM::t2MOVCCr: {
1967 // MOVCC can be commuted by inverting the condition.
1968 unsigned PredReg = 0;
1969 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1970 // MOVCC AL can't be inverted. Shouldn't happen.
1971 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1973 MachineInstr *CommutedMI =
1974 TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1977 // After swapping the MOVCC operands, also invert the condition.
1978 CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
1979 .setImm(ARMCC::getOppositeCondition(CC));
1983 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1986 /// Identify instructions that can be folded into a MOVCC instruction, and
1987 /// return the defining instruction.
1988 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1989 const MachineRegisterInfo &MRI,
1990 const TargetInstrInfo *TII) {
1991 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1993 if (!MRI.hasOneNonDBGUse(Reg))
1995 MachineInstr *MI = MRI.getVRegDef(Reg);
1998 // MI is folded into the MOVCC by predicating it.
1999 if (!MI->isPredicable())
2001 // Check if MI has any non-dead defs or physreg uses. This also detects
2002 // predicated instructions which will be reading CPSR.
2003 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
2004 const MachineOperand &MO = MI->getOperand(i);
2005 // Reject frame index operands, PEI can't handle the predicated pseudos.
2006 if (MO.isFI() || MO.isCPI() || MO.isJTI())
2010 // MI can't have any tied operands, that would conflict with predication.
2013 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
2015 if (MO.isDef() && !MO.isDead())
2018 bool DontMoveAcrossStores = true;
2019 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
2024 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,
2025 SmallVectorImpl<MachineOperand> &Cond,
2026 unsigned &TrueOp, unsigned &FalseOp,
2027 bool &Optimizable) const {
2028 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2029 "Unknown select instruction");
2034 // 3: Condition code.
2038 Cond.push_back(MI.getOperand(3));
2039 Cond.push_back(MI.getOperand(4));
2040 // We can always fold a def.
2046 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
2047 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
2048 bool PreferFalse) const {
2049 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
2050 "Unknown select instruction");
2051 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
2052 MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
2053 bool Invert = !DefMI;
2055 DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
2059 // Find new register class to use.
2060 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
2061 unsigned DestReg = MI.getOperand(0).getReg();
2062 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
2063 if (!MRI.constrainRegClass(DestReg, PreviousClass))
2066 // Create a new predicated version of DefMI.
2067 // Rfalse is the first use.
2068 MachineInstrBuilder NewMI =
2069 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
2071 // Copy all the DefMI operands, excluding its (null) predicate.
2072 const MCInstrDesc &DefDesc = DefMI->getDesc();
2073 for (unsigned i = 1, e = DefDesc.getNumOperands();
2074 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
2075 NewMI.add(DefMI->getOperand(i));
2077 unsigned CondCode = MI.getOperand(3).getImm();
2079 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
2081 NewMI.addImm(CondCode);
2082 NewMI.add(MI.getOperand(4));
2084 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
2085 if (NewMI->hasOptionalDef())
2086 NewMI.add(condCodeOp());
2088 // The output register value when the predicate is false is an implicit
2089 // register operand tied to the first def.
2090 // The tie makes the register allocator ensure the FalseReg is allocated the
2091 // same register as operand 0.
2092 FalseReg.setImplicit();
2093 NewMI.add(FalseReg);
2094 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
2096 // Update SeenMIs set: register newly created MI and erase removed DefMI.
2097 SeenMIs.insert(NewMI);
2098 SeenMIs.erase(DefMI);
2100 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
2101 // DefMI would be invalid when tranferred inside the loop. Checking for a
2102 // loop is expensive, but at least remove kill flags if they are in different
2104 if (DefMI->getParent() != MI.getParent())
2105 NewMI->clearKillInfo();
2107 // The caller will erase MI, but not DefMI.
2108 DefMI->eraseFromParent();
2112 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
2113 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
2116 /// This will go away once we can teach tblgen how to set the optional CPSR def
2118 struct AddSubFlagsOpcodePair {
2120 uint16_t MachineOpc;
2123 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
2124 {ARM::ADDSri, ARM::ADDri},
2125 {ARM::ADDSrr, ARM::ADDrr},
2126 {ARM::ADDSrsi, ARM::ADDrsi},
2127 {ARM::ADDSrsr, ARM::ADDrsr},
2129 {ARM::SUBSri, ARM::SUBri},
2130 {ARM::SUBSrr, ARM::SUBrr},
2131 {ARM::SUBSrsi, ARM::SUBrsi},
2132 {ARM::SUBSrsr, ARM::SUBrsr},
2134 {ARM::RSBSri, ARM::RSBri},
2135 {ARM::RSBSrsi, ARM::RSBrsi},
2136 {ARM::RSBSrsr, ARM::RSBrsr},
2138 {ARM::tADDSi3, ARM::tADDi3},
2139 {ARM::tADDSi8, ARM::tADDi8},
2140 {ARM::tADDSrr, ARM::tADDrr},
2141 {ARM::tADCS, ARM::tADC},
2143 {ARM::tSUBSi3, ARM::tSUBi3},
2144 {ARM::tSUBSi8, ARM::tSUBi8},
2145 {ARM::tSUBSrr, ARM::tSUBrr},
2146 {ARM::tSBCS, ARM::tSBC},
2148 {ARM::t2ADDSri, ARM::t2ADDri},
2149 {ARM::t2ADDSrr, ARM::t2ADDrr},
2150 {ARM::t2ADDSrs, ARM::t2ADDrs},
2152 {ARM::t2SUBSri, ARM::t2SUBri},
2153 {ARM::t2SUBSrr, ARM::t2SUBrr},
2154 {ARM::t2SUBSrs, ARM::t2SUBrs},
2156 {ARM::t2RSBSri, ARM::t2RSBri},
2157 {ARM::t2RSBSrs, ARM::t2RSBrs},
2160 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
2161 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
2162 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
2163 return AddSubFlagsOpcodeMap[i].MachineOpc;
2167 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
2168 MachineBasicBlock::iterator &MBBI,
2169 const DebugLoc &dl, unsigned DestReg,
2170 unsigned BaseReg, int NumBytes,
2171 ARMCC::CondCodes Pred, unsigned PredReg,
2172 const ARMBaseInstrInfo &TII,
2174 if (NumBytes == 0 && DestReg != BaseReg) {
2175 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2176 .addReg(BaseReg, RegState::Kill)
2177 .add(predOps(Pred, PredReg))
2179 .setMIFlags(MIFlags);
2183 bool isSub = NumBytes < 0;
2184 if (isSub) NumBytes = -NumBytes;
2187 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2188 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2189 assert(ThisVal && "Didn't extract field correctly");
2191 // We will handle these bits from offset, clear them.
2192 NumBytes &= ~ThisVal;
2194 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2196 // Build the new ADD / SUB.
2197 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2198 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2199 .addReg(BaseReg, RegState::Kill)
2201 .add(predOps(Pred, PredReg))
2203 .setMIFlags(MIFlags);
2208 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
2209 MachineFunction &MF, MachineInstr *MI,
2210 unsigned NumBytes) {
2211 // This optimisation potentially adds lots of load and store
2212 // micro-operations, it's only really a great benefit to code-size.
2213 if (!MF.getFunction().optForMinSize())
2216 // If only one register is pushed/popped, LLVM can use an LDR/STR
2217 // instead. We can't modify those so make sure we're dealing with an
2218 // instruction we understand.
2219 bool IsPop = isPopOpcode(MI->getOpcode());
2220 bool IsPush = isPushOpcode(MI->getOpcode());
2221 if (!IsPush && !IsPop)
2224 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2225 MI->getOpcode() == ARM::VLDMDIA_UPD;
2226 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2227 MI->getOpcode() == ARM::tPOP ||
2228 MI->getOpcode() == ARM::tPOP_RET;
2230 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2231 MI->getOperand(1).getReg() == ARM::SP)) &&
2232 "trying to fold sp update into non-sp-updating push/pop");
2234 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2235 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2236 // if this is violated.
2237 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2240 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2241 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2242 int RegListIdx = IsT1PushPop ? 2 : 4;
2244 // Calculate the space we'll need in terms of registers.
2245 unsigned RegsNeeded;
2246 const TargetRegisterClass *RegClass;
2248 RegsNeeded = NumBytes / 8;
2249 RegClass = &ARM::DPRRegClass;
2251 RegsNeeded = NumBytes / 4;
2252 RegClass = &ARM::GPRRegClass;
2255 // We're going to have to strip all list operands off before
2256 // re-adding them since the order matters, so save the existing ones
2258 SmallVector<MachineOperand, 4> RegList;
2260 // We're also going to need the first register transferred by this
2261 // instruction, which won't necessarily be the first register in the list.
2262 unsigned FirstRegEnc = -1;
2264 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2265 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) {
2266 MachineOperand &MO = MI->getOperand(i);
2267 RegList.push_back(MO);
2269 if (MO.isReg() && TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2270 FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2273 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2275 // Now try to find enough space in the reglist to allocate NumBytes.
2276 for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
2278 unsigned CurReg = RegClass->getRegister(CurRegEnc);
2280 // Pushing any register is completely harmless, mark the
2281 // register involved as undef since we don't care about it in
2283 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2284 false, false, true));
2289 // However, we can only pop an extra register if it's not live. For
2290 // registers live within the function we might clobber a return value
2291 // register; the other way a register can be live here is if it's
2293 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2294 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2295 MachineBasicBlock::LQR_Dead) {
2296 // VFP pops don't allow holes in the register list, so any skip is fatal
2297 // for our transformation. GPR pops do, so we should just keep looking.
2304 // Mark the unimportant registers as <def,dead> in the POP.
2305 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2313 // Finally we know we can profitably perform the optimisation so go
2314 // ahead: strip all existing registers off and add them back again
2315 // in the right order.
2316 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2317 MI->RemoveOperand(i);
2319 // Add the complete list back in.
2320 MachineInstrBuilder MIB(MF, &*MI);
2321 for (int i = RegList.size() - 1; i >= 0; --i)
2322 MIB.add(RegList[i]);
2327 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2328 unsigned FrameReg, int &Offset,
2329 const ARMBaseInstrInfo &TII) {
2330 unsigned Opcode = MI.getOpcode();
2331 const MCInstrDesc &Desc = MI.getDesc();
2332 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2335 // Memory operands in inline assembly always use AddrMode2.
2336 if (Opcode == ARM::INLINEASM)
2337 AddrMode = ARMII::AddrMode2;
2339 if (Opcode == ARM::ADDri) {
2340 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2342 // Turn it into a move.
2343 MI.setDesc(TII.get(ARM::MOVr));
2344 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2345 MI.RemoveOperand(FrameRegIdx+1);
2348 } else if (Offset < 0) {
2351 MI.setDesc(TII.get(ARM::SUBri));
2354 // Common case: small offset, fits into instruction.
2355 if (ARM_AM::getSOImmVal(Offset) != -1) {
2356 // Replace the FrameIndex with sp / fp
2357 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2358 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2363 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2365 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2366 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2368 // We will handle these bits from offset, clear them.
2369 Offset &= ~ThisImmVal;
2371 // Get the properly encoded SOImmVal field.
2372 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2373 "Bit extraction didn't work?");
2374 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2376 unsigned ImmIdx = 0;
2378 unsigned NumBits = 0;
2381 case ARMII::AddrMode_i12:
2382 ImmIdx = FrameRegIdx + 1;
2383 InstrOffs = MI.getOperand(ImmIdx).getImm();
2386 case ARMII::AddrMode2:
2387 ImmIdx = FrameRegIdx+2;
2388 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2389 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2393 case ARMII::AddrMode3:
2394 ImmIdx = FrameRegIdx+2;
2395 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2396 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2400 case ARMII::AddrMode4:
2401 case ARMII::AddrMode6:
2402 // Can't fold any offset even if it's zero.
2404 case ARMII::AddrMode5:
2405 ImmIdx = FrameRegIdx+1;
2406 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2407 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2413 llvm_unreachable("Unsupported addressing mode!");
2416 Offset += InstrOffs * Scale;
2417 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2423 // Attempt to fold address comp. if opcode has offset bits
2425 // Common case: small offset, fits into instruction.
2426 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2427 int ImmedOffset = Offset / Scale;
2428 unsigned Mask = (1 << NumBits) - 1;
2429 if ((unsigned)Offset <= Mask * Scale) {
2430 // Replace the FrameIndex with sp
2431 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2432 // FIXME: When addrmode2 goes away, this will simplify (like the
2433 // T2 version), as the LDR.i12 versions don't need the encoding
2434 // tricks for the offset value.
2436 if (AddrMode == ARMII::AddrMode_i12)
2437 ImmedOffset = -ImmedOffset;
2439 ImmedOffset |= 1 << NumBits;
2441 ImmOp.ChangeToImmediate(ImmedOffset);
2446 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2447 ImmedOffset = ImmedOffset & Mask;
2449 if (AddrMode == ARMII::AddrMode_i12)
2450 ImmedOffset = -ImmedOffset;
2452 ImmedOffset |= 1 << NumBits;
2454 ImmOp.ChangeToImmediate(ImmedOffset);
2455 Offset &= ~(Mask*Scale);
2459 Offset = (isSub) ? -Offset : Offset;
2463 /// analyzeCompare - For a comparison instruction, return the source registers
2464 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2465 /// compares against in CmpValue. Return true if the comparison instruction
2466 /// can be analyzed.
2467 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
2468 unsigned &SrcReg2, int &CmpMask,
2469 int &CmpValue) const {
2470 switch (MI.getOpcode()) {
2475 SrcReg = MI.getOperand(0).getReg();
2478 CmpValue = MI.getOperand(1).getImm();
2482 SrcReg = MI.getOperand(0).getReg();
2483 SrcReg2 = MI.getOperand(1).getReg();
2489 SrcReg = MI.getOperand(0).getReg();
2491 CmpMask = MI.getOperand(1).getImm();
2499 /// isSuitableForMask - Identify a suitable 'and' instruction that
2500 /// operates on the given source register and applies the same mask
2501 /// as a 'tst' instruction. Provide a limited look-through for copies.
2502 /// When successful, MI will hold the found instruction.
2503 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2504 int CmpMask, bool CommonUse) {
2505 switch (MI->getOpcode()) {
2508 if (CmpMask != MI->getOperand(2).getImm())
2510 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2518 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2519 /// the condition code if we modify the instructions such that flags are
2521 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2523 default: return ARMCC::AL;
2524 case ARMCC::EQ: return ARMCC::EQ;
2525 case ARMCC::NE: return ARMCC::NE;
2526 case ARMCC::HS: return ARMCC::LS;
2527 case ARMCC::LO: return ARMCC::HI;
2528 case ARMCC::HI: return ARMCC::LO;
2529 case ARMCC::LS: return ARMCC::HS;
2530 case ARMCC::GE: return ARMCC::LE;
2531 case ARMCC::LT: return ARMCC::GT;
2532 case ARMCC::GT: return ARMCC::LT;
2533 case ARMCC::LE: return ARMCC::GE;
2537 /// isRedundantFlagInstr - check whether the first instruction, whose only
2538 /// purpose is to update flags, can be made redundant.
2539 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2540 /// CMPri can be made redundant by SUBri if the operands are the same.
2541 /// This function can be extended later on.
2542 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2543 unsigned SrcReg2, int ImmValue,
2545 if ((CmpI->getOpcode() == ARM::CMPrr ||
2546 CmpI->getOpcode() == ARM::t2CMPrr) &&
2547 (OI->getOpcode() == ARM::SUBrr ||
2548 OI->getOpcode() == ARM::t2SUBrr) &&
2549 ((OI->getOperand(1).getReg() == SrcReg &&
2550 OI->getOperand(2).getReg() == SrcReg2) ||
2551 (OI->getOperand(1).getReg() == SrcReg2 &&
2552 OI->getOperand(2).getReg() == SrcReg)))
2555 if ((CmpI->getOpcode() == ARM::CMPri ||
2556 CmpI->getOpcode() == ARM::t2CMPri) &&
2557 (OI->getOpcode() == ARM::SUBri ||
2558 OI->getOpcode() == ARM::t2SUBri) &&
2559 OI->getOperand(1).getReg() == SrcReg &&
2560 OI->getOperand(2).getImm() == ImmValue)
2565 static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
2566 switch (MI->getOpcode()) {
2567 default: return false;
2622 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2623 /// comparison into one that sets the zero bit in the flags register;
2624 /// Remove a redundant Compare instruction if an earlier instruction can set the
2625 /// flags in the same way as Compare.
2626 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2627 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2628 /// condition code of instructions which use the flags.
2629 bool ARMBaseInstrInfo::optimizeCompareInstr(
2630 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
2631 int CmpValue, const MachineRegisterInfo *MRI) const {
2632 // Get the unique definition of SrcReg.
2633 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2634 if (!MI) return false;
2636 // Masked compares sometimes use the same register as the corresponding 'and'.
2637 if (CmpMask != ~0) {
2638 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2640 for (MachineRegisterInfo::use_instr_iterator
2641 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2643 if (UI->getParent() != CmpInstr.getParent())
2645 MachineInstr *PotentialAND = &*UI;
2646 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2647 isPredicated(*PotentialAND))
2652 if (!MI) return false;
2656 // Get ready to iterate backward from CmpInstr.
2657 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2658 B = CmpInstr.getParent()->begin();
2660 // Early exit if CmpInstr is at the beginning of the BB.
2661 if (I == B) return false;
2663 // There are two possible candidates which can be changed to set CPSR:
2664 // One is MI, the other is a SUB instruction.
2665 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2666 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2667 MachineInstr *Sub = nullptr;
2669 // MI is not a candidate for CMPrr.
2671 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
2672 // Conservatively refuse to convert an instruction which isn't in the same
2673 // BB as the comparison.
2674 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2675 // Thus we cannot return here.
2676 if (CmpInstr.getOpcode() == ARM::CMPri ||
2677 CmpInstr.getOpcode() == ARM::t2CMPri)
2683 bool IsThumb1 = false;
2684 if (MI && !isOptimizeCompareCandidate(MI, IsThumb1))
2687 // We also want to do this peephole for cases like this: if (a*b == 0),
2688 // and optimise away the CMP instruction from the generated code sequence:
2689 // MULS, MOVS, MOVS, CMP. Here the MOVS instructions load the boolean values
2690 // resulting from the select instruction, but these MOVS instructions for
2691 // Thumb1 (V6M) are flag setting and are thus preventing this optimisation.
2692 // However, if we only have MOVS instructions in between the CMP and the
2693 // other instruction (the MULS in this example), then the CPSR is dead so we
2694 // can safely reorder the sequence into: MOVS, MOVS, MULS, CMP. We do this
2695 // reordering and then continue the analysis hoping we can eliminate the
2696 // CMP. This peephole works on the vregs, so is still in SSA form. As a
2697 // consequence, the movs won't redefine/kill the MUL operands which would
2698 // make this reordering illegal.
2699 if (MI && IsThumb1) {
2701 bool CanReorder = true;
2702 const bool HasStmts = I != E;
2703 for (; I != E; --I) {
2704 if (I->getOpcode() != ARM::tMOVi8) {
2709 if (HasStmts && CanReorder) {
2710 MI = MI->removeFromParent();
2712 CmpInstr.getParent()->insert(E, MI);
2718 // Check that CPSR isn't set between the comparison instruction and the one we
2719 // want to change. At the same time, search for Sub.
2720 const TargetRegisterInfo *TRI = &getRegisterInfo();
2722 for (; I != E; --I) {
2723 const MachineInstr &Instr = *I;
2725 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2726 Instr.readsRegister(ARM::CPSR, TRI))
2727 // This instruction modifies or uses CPSR after the one we want to
2728 // change. We can't do this transformation.
2731 // Check whether CmpInstr can be made redundant by the current instruction.
2732 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2738 // The 'and' is below the comparison instruction.
2742 // Return false if no candidates exist.
2746 // The single candidate is called MI.
2749 // We can't use a predicated instruction - it doesn't always write the flags.
2750 if (isPredicated(*MI))
2753 // Scan forward for the use of CPSR
2754 // When checking against MI: if it's a conditional code that requires
2755 // checking of the V bit or C bit, then this is not safe to do.
2756 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2757 // If we are done with the basic block, we need to check whether CPSR is
2759 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2761 bool isSafe = false;
2763 E = CmpInstr.getParent()->end();
2764 while (!isSafe && ++I != E) {
2765 const MachineInstr &Instr = *I;
2766 for (unsigned IO = 0, EO = Instr.getNumOperands();
2767 !isSafe && IO != EO; ++IO) {
2768 const MachineOperand &MO = Instr.getOperand(IO);
2769 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2773 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2779 // Condition code is after the operand before CPSR except for VSELs.
2780 ARMCC::CondCodes CC;
2781 bool IsInstrVSel = true;
2782 switch (Instr.getOpcode()) {
2784 IsInstrVSel = false;
2785 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2806 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2807 if (NewCC == ARMCC::AL)
2809 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2810 // on CMP needs to be updated to be based on SUB.
2811 // Push the condition code operands to OperandsToUpdate.
2812 // If it is safe to remove CmpInstr, the condition code of these
2813 // operands will be modified.
2814 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2815 Sub->getOperand(2).getReg() == SrcReg) {
2816 // VSel doesn't support condition code update.
2819 OperandsToUpdate.push_back(
2820 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2823 // No Sub, so this is x = <op> y, z; cmp x, 0.
2825 case ARMCC::EQ: // Z
2826 case ARMCC::NE: // Z
2827 case ARMCC::MI: // N
2828 case ARMCC::PL: // N
2829 case ARMCC::AL: // none
2830 // CPSR can be used multiple times, we should continue.
2832 case ARMCC::HS: // C
2833 case ARMCC::LO: // C
2834 case ARMCC::VS: // V
2835 case ARMCC::VC: // V
2836 case ARMCC::HI: // C Z
2837 case ARMCC::LS: // C Z
2838 case ARMCC::GE: // N V
2839 case ARMCC::LT: // N V
2840 case ARMCC::GT: // Z N V
2841 case ARMCC::LE: // Z N V
2842 // The instruction uses the V bit or C bit which is not safe.
2849 // If CPSR is not killed nor re-defined, we should check whether it is
2850 // live-out. If it is live-out, do not optimize.
2852 MachineBasicBlock *MBB = CmpInstr.getParent();
2853 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2854 SE = MBB->succ_end(); SI != SE; ++SI)
2855 if ((*SI)->isLiveIn(ARM::CPSR))
2859 // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
2860 // set CPSR so this is represented as an explicit output)
2862 MI->getOperand(5).setReg(ARM::CPSR);
2863 MI->getOperand(5).setIsDef(true);
2865 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
2866 CmpInstr.eraseFromParent();
2868 // Modify the condition code of operands in OperandsToUpdate.
2869 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2870 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2871 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2872 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2877 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2879 MachineRegisterInfo *MRI) const {
2880 // Fold large immediates into add, sub, or, xor.
2881 unsigned DefOpc = DefMI.getOpcode();
2882 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2884 if (!DefMI.getOperand(1).isImm())
2885 // Could be t2MOVi32imm @xx
2888 if (!MRI->hasOneNonDBGUse(Reg))
2891 const MCInstrDesc &DefMCID = DefMI.getDesc();
2892 if (DefMCID.hasOptionalDef()) {
2893 unsigned NumOps = DefMCID.getNumOperands();
2894 const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
2895 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2896 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2901 const MCInstrDesc &UseMCID = UseMI.getDesc();
2902 if (UseMCID.hasOptionalDef()) {
2903 unsigned NumOps = UseMCID.getNumOperands();
2904 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
2905 // If the instruction sets the flag, do not attempt this optimization
2906 // since it may change the semantics of the code.
2910 unsigned UseOpc = UseMI.getOpcode();
2911 unsigned NewUseOpc = 0;
2912 uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
2913 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2914 bool Commute = false;
2916 default: return false;
2924 case ARM::t2EORrr: {
2925 Commute = UseMI.getOperand(2).getReg() != Reg;
2930 if (UseOpc == ARM::SUBrr && Commute)
2933 // ADD/SUB are special because they're essentially the same operation, so
2934 // we can handle a larger range of immediates.
2935 if (ARM_AM::isSOImmTwoPartVal(ImmVal))
2936 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
2937 else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
2939 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
2942 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2943 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2947 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2949 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2950 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2953 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2954 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2959 if (UseOpc == ARM::t2SUBrr && Commute)
2962 // ADD/SUB are special because they're essentially the same operation, so
2963 // we can handle a larger range of immediates.
2964 if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2965 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
2966 else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
2968 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
2971 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2972 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2976 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2978 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2979 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2982 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2983 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2990 unsigned OpIdx = Commute ? 2 : 1;
2991 unsigned Reg1 = UseMI.getOperand(OpIdx).getReg();
2992 bool isKill = UseMI.getOperand(OpIdx).isKill();
2993 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2994 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
2996 .addReg(Reg1, getKillRegState(isKill))
2998 .add(predOps(ARMCC::AL))
3000 UseMI.setDesc(get(NewUseOpc));
3001 UseMI.getOperand(1).setReg(NewReg);
3002 UseMI.getOperand(1).setIsKill();
3003 UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
3004 DefMI.eraseFromParent();
3008 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
3009 const MachineInstr &MI) {
3010 switch (MI.getOpcode()) {
3012 const MCInstrDesc &Desc = MI.getDesc();
3013 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
3014 assert(UOps >= 0 && "bad # UOps");
3022 unsigned ShOpVal = MI.getOperand(3).getImm();
3023 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3024 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3027 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3028 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3035 if (!MI.getOperand(2).getReg())
3038 unsigned ShOpVal = MI.getOperand(3).getImm();
3039 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3040 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3043 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3044 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3051 return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
3053 case ARM::LDRSB_POST:
3054 case ARM::LDRSH_POST: {
3055 unsigned Rt = MI.getOperand(0).getReg();
3056 unsigned Rm = MI.getOperand(3).getReg();
3057 return (Rt == Rm) ? 4 : 3;
3060 case ARM::LDR_PRE_REG:
3061 case ARM::LDRB_PRE_REG: {
3062 unsigned Rt = MI.getOperand(0).getReg();
3063 unsigned Rm = MI.getOperand(3).getReg();
3066 unsigned ShOpVal = MI.getOperand(4).getImm();
3067 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3068 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3071 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3072 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3077 case ARM::STR_PRE_REG:
3078 case ARM::STRB_PRE_REG: {
3079 unsigned ShOpVal = MI.getOperand(4).getImm();
3080 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3081 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3084 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3085 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3091 case ARM::STRH_PRE: {
3092 unsigned Rt = MI.getOperand(0).getReg();
3093 unsigned Rm = MI.getOperand(3).getReg();
3098 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
3101 case ARM::LDR_POST_REG:
3102 case ARM::LDRB_POST_REG:
3103 case ARM::LDRH_POST: {
3104 unsigned Rt = MI.getOperand(0).getReg();
3105 unsigned Rm = MI.getOperand(3).getReg();
3106 return (Rt == Rm) ? 3 : 2;
3109 case ARM::LDR_PRE_IMM:
3110 case ARM::LDRB_PRE_IMM:
3111 case ARM::LDR_POST_IMM:
3112 case ARM::LDRB_POST_IMM:
3113 case ARM::STRB_POST_IMM:
3114 case ARM::STRB_POST_REG:
3115 case ARM::STRB_PRE_IMM:
3116 case ARM::STRH_POST:
3117 case ARM::STR_POST_IMM:
3118 case ARM::STR_POST_REG:
3119 case ARM::STR_PRE_IMM:
3122 case ARM::LDRSB_PRE:
3123 case ARM::LDRSH_PRE: {
3124 unsigned Rm = MI.getOperand(3).getReg();
3127 unsigned Rt = MI.getOperand(0).getReg();
3130 unsigned ShOpVal = MI.getOperand(4).getImm();
3131 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3132 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3135 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3136 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3142 unsigned Rt = MI.getOperand(0).getReg();
3143 unsigned Rn = MI.getOperand(2).getReg();
3144 unsigned Rm = MI.getOperand(3).getReg();
3146 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3148 return (Rt == Rn) ? 3 : 2;
3152 unsigned Rm = MI.getOperand(3).getReg();
3154 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3159 case ARM::LDRD_POST:
3160 case ARM::t2LDRD_POST:
3163 case ARM::STRD_POST:
3164 case ARM::t2STRD_POST:
3167 case ARM::LDRD_PRE: {
3168 unsigned Rt = MI.getOperand(0).getReg();
3169 unsigned Rn = MI.getOperand(3).getReg();
3170 unsigned Rm = MI.getOperand(4).getReg();
3172 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3174 return (Rt == Rn) ? 4 : 3;
3177 case ARM::t2LDRD_PRE: {
3178 unsigned Rt = MI.getOperand(0).getReg();
3179 unsigned Rn = MI.getOperand(3).getReg();
3180 return (Rt == Rn) ? 4 : 3;
3183 case ARM::STRD_PRE: {
3184 unsigned Rm = MI.getOperand(4).getReg();
3186 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3191 case ARM::t2STRD_PRE:
3194 case ARM::t2LDR_POST:
3195 case ARM::t2LDRB_POST:
3196 case ARM::t2LDRB_PRE:
3197 case ARM::t2LDRSBi12:
3198 case ARM::t2LDRSBi8:
3199 case ARM::t2LDRSBpci:
3201 case ARM::t2LDRH_POST:
3202 case ARM::t2LDRH_PRE:
3204 case ARM::t2LDRSB_POST:
3205 case ARM::t2LDRSB_PRE:
3206 case ARM::t2LDRSH_POST:
3207 case ARM::t2LDRSH_PRE:
3208 case ARM::t2LDRSHi12:
3209 case ARM::t2LDRSHi8:
3210 case ARM::t2LDRSHpci:
3214 case ARM::t2LDRDi8: {
3215 unsigned Rt = MI.getOperand(0).getReg();
3216 unsigned Rn = MI.getOperand(2).getReg();
3217 return (Rt == Rn) ? 3 : 2;
3220 case ARM::t2STRB_POST:
3221 case ARM::t2STRB_PRE:
3224 case ARM::t2STRH_POST:
3225 case ARM::t2STRH_PRE:
3227 case ARM::t2STR_POST:
3228 case ARM::t2STR_PRE:
3234 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
3235 // can't be easily determined return 0 (missing MachineMemOperand).
3237 // FIXME: The current MachineInstr design does not support relying on machine
3238 // mem operands to determine the width of a memory access. Instead, we expect
3239 // the target to provide this information based on the instruction opcode and
3240 // operands. However, using MachineMemOperand is the best solution now for
3243 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3244 // operands. This is much more dangerous than using the MachineMemOperand
3245 // sizes because CodeGen passes can insert/remove optional machine operands. In
3246 // fact, it's totally incorrect for preRA passes and appears to be wrong for
3247 // postRA passes as well.
3249 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
3250 // machine model that calls this should handle the unknown (zero size) case.
3252 // Long term, we should require a target hook that verifies MachineMemOperand
3253 // sizes during MC lowering. That target hook should be local to MC lowering
3254 // because we can't ensure that it is aware of other MI forms. Doing this will
3255 // ensure that MachineMemOperands are correctly propagated through all passes.
3256 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {
3258 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
3259 E = MI.memoperands_end();
3261 Size += (*I)->getSize();
3266 static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,
3268 unsigned UOps = 1 + NumRegs; // 1 for address computation.
3272 case ARM::VLDMDIA_UPD:
3273 case ARM::VLDMDDB_UPD:
3274 case ARM::VLDMSIA_UPD:
3275 case ARM::VLDMSDB_UPD:
3276 case ARM::VSTMDIA_UPD:
3277 case ARM::VSTMDDB_UPD:
3278 case ARM::VSTMSIA_UPD:
3279 case ARM::VSTMSDB_UPD:
3280 case ARM::LDMIA_UPD:
3281 case ARM::LDMDA_UPD:
3282 case ARM::LDMDB_UPD:
3283 case ARM::LDMIB_UPD:
3284 case ARM::STMIA_UPD:
3285 case ARM::STMDA_UPD:
3286 case ARM::STMDB_UPD:
3287 case ARM::STMIB_UPD:
3288 case ARM::tLDMIA_UPD:
3289 case ARM::tSTMIA_UPD:
3290 case ARM::t2LDMIA_UPD:
3291 case ARM::t2LDMDB_UPD:
3292 case ARM::t2STMIA_UPD:
3293 case ARM::t2STMDB_UPD:
3294 ++UOps; // One for base register writeback.
3296 case ARM::LDMIA_RET:
3298 case ARM::t2LDMIA_RET:
3299 UOps += 2; // One for base reg wb, one for write to pc.
3305 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3306 const MachineInstr &MI) const {
3307 if (!ItinData || ItinData->isEmpty())
3310 const MCInstrDesc &Desc = MI.getDesc();
3311 unsigned Class = Desc.getSchedClass();
3312 int ItinUOps = ItinData->getNumMicroOps(Class);
3313 if (ItinUOps >= 0) {
3314 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3315 return getNumMicroOpsSwiftLdSt(ItinData, MI);
3320 unsigned Opc = MI.getOpcode();
3323 llvm_unreachable("Unexpected multi-uops instruction!");
3328 // The number of uOps for load / store multiple are determined by the number
3331 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3332 // same cycle. The scheduling for the first load / store must be done
3333 // separately by assuming the address is not 64-bit aligned.
3335 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3336 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3337 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3339 case ARM::VLDMDIA_UPD:
3340 case ARM::VLDMDDB_UPD:
3342 case ARM::VLDMSIA_UPD:
3343 case ARM::VLDMSDB_UPD:
3345 case ARM::VSTMDIA_UPD:
3346 case ARM::VSTMDDB_UPD:
3348 case ARM::VSTMSIA_UPD:
3349 case ARM::VSTMSDB_UPD: {
3350 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands();
3351 return (NumRegs / 2) + (NumRegs % 2) + 1;
3354 case ARM::LDMIA_RET:
3359 case ARM::LDMIA_UPD:
3360 case ARM::LDMDA_UPD:
3361 case ARM::LDMDB_UPD:
3362 case ARM::LDMIB_UPD:
3367 case ARM::STMIA_UPD:
3368 case ARM::STMDA_UPD:
3369 case ARM::STMDB_UPD:
3370 case ARM::STMIB_UPD:
3372 case ARM::tLDMIA_UPD:
3373 case ARM::tSTMIA_UPD:
3377 case ARM::t2LDMIA_RET:
3380 case ARM::t2LDMIA_UPD:
3381 case ARM::t2LDMDB_UPD:
3384 case ARM::t2STMIA_UPD:
3385 case ARM::t2STMDB_UPD: {
3386 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1;
3387 switch (Subtarget.getLdStMultipleTiming()) {
3388 case ARMSubtarget::SingleIssuePlusExtras:
3389 return getNumMicroOpsSingleIssuePlusExtras(Opc, NumRegs);
3390 case ARMSubtarget::SingleIssue:
3391 // Assume the worst.
3393 case ARMSubtarget::DoubleIssue: {
3396 // 4 registers would be issued: 2, 2.
3397 // 5 registers would be issued: 2, 2, 1.
3398 unsigned UOps = (NumRegs / 2);
3403 case ARMSubtarget::DoubleIssueCheckUnalignedAccess: {
3404 unsigned UOps = (NumRegs / 2);
3405 // If there are odd number of registers or if it's not 64-bit aligned,
3406 // then it takes an extra AGU (Address Generation Unit) cycle.
3407 if ((NumRegs % 2) || !MI.hasOneMemOperand() ||
3408 (*MI.memoperands_begin())->getAlignment() < 8)
3415 llvm_unreachable("Didn't find the number of microops");
3419 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3420 const MCInstrDesc &DefMCID,
3422 unsigned DefIdx, unsigned DefAlign) const {
3423 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3425 // Def is the address writeback.
3426 return ItinData->getOperandCycle(DefClass, DefIdx);
3429 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3430 // (regno / 2) + (regno % 2) + 1
3431 DefCycle = RegNo / 2 + 1;
3434 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3436 bool isSLoad = false;
3438 switch (DefMCID.getOpcode()) {
3441 case ARM::VLDMSIA_UPD:
3442 case ARM::VLDMSDB_UPD:
3447 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3448 // then it takes an extra cycle.
3449 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3452 // Assume the worst.
3453 DefCycle = RegNo + 2;
3459 bool ARMBaseInstrInfo::isLDMBaseRegInList(const MachineInstr &MI) const {
3460 unsigned BaseReg = MI.getOperand(0).getReg();
3461 for (unsigned i = 1, sz = MI.getNumOperands(); i < sz; ++i) {
3462 const auto &Op = MI.getOperand(i);
3463 if (Op.isReg() && Op.getReg() == BaseReg)
3469 ARMBaseInstrInfo::getLDMVariableDefsSize(const MachineInstr &MI) const {
3470 // ins GPR:$Rn, pred:$p (2xOp), reglist:$regs, variable_ops
3471 // (outs GPR:$wb), (ins GPR:$Rn, pred:$p (2xOp), reglist:$regs, variable_ops)
3472 return MI.getNumOperands() + 1 - MI.getDesc().getNumOperands();
3476 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3477 const MCInstrDesc &DefMCID,
3479 unsigned DefIdx, unsigned DefAlign) const {
3480 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3482 // Def is the address writeback.
3483 return ItinData->getOperandCycle(DefClass, DefIdx);
3486 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3487 // 4 registers would be issued: 1, 2, 1.
3488 // 5 registers would be issued: 1, 2, 2.
3489 DefCycle = RegNo / 2;
3492 // Result latency is issue cycle + 2: E2.
3494 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3495 DefCycle = (RegNo / 2);
3496 // If there are odd number of registers or if it's not 64-bit aligned,
3497 // then it takes an extra AGU (Address Generation Unit) cycle.
3498 if ((RegNo % 2) || DefAlign < 8)
3500 // Result latency is AGU cycles + 2.
3503 // Assume the worst.
3504 DefCycle = RegNo + 2;
3511 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3512 const MCInstrDesc &UseMCID,
3514 unsigned UseIdx, unsigned UseAlign) const {
3515 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3517 return ItinData->getOperandCycle(UseClass, UseIdx);
3520 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3521 // (regno / 2) + (regno % 2) + 1
3522 UseCycle = RegNo / 2 + 1;
3525 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3527 bool isSStore = false;
3529 switch (UseMCID.getOpcode()) {
3532 case ARM::VSTMSIA_UPD:
3533 case ARM::VSTMSDB_UPD:
3538 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3539 // then it takes an extra cycle.
3540 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3543 // Assume the worst.
3544 UseCycle = RegNo + 2;
3551 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3552 const MCInstrDesc &UseMCID,
3554 unsigned UseIdx, unsigned UseAlign) const {
3555 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3557 return ItinData->getOperandCycle(UseClass, UseIdx);
3560 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3561 UseCycle = RegNo / 2;
3566 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3567 UseCycle = (RegNo / 2);
3568 // If there are odd number of registers or if it's not 64-bit aligned,
3569 // then it takes an extra AGU (Address Generation Unit) cycle.
3570 if ((RegNo % 2) || UseAlign < 8)
3573 // Assume the worst.
3580 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3581 const MCInstrDesc &DefMCID,
3582 unsigned DefIdx, unsigned DefAlign,
3583 const MCInstrDesc &UseMCID,
3584 unsigned UseIdx, unsigned UseAlign) const {
3585 unsigned DefClass = DefMCID.getSchedClass();
3586 unsigned UseClass = UseMCID.getSchedClass();
3588 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3589 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3591 // This may be a def / use of a variable_ops instruction, the operand
3592 // latency might be determinable dynamically. Let the target try to
3595 bool LdmBypass = false;
3596 switch (DefMCID.getOpcode()) {
3598 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3602 case ARM::VLDMDIA_UPD:
3603 case ARM::VLDMDDB_UPD:
3605 case ARM::VLDMSIA_UPD:
3606 case ARM::VLDMSDB_UPD:
3607 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3610 case ARM::LDMIA_RET:
3615 case ARM::LDMIA_UPD:
3616 case ARM::LDMDA_UPD:
3617 case ARM::LDMDB_UPD:
3618 case ARM::LDMIB_UPD:
3620 case ARM::tLDMIA_UPD:
3622 case ARM::t2LDMIA_RET:
3625 case ARM::t2LDMIA_UPD:
3626 case ARM::t2LDMDB_UPD:
3628 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3633 // We can't seem to determine the result latency of the def, assume it's 2.
3637 switch (UseMCID.getOpcode()) {
3639 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3643 case ARM::VSTMDIA_UPD:
3644 case ARM::VSTMDDB_UPD:
3646 case ARM::VSTMSIA_UPD:
3647 case ARM::VSTMSDB_UPD:
3648 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3655 case ARM::STMIA_UPD:
3656 case ARM::STMDA_UPD:
3657 case ARM::STMDB_UPD:
3658 case ARM::STMIB_UPD:
3659 case ARM::tSTMIA_UPD:
3664 case ARM::t2STMIA_UPD:
3665 case ARM::t2STMDB_UPD:
3666 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3671 // Assume it's read in the first stage.
3674 UseCycle = DefCycle - UseCycle + 1;
3677 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3678 // first def operand.
3679 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3682 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3683 UseClass, UseIdx)) {
3691 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3692 const MachineInstr *MI, unsigned Reg,
3693 unsigned &DefIdx, unsigned &Dist) {
3696 MachineBasicBlock::const_iterator I = MI; ++I;
3697 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3698 assert(II->isInsideBundle() && "Empty bundle?");
3701 while (II->isInsideBundle()) {
3702 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3709 assert(Idx != -1 && "Cannot find bundled definition!");
3714 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3715 const MachineInstr &MI, unsigned Reg,
3716 unsigned &UseIdx, unsigned &Dist) {
3719 MachineBasicBlock::const_instr_iterator II = ++MI.getIterator();
3720 assert(II->isInsideBundle() && "Empty bundle?");
3721 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
3723 // FIXME: This doesn't properly handle multiple uses.
3725 while (II != E && II->isInsideBundle()) {
3726 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3729 if (II->getOpcode() != ARM::t2IT)
3743 /// Return the number of cycles to add to (or subtract from) the static
3744 /// itinerary based on the def opcode and alignment. The caller will ensure that
3745 /// adjusted latency is at least one cycle.
3746 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3747 const MachineInstr &DefMI,
3748 const MCInstrDesc &DefMCID, unsigned DefAlign) {
3750 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3751 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3752 // variants are one cycle cheaper.
3753 switch (DefMCID.getOpcode()) {
3757 unsigned ShOpVal = DefMI.getOperand(3).getImm();
3758 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3760 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3767 case ARM::t2LDRSHs: {
3768 // Thumb2 mode: lsl only.
3769 unsigned ShAmt = DefMI.getOperand(3).getImm();
3770 if (ShAmt == 0 || ShAmt == 2)
3775 } else if (Subtarget.isSwift()) {
3776 // FIXME: Properly handle all of the latency adjustments for address
3778 switch (DefMCID.getOpcode()) {
3782 unsigned ShOpVal = DefMI.getOperand(3).getImm();
3783 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3784 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3787 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3788 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3791 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3798 case ARM::t2LDRSHs: {
3799 // Thumb2 mode: lsl only.
3800 unsigned ShAmt = DefMI.getOperand(3).getImm();
3801 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3808 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) {
3809 switch (DefMCID.getOpcode()) {
3815 case ARM::VLD1q8wb_fixed:
3816 case ARM::VLD1q16wb_fixed:
3817 case ARM::VLD1q32wb_fixed:
3818 case ARM::VLD1q64wb_fixed:
3819 case ARM::VLD1q8wb_register:
3820 case ARM::VLD1q16wb_register:
3821 case ARM::VLD1q32wb_register:
3822 case ARM::VLD1q64wb_register:
3829 case ARM::VLD2d8wb_fixed:
3830 case ARM::VLD2d16wb_fixed:
3831 case ARM::VLD2d32wb_fixed:
3832 case ARM::VLD2q8wb_fixed:
3833 case ARM::VLD2q16wb_fixed:
3834 case ARM::VLD2q32wb_fixed:
3835 case ARM::VLD2d8wb_register:
3836 case ARM::VLD2d16wb_register:
3837 case ARM::VLD2d32wb_register:
3838 case ARM::VLD2q8wb_register:
3839 case ARM::VLD2q16wb_register:
3840 case ARM::VLD2q32wb_register:
3845 case ARM::VLD3d8_UPD:
3846 case ARM::VLD3d16_UPD:
3847 case ARM::VLD3d32_UPD:
3848 case ARM::VLD1d64Twb_fixed:
3849 case ARM::VLD1d64Twb_register:
3850 case ARM::VLD3q8_UPD:
3851 case ARM::VLD3q16_UPD:
3852 case ARM::VLD3q32_UPD:
3857 case ARM::VLD4d8_UPD:
3858 case ARM::VLD4d16_UPD:
3859 case ARM::VLD4d32_UPD:
3860 case ARM::VLD1d64Qwb_fixed:
3861 case ARM::VLD1d64Qwb_register:
3862 case ARM::VLD4q8_UPD:
3863 case ARM::VLD4q16_UPD:
3864 case ARM::VLD4q32_UPD:
3865 case ARM::VLD1DUPq8:
3866 case ARM::VLD1DUPq16:
3867 case ARM::VLD1DUPq32:
3868 case ARM::VLD1DUPq8wb_fixed:
3869 case ARM::VLD1DUPq16wb_fixed:
3870 case ARM::VLD1DUPq32wb_fixed:
3871 case ARM::VLD1DUPq8wb_register:
3872 case ARM::VLD1DUPq16wb_register:
3873 case ARM::VLD1DUPq32wb_register:
3874 case ARM::VLD2DUPd8:
3875 case ARM::VLD2DUPd16:
3876 case ARM::VLD2DUPd32:
3877 case ARM::VLD2DUPd8wb_fixed:
3878 case ARM::VLD2DUPd16wb_fixed:
3879 case ARM::VLD2DUPd32wb_fixed:
3880 case ARM::VLD2DUPd8wb_register:
3881 case ARM::VLD2DUPd16wb_register:
3882 case ARM::VLD2DUPd32wb_register:
3883 case ARM::VLD4DUPd8:
3884 case ARM::VLD4DUPd16:
3885 case ARM::VLD4DUPd32:
3886 case ARM::VLD4DUPd8_UPD:
3887 case ARM::VLD4DUPd16_UPD:
3888 case ARM::VLD4DUPd32_UPD:
3890 case ARM::VLD1LNd16:
3891 case ARM::VLD1LNd32:
3892 case ARM::VLD1LNd8_UPD:
3893 case ARM::VLD1LNd16_UPD:
3894 case ARM::VLD1LNd32_UPD:
3896 case ARM::VLD2LNd16:
3897 case ARM::VLD2LNd32:
3898 case ARM::VLD2LNq16:
3899 case ARM::VLD2LNq32:
3900 case ARM::VLD2LNd8_UPD:
3901 case ARM::VLD2LNd16_UPD:
3902 case ARM::VLD2LNd32_UPD:
3903 case ARM::VLD2LNq16_UPD:
3904 case ARM::VLD2LNq32_UPD:
3906 case ARM::VLD4LNd16:
3907 case ARM::VLD4LNd32:
3908 case ARM::VLD4LNq16:
3909 case ARM::VLD4LNq32:
3910 case ARM::VLD4LNd8_UPD:
3911 case ARM::VLD4LNd16_UPD:
3912 case ARM::VLD4LNd32_UPD:
3913 case ARM::VLD4LNq16_UPD:
3914 case ARM::VLD4LNq32_UPD:
3915 // If the address is not 64-bit aligned, the latencies of these
3916 // instructions increases by one.
3924 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3925 const MachineInstr &DefMI,
3927 const MachineInstr &UseMI,
3928 unsigned UseIdx) const {
3929 // No operand latency. The caller may fall back to getInstrLatency.
3930 if (!ItinData || ItinData->isEmpty())
3933 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
3934 unsigned Reg = DefMO.getReg();
3936 const MachineInstr *ResolvedDefMI = &DefMI;
3937 unsigned DefAdj = 0;
3938 if (DefMI.isBundle())
3940 getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
3941 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() ||
3942 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) {
3946 const MachineInstr *ResolvedUseMI = &UseMI;
3947 unsigned UseAdj = 0;
3948 if (UseMI.isBundle()) {
3950 getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
3955 return getOperandLatencyImpl(
3956 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
3957 Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
3960 int ARMBaseInstrInfo::getOperandLatencyImpl(
3961 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
3962 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
3963 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
3964 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
3965 if (Reg == ARM::CPSR) {
3966 if (DefMI.getOpcode() == ARM::FMSTAT) {
3967 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3968 return Subtarget.isLikeA9() ? 1 : 20;
3971 // CPSR set and branch can be paired in the same cycle.
3972 if (UseMI.isBranch())
3975 // Otherwise it takes the instruction latency (generally one).
3976 unsigned Latency = getInstrLatency(ItinData, DefMI);
3978 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3979 // its uses. Instructions which are otherwise scheduled between them may
3980 // incur a code size penalty (not able to use the CPSR setting 16-bit
3982 if (Latency > 0 && Subtarget.isThumb2()) {
3983 const MachineFunction *MF = DefMI.getParent()->getParent();
3984 // FIXME: Use Function::optForSize().
3985 if (MF->getFunction().hasFnAttribute(Attribute::OptimizeForSize))
3991 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
3994 unsigned DefAlign = DefMI.hasOneMemOperand()
3995 ? (*DefMI.memoperands_begin())->getAlignment()
3997 unsigned UseAlign = UseMI.hasOneMemOperand()
3998 ? (*UseMI.memoperands_begin())->getAlignment()
4001 // Get the itinerary's latency if possible, and handle variable_ops.
4002 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,
4004 // Unable to find operand latency. The caller may resort to getInstrLatency.
4008 // Adjust for IT block position.
4009 int Adj = DefAdj + UseAdj;
4011 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4012 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
4013 if (Adj >= 0 || (int)Latency > -Adj) {
4014 return Latency + Adj;
4016 // Return the itinerary latency, which may be zero but not less than zero.
4021 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
4022 SDNode *DefNode, unsigned DefIdx,
4023 SDNode *UseNode, unsigned UseIdx) const {
4024 if (!DefNode->isMachineOpcode())
4027 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
4029 if (isZeroCost(DefMCID.Opcode))
4032 if (!ItinData || ItinData->isEmpty())
4033 return DefMCID.mayLoad() ? 3 : 1;
4035 if (!UseNode->isMachineOpcode()) {
4036 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
4037 int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
4038 int Threshold = 1 + Adj;
4039 return Latency <= Threshold ? 1 : Latency - Adj;
4042 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
4043 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
4044 unsigned DefAlign = !DefMN->memoperands_empty()
4045 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
4046 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
4047 unsigned UseAlign = !UseMN->memoperands_empty()
4048 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
4049 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
4050 UseMCID, UseIdx, UseAlign);
4053 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
4054 Subtarget.isCortexA7())) {
4055 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
4056 // variants are one cycle cheaper.
4057 switch (DefMCID.getOpcode()) {
4062 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4063 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4065 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4072 case ARM::t2LDRSHs: {
4073 // Thumb2 mode: lsl only.
4075 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4076 if (ShAmt == 0 || ShAmt == 2)
4081 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
4082 // FIXME: Properly handle all of the latency adjustments for address
4084 switch (DefMCID.getOpcode()) {
4089 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
4090 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
4092 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
4093 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
4095 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
4103 // Thumb2 mode: lsl 0-3 only.
4109 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment())
4110 switch (DefMCID.getOpcode()) {
4116 case ARM::VLD1q8wb_register:
4117 case ARM::VLD1q16wb_register:
4118 case ARM::VLD1q32wb_register:
4119 case ARM::VLD1q64wb_register:
4120 case ARM::VLD1q8wb_fixed:
4121 case ARM::VLD1q16wb_fixed:
4122 case ARM::VLD1q32wb_fixed:
4123 case ARM::VLD1q64wb_fixed:
4127 case ARM::VLD2q8Pseudo:
4128 case ARM::VLD2q16Pseudo:
4129 case ARM::VLD2q32Pseudo:
4130 case ARM::VLD2d8wb_fixed:
4131 case ARM::VLD2d16wb_fixed:
4132 case ARM::VLD2d32wb_fixed:
4133 case ARM::VLD2q8PseudoWB_fixed:
4134 case ARM::VLD2q16PseudoWB_fixed:
4135 case ARM::VLD2q32PseudoWB_fixed:
4136 case ARM::VLD2d8wb_register:
4137 case ARM::VLD2d16wb_register:
4138 case ARM::VLD2d32wb_register:
4139 case ARM::VLD2q8PseudoWB_register:
4140 case ARM::VLD2q16PseudoWB_register:
4141 case ARM::VLD2q32PseudoWB_register:
4142 case ARM::VLD3d8Pseudo:
4143 case ARM::VLD3d16Pseudo:
4144 case ARM::VLD3d32Pseudo:
4145 case ARM::VLD1d64TPseudo:
4146 case ARM::VLD1d64TPseudoWB_fixed:
4147 case ARM::VLD3d8Pseudo_UPD:
4148 case ARM::VLD3d16Pseudo_UPD:
4149 case ARM::VLD3d32Pseudo_UPD:
4150 case ARM::VLD3q8Pseudo_UPD:
4151 case ARM::VLD3q16Pseudo_UPD:
4152 case ARM::VLD3q32Pseudo_UPD:
4153 case ARM::VLD3q8oddPseudo:
4154 case ARM::VLD3q16oddPseudo:
4155 case ARM::VLD3q32oddPseudo:
4156 case ARM::VLD3q8oddPseudo_UPD:
4157 case ARM::VLD3q16oddPseudo_UPD:
4158 case ARM::VLD3q32oddPseudo_UPD:
4159 case ARM::VLD4d8Pseudo:
4160 case ARM::VLD4d16Pseudo:
4161 case ARM::VLD4d32Pseudo:
4162 case ARM::VLD1d64QPseudo:
4163 case ARM::VLD1d64QPseudoWB_fixed:
4164 case ARM::VLD4d8Pseudo_UPD:
4165 case ARM::VLD4d16Pseudo_UPD:
4166 case ARM::VLD4d32Pseudo_UPD:
4167 case ARM::VLD4q8Pseudo_UPD:
4168 case ARM::VLD4q16Pseudo_UPD:
4169 case ARM::VLD4q32Pseudo_UPD:
4170 case ARM::VLD4q8oddPseudo:
4171 case ARM::VLD4q16oddPseudo:
4172 case ARM::VLD4q32oddPseudo:
4173 case ARM::VLD4q8oddPseudo_UPD:
4174 case ARM::VLD4q16oddPseudo_UPD:
4175 case ARM::VLD4q32oddPseudo_UPD:
4176 case ARM::VLD1DUPq8:
4177 case ARM::VLD1DUPq16:
4178 case ARM::VLD1DUPq32:
4179 case ARM::VLD1DUPq8wb_fixed:
4180 case ARM::VLD1DUPq16wb_fixed:
4181 case ARM::VLD1DUPq32wb_fixed:
4182 case ARM::VLD1DUPq8wb_register:
4183 case ARM::VLD1DUPq16wb_register:
4184 case ARM::VLD1DUPq32wb_register:
4185 case ARM::VLD2DUPd8:
4186 case ARM::VLD2DUPd16:
4187 case ARM::VLD2DUPd32:
4188 case ARM::VLD2DUPd8wb_fixed:
4189 case ARM::VLD2DUPd16wb_fixed:
4190 case ARM::VLD2DUPd32wb_fixed:
4191 case ARM::VLD2DUPd8wb_register:
4192 case ARM::VLD2DUPd16wb_register:
4193 case ARM::VLD2DUPd32wb_register:
4194 case ARM::VLD4DUPd8Pseudo:
4195 case ARM::VLD4DUPd16Pseudo:
4196 case ARM::VLD4DUPd32Pseudo:
4197 case ARM::VLD4DUPd8Pseudo_UPD:
4198 case ARM::VLD4DUPd16Pseudo_UPD:
4199 case ARM::VLD4DUPd32Pseudo_UPD:
4200 case ARM::VLD1LNq8Pseudo:
4201 case ARM::VLD1LNq16Pseudo:
4202 case ARM::VLD1LNq32Pseudo:
4203 case ARM::VLD1LNq8Pseudo_UPD:
4204 case ARM::VLD1LNq16Pseudo_UPD:
4205 case ARM::VLD1LNq32Pseudo_UPD:
4206 case ARM::VLD2LNd8Pseudo:
4207 case ARM::VLD2LNd16Pseudo:
4208 case ARM::VLD2LNd32Pseudo:
4209 case ARM::VLD2LNq16Pseudo:
4210 case ARM::VLD2LNq32Pseudo:
4211 case ARM::VLD2LNd8Pseudo_UPD:
4212 case ARM::VLD2LNd16Pseudo_UPD:
4213 case ARM::VLD2LNd32Pseudo_UPD:
4214 case ARM::VLD2LNq16Pseudo_UPD:
4215 case ARM::VLD2LNq32Pseudo_UPD:
4216 case ARM::VLD4LNd8Pseudo:
4217 case ARM::VLD4LNd16Pseudo:
4218 case ARM::VLD4LNd32Pseudo:
4219 case ARM::VLD4LNq16Pseudo:
4220 case ARM::VLD4LNq32Pseudo:
4221 case ARM::VLD4LNd8Pseudo_UPD:
4222 case ARM::VLD4LNd16Pseudo_UPD:
4223 case ARM::VLD4LNd32Pseudo_UPD:
4224 case ARM::VLD4LNq16Pseudo_UPD:
4225 case ARM::VLD4LNq32Pseudo_UPD:
4226 // If the address is not 64-bit aligned, the latencies of these
4227 // instructions increases by one.
4235 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4236 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4243 const MCInstrDesc &MCID = MI.getDesc();
4245 if (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4246 !Subtarget.cheapPredicableCPSRDef())) {
4247 // When predicated, CPSR is an additional source operand for CPSR updating
4248 // instructions, this apparently increases their latencies.
4254 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4255 const MachineInstr &MI,
4256 unsigned *PredCost) const {
4257 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4261 // An instruction scheduler typically runs on unbundled instructions, however
4262 // other passes may query the latency of a bundled instruction.
4263 if (MI.isBundle()) {
4264 unsigned Latency = 0;
4265 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
4266 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
4267 while (++I != E && I->isInsideBundle()) {
4268 if (I->getOpcode() != ARM::t2IT)
4269 Latency += getInstrLatency(ItinData, *I, PredCost);
4274 const MCInstrDesc &MCID = MI.getDesc();
4275 if (PredCost && (MCID.isCall() || (MCID.hasImplicitDefOfPhysReg(ARM::CPSR) &&
4276 !Subtarget.cheapPredicableCPSRDef()))) {
4277 // When predicated, CPSR is an additional source operand for CPSR updating
4278 // instructions, this apparently increases their latencies.
4281 // Be sure to call getStageLatency for an empty itinerary in case it has a
4282 // valid MinLatency property.
4284 return MI.mayLoad() ? 3 : 1;
4286 unsigned Class = MCID.getSchedClass();
4288 // For instructions with variable uops, use uops as latency.
4289 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4290 return getNumMicroOps(ItinData, MI);
4292 // For the common case, fall back on the itinerary's latency.
4293 unsigned Latency = ItinData->getStageLatency(Class);
4295 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4297 MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlignment() : 0;
4298 int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign);
4299 if (Adj >= 0 || (int)Latency > -Adj) {
4300 return Latency + Adj;
4305 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4306 SDNode *Node) const {
4307 if (!Node->isMachineOpcode())
4310 if (!ItinData || ItinData->isEmpty())
4313 unsigned Opcode = Node->getMachineOpcode();
4316 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4323 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4324 const MachineRegisterInfo *MRI,
4325 const MachineInstr &DefMI,
4327 const MachineInstr &UseMI,
4328 unsigned UseIdx) const {
4329 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4330 unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4331 if (Subtarget.nonpipelinedVFP() &&
4332 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4335 // Hoist VFP / NEON instructions with 4 or higher latency.
4337 SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4340 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4341 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4344 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4345 const MachineInstr &DefMI,
4346 unsigned DefIdx) const {
4347 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4348 if (!ItinData || ItinData->isEmpty())
4351 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4352 if (DDomain == ARMII::DomainGeneral) {
4353 unsigned DefClass = DefMI.getDesc().getSchedClass();
4354 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4355 return (DefCycle != -1 && DefCycle <= 2);
4360 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4361 StringRef &ErrInfo) const {
4362 if (convertAddSubFlagsOpcode(MI.getOpcode())) {
4363 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4369 // LoadStackGuard has so far only been implemented for MachO. Different code
4370 // sequence is needed for other targets.
4371 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4372 unsigned LoadImmOpc,
4373 unsigned LoadOpc) const {
4374 assert(!Subtarget.isROPI() && !Subtarget.isRWPI() &&
4375 "ROPI/RWPI not currently supported with stack guard");
4377 MachineBasicBlock &MBB = *MI->getParent();
4378 DebugLoc DL = MI->getDebugLoc();
4379 unsigned Reg = MI->getOperand(0).getReg();
4380 const GlobalValue *GV =
4381 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4382 MachineInstrBuilder MIB;
4384 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4385 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4387 if (Subtarget.isGVIndirectSymbol(GV)) {
4388 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4389 MIB.addReg(Reg, RegState::Kill).addImm(0);
4390 auto Flags = MachineMemOperand::MOLoad |
4391 MachineMemOperand::MODereferenceable |
4392 MachineMemOperand::MOInvariant;
4393 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4394 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, 4);
4395 MIB.addMemOperand(MMO).add(predOps(ARMCC::AL));
4398 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4399 MIB.addReg(Reg, RegState::Kill)
4401 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end())
4402 .add(predOps(ARMCC::AL));
4406 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4407 unsigned &AddSubOpc,
4408 bool &NegAcc, bool &HasLane) const {
4409 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4410 if (I == MLxEntryMap.end())
4413 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4414 MulOpc = Entry.MulOpc;
4415 AddSubOpc = Entry.AddSubOpc;
4416 NegAcc = Entry.NegAcc;
4417 HasLane = Entry.HasLane;
4421 //===----------------------------------------------------------------------===//
4422 // Execution domains.
4423 //===----------------------------------------------------------------------===//
4425 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4426 // and some can go down both. The vmov instructions go down the VFP pipeline,
4427 // but they can be changed to vorr equivalents that are executed by the NEON
4430 // We use the following execution domain numbering:
4439 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4441 std::pair<uint16_t, uint16_t>
4442 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
4443 // If we don't have access to NEON instructions then we won't be able
4444 // to swizzle anything to the NEON domain. Check to make sure.
4445 if (Subtarget.hasNEON()) {
4446 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4447 // if they are not predicated.
4448 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI))
4449 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4451 // CortexA9 is particularly picky about mixing the two and wants these
4453 if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) &&
4454 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR ||
4455 MI.getOpcode() == ARM::VMOVS))
4456 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4458 // No other instructions can be swizzled, so just determine their domain.
4459 unsigned Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
4461 if (Domain & ARMII::DomainNEON)
4462 return std::make_pair(ExeNEON, 0);
4464 // Certain instructions can go either way on Cortex-A8.
4465 // Treat them as NEON instructions.
4466 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4467 return std::make_pair(ExeNEON, 0);
4469 if (Domain & ARMII::DomainVFP)
4470 return std::make_pair(ExeVFP, 0);
4472 return std::make_pair(ExeGeneric, 0);
4475 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4476 unsigned SReg, unsigned &Lane) {
4477 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4480 if (DReg != ARM::NoRegister)
4484 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4486 assert(DReg && "S-register with no D super-register?");
4490 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4491 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4492 /// zero if no register needs to be defined as implicit-use.
4494 /// If the function cannot determine if an SPR should be marked implicit use or
4495 /// not, it returns false.
4497 /// This function handles cases where an instruction is being modified from taking
4498 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4499 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4500 /// lane of the DPR).
4502 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4503 /// (including the case where the DPR itself is defined), it should not.
4505 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4506 MachineInstr &MI, unsigned DReg,
4507 unsigned Lane, unsigned &ImplicitSReg) {
4508 // If the DPR is defined or used already, the other SPR lane will be chained
4509 // correctly, so there is nothing to be done.
4510 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
4515 // Otherwise we need to go searching to see if the SPR is set explicitly.
4516 ImplicitSReg = TRI->getSubReg(DReg,
4517 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4518 MachineBasicBlock::LivenessQueryResult LQR =
4519 MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4521 if (LQR == MachineBasicBlock::LQR_Live)
4523 else if (LQR == MachineBasicBlock::LQR_Unknown)
4526 // If the register is known not to be live, there is no need to add an
4532 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
4533 unsigned Domain) const {
4534 unsigned DstReg, SrcReg, DReg;
4536 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4537 const TargetRegisterInfo *TRI = &getRegisterInfo();
4538 switch (MI.getOpcode()) {
4540 llvm_unreachable("cannot handle opcode!");
4543 if (Domain != ExeNEON)
4546 // Zap the predicate operands.
4547 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4549 // Make sure we've got NEON instructions.
4550 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4552 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4553 DstReg = MI.getOperand(0).getReg();
4554 SrcReg = MI.getOperand(1).getReg();
4556 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4557 MI.RemoveOperand(i - 1);
4559 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4560 MI.setDesc(get(ARM::VORRd));
4561 MIB.addReg(DstReg, RegState::Define)
4564 .add(predOps(ARMCC::AL));
4567 if (Domain != ExeNEON)
4569 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4571 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4572 DstReg = MI.getOperand(0).getReg();
4573 SrcReg = MI.getOperand(1).getReg();
4575 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4576 MI.RemoveOperand(i - 1);
4578 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4580 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4581 // Note that DSrc has been widened and the other lane may be undef, which
4582 // contaminates the entire register.
4583 MI.setDesc(get(ARM::VGETLNi32));
4584 MIB.addReg(DstReg, RegState::Define)
4585 .addReg(DReg, RegState::Undef)
4587 .add(predOps(ARMCC::AL));
4589 // The old source should be an implicit use, otherwise we might think it
4590 // was dead before here.
4591 MIB.addReg(SrcReg, RegState::Implicit);
4594 if (Domain != ExeNEON)
4596 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4598 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4599 DstReg = MI.getOperand(0).getReg();
4600 SrcReg = MI.getOperand(1).getReg();
4602 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4604 unsigned ImplicitSReg;
4605 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4608 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4609 MI.RemoveOperand(i - 1);
4611 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4612 // Again DDst may be undefined at the beginning of this instruction.
4613 MI.setDesc(get(ARM::VSETLNi32));
4614 MIB.addReg(DReg, RegState::Define)
4615 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
4618 .add(predOps(ARMCC::AL));
4620 // The narrower destination must be marked as set to keep previous chains
4622 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4623 if (ImplicitSReg != 0)
4624 MIB.addReg(ImplicitSReg, RegState::Implicit);
4628 if (Domain != ExeNEON)
4631 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4632 DstReg = MI.getOperand(0).getReg();
4633 SrcReg = MI.getOperand(1).getReg();
4635 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4636 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4637 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4639 unsigned ImplicitSReg;
4640 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4643 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4644 MI.RemoveOperand(i - 1);
4647 // Destination can be:
4648 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4649 MI.setDesc(get(ARM::VDUPLN32d));
4650 MIB.addReg(DDst, RegState::Define)
4651 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
4653 .add(predOps(ARMCC::AL));
4655 // Neither the source or the destination are naturally represented any
4656 // more, so add them in manually.
4657 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4658 MIB.addReg(SrcReg, RegState::Implicit);
4659 if (ImplicitSReg != 0)
4660 MIB.addReg(ImplicitSReg, RegState::Implicit);
4664 // In general there's no single instruction that can perform an S <-> S
4665 // move in NEON space, but a pair of VEXT instructions *can* do the
4666 // job. It turns out that the VEXTs needed will only use DSrc once, with
4667 // the position based purely on the combination of lane-0 and lane-1
4668 // involved. For example
4669 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4670 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4671 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4672 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4674 // Pattern of the MachineInstrs is:
4675 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4676 MachineInstrBuilder NewMIB;
4677 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
4680 // On the first instruction, both DSrc and DDst may be undef if present.
4681 // Specifically when the original instruction didn't have them as an
4683 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4684 bool CurUndef = !MI.readsRegister(CurReg, TRI);
4685 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4687 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4688 CurUndef = !MI.readsRegister(CurReg, TRI);
4689 NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
4691 .add(predOps(ARMCC::AL));
4693 if (SrcLane == DstLane)
4694 NewMIB.addReg(SrcReg, RegState::Implicit);
4696 MI.setDesc(get(ARM::VEXTd32));
4697 MIB.addReg(DDst, RegState::Define);
4699 // On the second instruction, DDst has definitely been defined above, so
4700 // it is not undef. DSrc, if present, can be undef as above.
4701 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4702 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4703 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4705 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4706 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4707 MIB.addReg(CurReg, getUndefRegState(CurUndef))
4709 .add(predOps(ARMCC::AL));
4711 if (SrcLane != DstLane)
4712 MIB.addReg(SrcReg, RegState::Implicit);
4714 // As before, the original destination is no longer represented, add it
4716 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4717 if (ImplicitSReg != 0)
4718 MIB.addReg(ImplicitSReg, RegState::Implicit);
4724 //===----------------------------------------------------------------------===//
4725 // Partial register updates
4726 //===----------------------------------------------------------------------===//
4728 // Swift renames NEON registers with 64-bit granularity. That means any
4729 // instruction writing an S-reg implicitly reads the containing D-reg. The
4730 // problem is mostly avoided by translating f32 operations to v2f32 operations
4731 // on D-registers, but f32 loads are still a problem.
4733 // These instructions can load an f32 into a NEON register:
4735 // VLDRS - Only writes S, partial D update.
4736 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4737 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4739 // FCONSTD can be used as a dependency-breaking instruction.
4740 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
4741 const MachineInstr &MI, unsigned OpNum,
4742 const TargetRegisterInfo *TRI) const {
4743 auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
4744 if (!PartialUpdateClearance)
4747 assert(TRI && "Need TRI instance");
4749 const MachineOperand &MO = MI.getOperand(OpNum);
4752 unsigned Reg = MO.getReg();
4755 switch (MI.getOpcode()) {
4756 // Normal instructions writing only an S-register.
4761 case ARM::VMOVv4i16:
4762 case ARM::VMOVv2i32:
4763 case ARM::VMOVv2f32:
4764 case ARM::VMOVv1i64:
4765 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI);
4768 // Explicitly reads the dependency.
4769 case ARM::VLD1LNd32:
4776 // If this instruction actually reads a value from Reg, there is no unwanted
4778 if (UseOp != -1 && MI.getOperand(UseOp).readsReg())
4781 // We must be able to clobber the whole D-reg.
4782 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4783 // Virtual register must be a def undef foo:ssub_0 operand.
4784 if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
4786 } else if (ARM::SPRRegClass.contains(Reg)) {
4787 // Physical register: MI must define the full D-reg.
4788 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4790 if (!DReg || !MI.definesRegister(DReg, TRI))
4794 // MI has an unwanted D-register dependency.
4795 // Avoid defs in the previous N instructrions.
4796 return PartialUpdateClearance;
4799 // Break a partial register dependency after getPartialRegUpdateClearance
4800 // returned non-zero.
4801 void ARMBaseInstrInfo::breakPartialRegDependency(
4802 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4803 assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
4804 assert(TRI && "Need TRI instance");
4806 const MachineOperand &MO = MI.getOperand(OpNum);
4807 unsigned Reg = MO.getReg();
4808 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4809 "Can't break virtual register dependencies.");
4810 unsigned DReg = Reg;
4812 // If MI defines an S-reg, find the corresponding D super-register.
4813 if (ARM::SPRRegClass.contains(Reg)) {
4814 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4815 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4818 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4819 assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4821 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4822 // the full D-register by loading the same value to both lanes. The
4823 // instruction is micro-coded with 2 uops, so don't do this until we can
4824 // properly schedule micro-coded instructions. The dispatcher stalls cause
4825 // too big regressions.
4827 // Insert the dependency-breaking FCONSTD before MI.
4828 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4829 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
4831 .add(predOps(ARMCC::AL));
4832 MI.addRegisterKilled(DReg, TRI, true);
4835 bool ARMBaseInstrInfo::hasNOP() const {
4836 return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4839 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4840 if (MI->getNumOperands() < 4)
4842 unsigned ShOpVal = MI->getOperand(3).getImm();
4843 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4844 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4845 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4846 ((ShImm == 1 || ShImm == 2) &&
4847 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4853 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4854 const MachineInstr &MI, unsigned DefIdx,
4855 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4856 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4857 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4859 switch (MI.getOpcode()) {
4861 // dX = VMOVDRR rY, rZ
4863 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4864 // Populate the InputRegs accordingly.
4866 const MachineOperand *MOReg = &MI.getOperand(1);
4867 InputRegs.push_back(
4868 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4870 MOReg = &MI.getOperand(2);
4871 InputRegs.push_back(
4872 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4875 llvm_unreachable("Target dependent opcode missing");
4878 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4879 const MachineInstr &MI, unsigned DefIdx,
4880 RegSubRegPairAndIdx &InputReg) const {
4881 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4882 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4884 switch (MI.getOpcode()) {
4886 // rX, rY = VMOVRRD dZ
4888 // rX = EXTRACT_SUBREG dZ, ssub_0
4889 // rY = EXTRACT_SUBREG dZ, ssub_1
4890 const MachineOperand &MOReg = MI.getOperand(2);
4891 InputReg.Reg = MOReg.getReg();
4892 InputReg.SubReg = MOReg.getSubReg();
4893 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4896 llvm_unreachable("Target dependent opcode missing");
4899 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4900 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4901 RegSubRegPairAndIdx &InsertedReg) const {
4902 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4903 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4905 switch (MI.getOpcode()) {
4906 case ARM::VSETLNi32:
4907 // dX = VSETLNi32 dY, rZ, imm
4908 const MachineOperand &MOBaseReg = MI.getOperand(1);
4909 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4910 const MachineOperand &MOIndex = MI.getOperand(3);
4911 BaseReg.Reg = MOBaseReg.getReg();
4912 BaseReg.SubReg = MOBaseReg.getSubReg();
4914 InsertedReg.Reg = MOInsertedReg.getReg();
4915 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4916 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4919 llvm_unreachable("Target dependent opcode missing");