1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMConstantPoolValue.h"
18 #include "ARMFeatures.h"
19 #include "ARMHazardRecognizer.h"
20 #include "ARMMachineFunctionInfo.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/LiveVariables.h"
24 #include "llvm/CodeGen/MachineConstantPool.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineJumpTableInfo.h"
28 #include "llvm/CodeGen/MachineMemOperand.h"
29 #include "llvm/CodeGen/MachineRegisterInfo.h"
30 #include "llvm/CodeGen/SelectionDAGNodes.h"
31 #include "llvm/CodeGen/TargetSchedule.h"
32 #include "llvm/IR/Constants.h"
33 #include "llvm/IR/Function.h"
34 #include "llvm/IR/GlobalValue.h"
35 #include "llvm/MC/MCAsmInfo.h"
36 #include "llvm/MC/MCExpr.h"
37 #include "llvm/Support/BranchProbability.h"
38 #include "llvm/Support/CommandLine.h"
39 #include "llvm/Support/Debug.h"
40 #include "llvm/Support/ErrorHandling.h"
41 #include "llvm/Support/raw_ostream.h"
45 #define DEBUG_TYPE "arm-instrinfo"
47 #define GET_INSTRINFO_CTOR_DTOR
48 #include "ARMGenInstrInfo.inc"
51 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
52 cl::desc("Enable ARM 2-addr to 3-addr conv"));
55 WidenVMOVS("widen-vmovs", cl::Hidden, cl::init(true),
56 cl::desc("Widen ARM vmovs to vmovd when possible"));
58 static cl::opt<unsigned>
59 SwiftPartialUpdateClearance("swift-partial-update-clearance",
60 cl::Hidden, cl::init(12),
61 cl::desc("Clearance before partial register updates"));
63 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
65 uint16_t MLxOpc; // MLA / MLS opcode
66 uint16_t MulOpc; // Expanded multiplication opcode
67 uint16_t AddSubOpc; // Expanded add / sub opcode
68 bool NegAcc; // True if the acc is negated before the add / sub.
69 bool HasLane; // True if instruction has an extra "lane" operand.
72 static const ARM_MLxEntry ARM_MLxTable[] = {
73 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
75 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
76 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
77 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
78 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
79 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
80 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
81 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
82 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
85 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
86 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
87 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
88 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
89 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
90 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
91 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
92 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
95 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
96 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
98 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
99 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
100 llvm_unreachable("Duplicated entries?");
101 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
102 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
106 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
107 // currently defaults to no prepass hazard recognizer.
108 ScheduleHazardRecognizer *
109 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
110 const ScheduleDAG *DAG) const {
111 if (usePreRAHazardRecognizer()) {
112 const InstrItineraryData *II =
113 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
114 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
116 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
119 ScheduleHazardRecognizer *ARMBaseInstrInfo::
120 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
121 const ScheduleDAG *DAG) const {
122 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
123 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
124 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
128 ARMBaseInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
129 MachineBasicBlock::iterator &MBBI,
130 LiveVariables *LV) const {
131 // FIXME: Thumb2 support.
136 MachineInstr *MI = MBBI;
137 MachineFunction &MF = *MI->getParent()->getParent();
138 uint64_t TSFlags = MI->getDesc().TSFlags;
140 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
141 default: return nullptr;
142 case ARMII::IndexModePre:
145 case ARMII::IndexModePost:
149 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
151 unsigned MemOpc = getUnindexedOpcode(MI->getOpcode());
155 MachineInstr *UpdateMI = nullptr;
156 MachineInstr *MemMI = nullptr;
157 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
158 const MCInstrDesc &MCID = MI->getDesc();
159 unsigned NumOps = MCID.getNumOperands();
160 bool isLoad = !MI->mayStore();
161 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0);
162 const MachineOperand &Base = MI->getOperand(2);
163 const MachineOperand &Offset = MI->getOperand(NumOps-3);
164 unsigned WBReg = WB.getReg();
165 unsigned BaseReg = Base.getReg();
166 unsigned OffReg = Offset.getReg();
167 unsigned OffImm = MI->getOperand(NumOps-2).getImm();
168 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm();
170 default: llvm_unreachable("Unknown indexed op!");
171 case ARMII::AddrMode2: {
172 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
173 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
175 if (ARM_AM::getSOImmVal(Amt) == -1)
176 // Can't encode it in a so_imm operand. This transformation will
177 // add more than 1 instruction. Abandon!
179 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
180 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
181 .addReg(BaseReg).addImm(Amt)
182 .addImm(Pred).addReg(0).addReg(0);
183 } else if (Amt != 0) {
184 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
185 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
186 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
187 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
188 .addReg(BaseReg).addReg(OffReg).addReg(0).addImm(SOOpc)
189 .addImm(Pred).addReg(0).addReg(0);
191 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
192 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
193 .addReg(BaseReg).addReg(OffReg)
194 .addImm(Pred).addReg(0).addReg(0);
197 case ARMII::AddrMode3 : {
198 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
199 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
201 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
202 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
203 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
204 .addReg(BaseReg).addImm(Amt)
205 .addImm(Pred).addReg(0).addReg(0);
207 UpdateMI = BuildMI(MF, MI->getDebugLoc(),
208 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
209 .addReg(BaseReg).addReg(OffReg)
210 .addImm(Pred).addReg(0).addReg(0);
215 std::vector<MachineInstr*> NewMIs;
218 MemMI = BuildMI(MF, MI->getDebugLoc(),
219 get(MemOpc), MI->getOperand(0).getReg())
220 .addReg(WBReg).addImm(0).addImm(Pred);
222 MemMI = BuildMI(MF, MI->getDebugLoc(),
223 get(MemOpc)).addReg(MI->getOperand(1).getReg())
224 .addReg(WBReg).addReg(0).addImm(0).addImm(Pred);
225 NewMIs.push_back(MemMI);
226 NewMIs.push_back(UpdateMI);
229 MemMI = BuildMI(MF, MI->getDebugLoc(),
230 get(MemOpc), MI->getOperand(0).getReg())
231 .addReg(BaseReg).addImm(0).addImm(Pred);
233 MemMI = BuildMI(MF, MI->getDebugLoc(),
234 get(MemOpc)).addReg(MI->getOperand(1).getReg())
235 .addReg(BaseReg).addReg(0).addImm(0).addImm(Pred);
237 UpdateMI->getOperand(0).setIsDead();
238 NewMIs.push_back(UpdateMI);
239 NewMIs.push_back(MemMI);
242 // Transfer LiveVariables states, kill / dead info.
244 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
245 MachineOperand &MO = MI->getOperand(i);
246 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
247 unsigned Reg = MO.getReg();
249 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
251 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
253 LV->addVirtualRegisterDead(Reg, NewMI);
255 if (MO.isUse() && MO.isKill()) {
256 for (unsigned j = 0; j < 2; ++j) {
257 // Look at the two new MI's in reverse order.
258 MachineInstr *NewMI = NewMIs[j];
259 if (!NewMI->readsRegister(Reg))
261 LV->addVirtualRegisterKilled(Reg, NewMI);
262 if (VI.removeKill(MI))
263 VI.Kills.push_back(NewMI);
271 MFI->insert(MBBI, NewMIs[1]);
272 MFI->insert(MBBI, NewMIs[0]);
278 ARMBaseInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
279 MachineBasicBlock *&FBB,
280 SmallVectorImpl<MachineOperand> &Cond,
281 bool AllowModify) const {
285 MachineBasicBlock::iterator I = MBB.end();
286 if (I == MBB.begin())
287 return false; // Empty blocks are easy.
290 // Walk backwards from the end of the basic block until the branch is
291 // analyzed or we give up.
292 while (isPredicated(I) || I->isTerminator() || I->isDebugValue()) {
294 // Flag to be raised on unanalyzeable instructions. This is useful in cases
295 // where we want to clean up on the end of the basic block before we bail
297 bool CantAnalyze = false;
299 // Skip over DEBUG values and predicated nonterminators.
300 while (I->isDebugValue() || !I->isTerminator()) {
301 if (I == MBB.begin())
306 if (isIndirectBranchOpcode(I->getOpcode()) ||
307 isJumpTableBranchOpcode(I->getOpcode())) {
308 // Indirect branches and jump tables can't be analyzed, but we still want
309 // to clean up any instructions at the tail of the basic block.
311 } else if (isUncondBranchOpcode(I->getOpcode())) {
312 TBB = I->getOperand(0).getMBB();
313 } else if (isCondBranchOpcode(I->getOpcode())) {
314 // Bail out if we encounter multiple conditional branches.
318 assert(!FBB && "FBB should have been null.");
320 TBB = I->getOperand(0).getMBB();
321 Cond.push_back(I->getOperand(1));
322 Cond.push_back(I->getOperand(2));
323 } else if (I->isReturn()) {
324 // Returns can't be analyzed, but we should run cleanup.
325 CantAnalyze = !isPredicated(I);
327 // We encountered other unrecognized terminator. Bail out immediately.
331 // Cleanup code - to be run for unpredicated unconditional branches and
333 if (!isPredicated(I) &&
334 (isUncondBranchOpcode(I->getOpcode()) ||
335 isIndirectBranchOpcode(I->getOpcode()) ||
336 isJumpTableBranchOpcode(I->getOpcode()) ||
338 // Forget any previous condition branch information - it no longer applies.
342 // If we can modify the function, delete everything below this
343 // unconditional branch.
345 MachineBasicBlock::iterator DI = std::next(I);
346 while (DI != MBB.end()) {
347 MachineInstr *InstToDelete = DI;
349 InstToDelete->eraseFromParent();
357 if (I == MBB.begin())
363 // We made it past the terminators without bailing out - we must have
364 // analyzed this branch successfully.
369 unsigned ARMBaseInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
370 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
374 if (!isUncondBranchOpcode(I->getOpcode()) &&
375 !isCondBranchOpcode(I->getOpcode()))
378 // Remove the branch.
379 I->eraseFromParent();
383 if (I == MBB.begin()) return 1;
385 if (!isCondBranchOpcode(I->getOpcode()))
388 // Remove the branch.
389 I->eraseFromParent();
394 ARMBaseInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
395 MachineBasicBlock *FBB,
396 ArrayRef<MachineOperand> Cond,
398 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
399 int BOpc = !AFI->isThumbFunction()
400 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
401 int BccOpc = !AFI->isThumbFunction()
402 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
403 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
405 // Shouldn't be a fall through.
406 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
407 assert((Cond.size() == 2 || Cond.size() == 0) &&
408 "ARM branch conditions have two components!");
410 // For conditional branches, we use addOperand to preserve CPSR flags.
413 if (Cond.empty()) { // Unconditional branch?
415 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).addImm(ARMCC::AL).addReg(0);
417 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
419 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
420 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
424 // Two-way conditional branch.
425 BuildMI(&MBB, DL, get(BccOpc)).addMBB(TBB)
426 .addImm(Cond[0].getImm()).addOperand(Cond[1]);
428 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).addImm(ARMCC::AL).addReg(0);
430 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
434 bool ARMBaseInstrInfo::
435 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
436 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
437 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
441 bool ARMBaseInstrInfo::isPredicated(const MachineInstr *MI) const {
442 if (MI->isBundle()) {
443 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
444 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
445 while (++I != E && I->isInsideBundle()) {
446 int PIdx = I->findFirstPredOperandIdx();
447 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
453 int PIdx = MI->findFirstPredOperandIdx();
454 return PIdx != -1 && MI->getOperand(PIdx).getImm() != ARMCC::AL;
457 bool ARMBaseInstrInfo::
458 PredicateInstruction(MachineInstr *MI, ArrayRef<MachineOperand> Pred) const {
459 unsigned Opc = MI->getOpcode();
460 if (isUncondBranchOpcode(Opc)) {
461 MI->setDesc(get(getMatchingCondBranchOpcode(Opc)));
462 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
463 .addImm(Pred[0].getImm())
464 .addReg(Pred[1].getReg());
468 int PIdx = MI->findFirstPredOperandIdx();
470 MachineOperand &PMO = MI->getOperand(PIdx);
471 PMO.setImm(Pred[0].getImm());
472 MI->getOperand(PIdx+1).setReg(Pred[1].getReg());
478 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
479 ArrayRef<MachineOperand> Pred2) const {
480 if (Pred1.size() > 2 || Pred2.size() > 2)
483 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
484 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
494 return CC2 == ARMCC::HI;
496 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
498 return CC2 == ARMCC::GT;
500 return CC2 == ARMCC::LT;
504 bool ARMBaseInstrInfo::DefinesPredicate(MachineInstr *MI,
505 std::vector<MachineOperand> &Pred) const {
507 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
508 const MachineOperand &MO = MI->getOperand(i);
509 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
510 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
519 static bool isCPSRDefined(const MachineInstr *MI) {
520 for (const auto &MO : MI->operands())
521 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
526 static bool isEligibleForITBlock(const MachineInstr *MI) {
527 switch (MI->getOpcode()) {
528 default: return true;
529 case ARM::tADC: // ADC (register) T1
530 case ARM::tADDi3: // ADD (immediate) T1
531 case ARM::tADDi8: // ADD (immediate) T2
532 case ARM::tADDrr: // ADD (register) T1
533 case ARM::tAND: // AND (register) T1
534 case ARM::tASRri: // ASR (immediate) T1
535 case ARM::tASRrr: // ASR (register) T1
536 case ARM::tBIC: // BIC (register) T1
537 case ARM::tEOR: // EOR (register) T1
538 case ARM::tLSLri: // LSL (immediate) T1
539 case ARM::tLSLrr: // LSL (register) T1
540 case ARM::tLSRri: // LSR (immediate) T1
541 case ARM::tLSRrr: // LSR (register) T1
542 case ARM::tMUL: // MUL T1
543 case ARM::tMVN: // MVN (register) T1
544 case ARM::tORR: // ORR (register) T1
545 case ARM::tROR: // ROR (register) T1
546 case ARM::tRSB: // RSB (immediate) T1
547 case ARM::tSBC: // SBC (register) T1
548 case ARM::tSUBi3: // SUB (immediate) T1
549 case ARM::tSUBi8: // SUB (immediate) T2
550 case ARM::tSUBrr: // SUB (register) T1
551 return !isCPSRDefined(MI);
555 /// isPredicable - Return true if the specified instruction can be predicated.
556 /// By default, this returns true for every instruction with a
557 /// PredicateOperand.
558 bool ARMBaseInstrInfo::isPredicable(MachineInstr *MI) const {
559 if (!MI->isPredicable())
562 if (!isEligibleForITBlock(MI))
565 ARMFunctionInfo *AFI =
566 MI->getParent()->getParent()->getInfo<ARMFunctionInfo>();
568 if (AFI->isThumb2Function()) {
569 if (getSubtarget().restrictIT())
570 return isV8EligibleForIT(MI);
571 } else { // non-Thumb
572 if ((MI->getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
580 template <> bool IsCPSRDead<MachineInstr>(MachineInstr *MI) {
581 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
582 const MachineOperand &MO = MI->getOperand(i);
583 if (!MO.isReg() || MO.isUndef() || MO.isUse())
585 if (MO.getReg() != ARM::CPSR)
590 // all definitions of CPSR are dead
595 /// GetInstSize - Return the size of the specified MachineInstr.
597 unsigned ARMBaseInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
598 const MachineBasicBlock &MBB = *MI->getParent();
599 const MachineFunction *MF = MBB.getParent();
600 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
602 const MCInstrDesc &MCID = MI->getDesc();
604 return MCID.getSize();
606 // If this machine instr is an inline asm, measure it.
607 if (MI->getOpcode() == ARM::INLINEASM)
608 return getInlineAsmLength(MI->getOperand(0).getSymbolName(), *MAI);
609 unsigned Opc = MI->getOpcode();
612 // pseudo-instruction sizes are zero.
614 case TargetOpcode::BUNDLE:
615 return getInstBundleLength(MI);
616 case ARM::MOVi16_ga_pcrel:
617 case ARM::MOVTi16_ga_pcrel:
618 case ARM::t2MOVi16_ga_pcrel:
619 case ARM::t2MOVTi16_ga_pcrel:
622 case ARM::t2MOVi32imm:
624 case ARM::CONSTPOOL_ENTRY:
625 case ARM::JUMPTABLE_INSTS:
626 case ARM::JUMPTABLE_ADDRS:
627 case ARM::JUMPTABLE_TBB:
628 case ARM::JUMPTABLE_TBH:
629 // If this machine instr is a constant pool entry, its size is recorded as
631 return MI->getOperand(2).getImm();
632 case ARM::Int_eh_sjlj_longjmp:
634 case ARM::tInt_eh_sjlj_longjmp:
636 case ARM::Int_eh_sjlj_setjmp:
637 case ARM::Int_eh_sjlj_setjmp_nofp:
639 case ARM::tInt_eh_sjlj_setjmp:
640 case ARM::t2Int_eh_sjlj_setjmp:
641 case ARM::t2Int_eh_sjlj_setjmp_nofp:
644 return MI->getOperand(1).getImm();
648 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr *MI) const {
650 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
651 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
652 while (++I != E && I->isInsideBundle()) {
653 assert(!I->isBundle() && "No nested bundle!");
654 Size += GetInstSizeInBytes(&*I);
659 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
660 MachineBasicBlock::iterator I,
661 unsigned DestReg, bool KillSrc,
662 const ARMSubtarget &Subtarget) const {
663 unsigned Opc = Subtarget.isThumb()
664 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
667 MachineInstrBuilder MIB =
668 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
670 // There is only 1 A/R class MRS instruction, and it always refers to
671 // APSR. However, there are lots of other possibilities on M-class cores.
672 if (Subtarget.isMClass())
677 MIB.addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
680 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
681 MachineBasicBlock::iterator I,
682 unsigned SrcReg, bool KillSrc,
683 const ARMSubtarget &Subtarget) const {
684 unsigned Opc = Subtarget.isThumb()
685 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
688 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
690 if (Subtarget.isMClass())
695 MIB.addReg(SrcReg, getKillRegState(KillSrc));
699 MIB.addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
702 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
703 MachineBasicBlock::iterator I, DebugLoc DL,
704 unsigned DestReg, unsigned SrcReg,
705 bool KillSrc) const {
706 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
707 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
709 if (GPRDest && GPRSrc) {
710 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
711 .addReg(SrcReg, getKillRegState(KillSrc))));
715 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
716 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
719 if (SPRDest && SPRSrc)
721 else if (GPRDest && SPRSrc)
723 else if (SPRDest && GPRSrc)
725 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
727 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
731 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
732 MIB.addReg(SrcReg, getKillRegState(KillSrc));
733 if (Opc == ARM::VORRq)
734 MIB.addReg(SrcReg, getKillRegState(KillSrc));
739 // Handle register classes that require multiple instructions.
740 unsigned BeginIdx = 0;
741 unsigned SubRegs = 0;
744 // Use VORRq when possible.
745 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
747 BeginIdx = ARM::qsub_0;
749 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
751 BeginIdx = ARM::qsub_0;
753 // Fall back to VMOVD.
754 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
756 BeginIdx = ARM::dsub_0;
758 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
760 BeginIdx = ARM::dsub_0;
762 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
764 BeginIdx = ARM::dsub_0;
766 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
767 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
768 BeginIdx = ARM::gsub_0;
770 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
772 BeginIdx = ARM::dsub_0;
775 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
777 BeginIdx = ARM::dsub_0;
780 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
782 BeginIdx = ARM::dsub_0;
785 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
787 BeginIdx = ARM::ssub_0;
789 } else if (SrcReg == ARM::CPSR) {
790 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
792 } else if (DestReg == ARM::CPSR) {
793 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
797 assert(Opc && "Impossible reg-to-reg copy");
799 const TargetRegisterInfo *TRI = &getRegisterInfo();
800 MachineInstrBuilder Mov;
802 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
803 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
804 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
808 SmallSet<unsigned, 4> DstRegs;
810 for (unsigned i = 0; i != SubRegs; ++i) {
811 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
812 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
813 assert(Dst && Src && "Bad sub-register");
815 assert(!DstRegs.count(Src) && "destructive vector copy");
818 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
819 // VORR takes two source operands.
820 if (Opc == ARM::VORRq)
822 Mov = AddDefaultPred(Mov);
824 if (Opc == ARM::MOVr)
825 Mov = AddDefaultCC(Mov);
827 // Add implicit super-register defs and kills to the last instruction.
828 Mov->addRegisterDefined(DestReg, TRI);
830 Mov->addRegisterKilled(SrcReg, TRI);
833 const MachineInstrBuilder &
834 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
835 unsigned SubIdx, unsigned State,
836 const TargetRegisterInfo *TRI) const {
838 return MIB.addReg(Reg, State);
840 if (TargetRegisterInfo::isPhysicalRegister(Reg))
841 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
842 return MIB.addReg(Reg, State, SubIdx);
845 void ARMBaseInstrInfo::
846 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
847 unsigned SrcReg, bool isKill, int FI,
848 const TargetRegisterClass *RC,
849 const TargetRegisterInfo *TRI) const {
851 if (I != MBB.end()) DL = I->getDebugLoc();
852 MachineFunction &MF = *MBB.getParent();
853 MachineFrameInfo &MFI = *MF.getFrameInfo();
854 unsigned Align = MFI.getObjectAlignment(FI);
856 MachineMemOperand *MMO = MF.getMachineMemOperand(
857 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
858 MFI.getObjectSize(FI), Align);
860 switch (RC->getSize()) {
862 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
863 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STRi12))
864 .addReg(SrcReg, getKillRegState(isKill))
865 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
866 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
867 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRS))
868 .addReg(SrcReg, getKillRegState(isKill))
869 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
871 llvm_unreachable("Unknown reg class!");
874 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
875 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTRD))
876 .addReg(SrcReg, getKillRegState(isKill))
877 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
878 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
879 if (Subtarget.hasV5TEOps()) {
880 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
881 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
882 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
883 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
887 // Fallback to STM instruction, which has existed since the dawn of
889 MachineInstrBuilder MIB =
890 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::STMIA))
891 .addFrameIndex(FI).addMemOperand(MMO));
892 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
893 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
896 llvm_unreachable("Unknown reg class!");
899 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
900 // Use aligned spills if the stack can be realigned.
901 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
902 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1q64))
903 .addFrameIndex(FI).addImm(16)
904 .addReg(SrcReg, getKillRegState(isKill))
905 .addMemOperand(MMO));
907 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
908 .addReg(SrcReg, getKillRegState(isKill))
910 .addMemOperand(MMO));
913 llvm_unreachable("Unknown reg class!");
916 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
917 // Use aligned spills if the stack can be realigned.
918 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
919 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
920 .addFrameIndex(FI).addImm(16)
921 .addReg(SrcReg, getKillRegState(isKill))
922 .addMemOperand(MMO));
924 MachineInstrBuilder MIB =
925 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
928 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
929 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
930 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
933 llvm_unreachable("Unknown reg class!");
936 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
937 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
938 // FIXME: It's possible to only store part of the QQ register if the
939 // spilled def has a sub-register index.
940 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
941 .addFrameIndex(FI).addImm(16)
942 .addReg(SrcReg, getKillRegState(isKill))
943 .addMemOperand(MMO));
945 MachineInstrBuilder MIB =
946 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
949 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
950 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
951 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
952 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
955 llvm_unreachable("Unknown reg class!");
958 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
959 MachineInstrBuilder MIB =
960 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
963 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
964 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
965 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
966 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
967 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
968 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
969 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
970 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
972 llvm_unreachable("Unknown reg class!");
975 llvm_unreachable("Unknown reg class!");
980 ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
981 int &FrameIndex) const {
982 switch (MI->getOpcode()) {
985 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
986 if (MI->getOperand(1).isFI() &&
987 MI->getOperand(2).isReg() &&
988 MI->getOperand(3).isImm() &&
989 MI->getOperand(2).getReg() == 0 &&
990 MI->getOperand(3).getImm() == 0) {
991 FrameIndex = MI->getOperand(1).getIndex();
992 return MI->getOperand(0).getReg();
1000 if (MI->getOperand(1).isFI() &&
1001 MI->getOperand(2).isImm() &&
1002 MI->getOperand(2).getImm() == 0) {
1003 FrameIndex = MI->getOperand(1).getIndex();
1004 return MI->getOperand(0).getReg();
1008 case ARM::VST1d64TPseudo:
1009 case ARM::VST1d64QPseudo:
1010 if (MI->getOperand(0).isFI() &&
1011 MI->getOperand(2).getSubReg() == 0) {
1012 FrameIndex = MI->getOperand(0).getIndex();
1013 return MI->getOperand(2).getReg();
1017 if (MI->getOperand(1).isFI() &&
1018 MI->getOperand(0).getSubReg() == 0) {
1019 FrameIndex = MI->getOperand(1).getIndex();
1020 return MI->getOperand(0).getReg();
1028 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
1029 int &FrameIndex) const {
1030 const MachineMemOperand *Dummy;
1031 return MI->mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1034 void ARMBaseInstrInfo::
1035 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1036 unsigned DestReg, int FI,
1037 const TargetRegisterClass *RC,
1038 const TargetRegisterInfo *TRI) const {
1040 if (I != MBB.end()) DL = I->getDebugLoc();
1041 MachineFunction &MF = *MBB.getParent();
1042 MachineFrameInfo &MFI = *MF.getFrameInfo();
1043 unsigned Align = MFI.getObjectAlignment(FI);
1044 MachineMemOperand *MMO = MF.getMachineMemOperand(
1045 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
1046 MFI.getObjectSize(FI), Align);
1048 switch (RC->getSize()) {
1050 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1051 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1052 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1054 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1055 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1056 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1058 llvm_unreachable("Unknown reg class!");
1061 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1062 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1063 .addFrameIndex(FI).addImm(0).addMemOperand(MMO));
1064 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1065 MachineInstrBuilder MIB;
1067 if (Subtarget.hasV5TEOps()) {
1068 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1069 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1070 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1071 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO);
1073 AddDefaultPred(MIB);
1075 // Fallback to LDM instruction, which has existed since the dawn of
1077 MIB = AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::LDMIA))
1078 .addFrameIndex(FI).addMemOperand(MMO));
1079 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1080 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1083 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1084 MIB.addReg(DestReg, RegState::ImplicitDefine);
1086 llvm_unreachable("Unknown reg class!");
1089 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1090 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1091 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1092 .addFrameIndex(FI).addImm(16)
1093 .addMemOperand(MMO));
1095 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1097 .addMemOperand(MMO));
1100 llvm_unreachable("Unknown reg class!");
1103 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1104 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1105 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1106 .addFrameIndex(FI).addImm(16)
1107 .addMemOperand(MMO));
1109 MachineInstrBuilder MIB =
1110 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1112 .addMemOperand(MMO));
1113 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1114 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1115 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1116 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1117 MIB.addReg(DestReg, RegState::ImplicitDefine);
1120 llvm_unreachable("Unknown reg class!");
1123 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1124 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1125 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1126 .addFrameIndex(FI).addImm(16)
1127 .addMemOperand(MMO));
1129 MachineInstrBuilder MIB =
1130 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1132 .addMemOperand(MMO);
1133 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1134 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1135 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1136 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1137 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1138 MIB.addReg(DestReg, RegState::ImplicitDefine);
1141 llvm_unreachable("Unknown reg class!");
1144 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1145 MachineInstrBuilder MIB =
1146 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1148 .addMemOperand(MMO);
1149 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1150 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1151 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1152 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1153 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1154 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1155 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1156 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1157 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1158 MIB.addReg(DestReg, RegState::ImplicitDefine);
1160 llvm_unreachable("Unknown reg class!");
1163 llvm_unreachable("Unknown regclass!");
1168 ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
1169 int &FrameIndex) const {
1170 switch (MI->getOpcode()) {
1173 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1174 if (MI->getOperand(1).isFI() &&
1175 MI->getOperand(2).isReg() &&
1176 MI->getOperand(3).isImm() &&
1177 MI->getOperand(2).getReg() == 0 &&
1178 MI->getOperand(3).getImm() == 0) {
1179 FrameIndex = MI->getOperand(1).getIndex();
1180 return MI->getOperand(0).getReg();
1188 if (MI->getOperand(1).isFI() &&
1189 MI->getOperand(2).isImm() &&
1190 MI->getOperand(2).getImm() == 0) {
1191 FrameIndex = MI->getOperand(1).getIndex();
1192 return MI->getOperand(0).getReg();
1196 case ARM::VLD1d64TPseudo:
1197 case ARM::VLD1d64QPseudo:
1198 if (MI->getOperand(1).isFI() &&
1199 MI->getOperand(0).getSubReg() == 0) {
1200 FrameIndex = MI->getOperand(1).getIndex();
1201 return MI->getOperand(0).getReg();
1205 if (MI->getOperand(1).isFI() &&
1206 MI->getOperand(0).getSubReg() == 0) {
1207 FrameIndex = MI->getOperand(1).getIndex();
1208 return MI->getOperand(0).getReg();
1216 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
1217 int &FrameIndex) const {
1218 const MachineMemOperand *Dummy;
1219 return MI->mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1222 /// \brief Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1223 /// depending on whether the result is used.
1224 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MBBI) const {
1225 bool isThumb1 = Subtarget.isThumb1Only();
1226 bool isThumb2 = Subtarget.isThumb2();
1227 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1229 MachineInstr *MI = MBBI;
1230 DebugLoc dl = MI->getDebugLoc();
1231 MachineBasicBlock *BB = MI->getParent();
1233 MachineInstrBuilder LDM, STM;
1234 if (isThumb1 || !MI->getOperand(1).isDead()) {
1235 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1236 : isThumb1 ? ARM::tLDMIA_UPD
1238 .addOperand(MI->getOperand(1));
1240 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1243 if (isThumb1 || !MI->getOperand(0).isDead()) {
1244 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1245 : isThumb1 ? ARM::tSTMIA_UPD
1247 .addOperand(MI->getOperand(0));
1249 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1252 AddDefaultPred(LDM.addOperand(MI->getOperand(3)));
1253 AddDefaultPred(STM.addOperand(MI->getOperand(2)));
1255 // Sort the scratch registers into ascending order.
1256 const TargetRegisterInfo &TRI = getRegisterInfo();
1257 llvm::SmallVector<unsigned, 6> ScratchRegs;
1258 for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1259 ScratchRegs.push_back(MI->getOperand(I).getReg());
1260 std::sort(ScratchRegs.begin(), ScratchRegs.end(),
1261 [&TRI](const unsigned &Reg1,
1262 const unsigned &Reg2) -> bool {
1263 return TRI.getEncodingValue(Reg1) <
1264 TRI.getEncodingValue(Reg2);
1267 for (const auto &Reg : ScratchRegs) {
1268 LDM.addReg(Reg, RegState::Define);
1269 STM.addReg(Reg, RegState::Kill);
1277 ARMBaseInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
1278 MachineFunction &MF = *MI->getParent()->getParent();
1279 Reloc::Model RM = MF.getTarget().getRelocationModel();
1281 if (MI->getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1282 assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1283 "LOAD_STACK_GUARD currently supported only for MachO.");
1284 expandLoadStackGuard(MI, RM);
1285 MI->getParent()->erase(MI);
1289 if (MI->getOpcode() == ARM::MEMCPY) {
1294 // This hook gets to expand COPY instructions before they become
1295 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1296 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1297 // changed into a VORR that can go down the NEON pipeline.
1298 if (!WidenVMOVS || !MI->isCopy() || Subtarget.isCortexA15() ||
1299 Subtarget.isFPOnlySP())
1302 // Look for a copy between even S-registers. That is where we keep floats
1303 // when using NEON v2f32 instructions for f32 arithmetic.
1304 unsigned DstRegS = MI->getOperand(0).getReg();
1305 unsigned SrcRegS = MI->getOperand(1).getReg();
1306 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1309 const TargetRegisterInfo *TRI = &getRegisterInfo();
1310 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1312 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1314 if (!DstRegD || !SrcRegD)
1317 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1318 // legal if the COPY already defines the full DstRegD, and it isn't a
1319 // sub-register insertion.
1320 if (!MI->definesRegister(DstRegD, TRI) || MI->readsRegister(DstRegD, TRI))
1323 // A dead copy shouldn't show up here, but reject it just in case.
1324 if (MI->getOperand(0).isDead())
1327 // All clear, widen the COPY.
1328 DEBUG(dbgs() << "widening: " << *MI);
1329 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
1331 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1332 // or some other super-register.
1333 int ImpDefIdx = MI->findRegisterDefOperandIdx(DstRegD);
1334 if (ImpDefIdx != -1)
1335 MI->RemoveOperand(ImpDefIdx);
1337 // Change the opcode and operands.
1338 MI->setDesc(get(ARM::VMOVD));
1339 MI->getOperand(0).setReg(DstRegD);
1340 MI->getOperand(1).setReg(SrcRegD);
1341 AddDefaultPred(MIB);
1343 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1344 // register scavenger and machine verifier, so we need to indicate that we
1345 // are reading an undefined value from SrcRegD, but a proper value from
1347 MI->getOperand(1).setIsUndef();
1348 MIB.addReg(SrcRegS, RegState::Implicit);
1350 // SrcRegD may actually contain an unrelated value in the ssub_1
1351 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1352 if (MI->getOperand(1).isKill()) {
1353 MI->getOperand(1).setIsKill(false);
1354 MI->addRegisterKilled(SrcRegS, TRI, true);
1357 DEBUG(dbgs() << "replaced by: " << *MI);
1361 /// Create a copy of a const pool value. Update CPI to the new index and return
1363 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1364 MachineConstantPool *MCP = MF.getConstantPool();
1365 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1367 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1368 assert(MCPE.isMachineConstantPoolEntry() &&
1369 "Expecting a machine constantpool entry!");
1370 ARMConstantPoolValue *ACPV =
1371 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1373 unsigned PCLabelId = AFI->createPICLabelUId();
1374 ARMConstantPoolValue *NewCPV = nullptr;
1376 // FIXME: The below assumes PIC relocation model and that the function
1377 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1378 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1379 // instructions, so that's probably OK, but is PIC always correct when
1381 if (ACPV->isGlobalValue())
1382 NewCPV = ARMConstantPoolConstant::Create(
1383 cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1384 4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1385 else if (ACPV->isExtSymbol())
1386 NewCPV = ARMConstantPoolSymbol::
1387 Create(MF.getFunction()->getContext(),
1388 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1389 else if (ACPV->isBlockAddress())
1390 NewCPV = ARMConstantPoolConstant::
1391 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1392 ARMCP::CPBlockAddress, 4);
1393 else if (ACPV->isLSDA())
1394 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1396 else if (ACPV->isMachineBasicBlock())
1397 NewCPV = ARMConstantPoolMBB::
1398 Create(MF.getFunction()->getContext(),
1399 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1401 llvm_unreachable("Unexpected ARM constantpool value type!!");
1402 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1406 void ARMBaseInstrInfo::
1407 reMaterialize(MachineBasicBlock &MBB,
1408 MachineBasicBlock::iterator I,
1409 unsigned DestReg, unsigned SubIdx,
1410 const MachineInstr *Orig,
1411 const TargetRegisterInfo &TRI) const {
1412 unsigned Opcode = Orig->getOpcode();
1415 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
1416 MI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
1420 case ARM::tLDRpci_pic:
1421 case ARM::t2LDRpci_pic: {
1422 MachineFunction &MF = *MBB.getParent();
1423 unsigned CPI = Orig->getOperand(1).getIndex();
1424 unsigned PCLabelId = duplicateCPV(MF, CPI);
1425 MachineInstrBuilder MIB = BuildMI(MBB, I, Orig->getDebugLoc(), get(Opcode),
1427 .addConstantPoolIndex(CPI).addImm(PCLabelId);
1428 MIB->setMemRefs(Orig->memoperands_begin(), Orig->memoperands_end());
1435 ARMBaseInstrInfo::duplicate(MachineInstr *Orig, MachineFunction &MF) const {
1436 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1437 switch(Orig->getOpcode()) {
1438 case ARM::tLDRpci_pic:
1439 case ARM::t2LDRpci_pic: {
1440 unsigned CPI = Orig->getOperand(1).getIndex();
1441 unsigned PCLabelId = duplicateCPV(MF, CPI);
1442 Orig->getOperand(1).setIndex(CPI);
1443 Orig->getOperand(2).setImm(PCLabelId);
1450 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr *MI0,
1451 const MachineInstr *MI1,
1452 const MachineRegisterInfo *MRI) const {
1453 unsigned Opcode = MI0->getOpcode();
1454 if (Opcode == ARM::t2LDRpci ||
1455 Opcode == ARM::t2LDRpci_pic ||
1456 Opcode == ARM::tLDRpci ||
1457 Opcode == ARM::tLDRpci_pic ||
1458 Opcode == ARM::LDRLIT_ga_pcrel ||
1459 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1460 Opcode == ARM::tLDRLIT_ga_pcrel ||
1461 Opcode == ARM::MOV_ga_pcrel ||
1462 Opcode == ARM::MOV_ga_pcrel_ldr ||
1463 Opcode == ARM::t2MOV_ga_pcrel) {
1464 if (MI1->getOpcode() != Opcode)
1466 if (MI0->getNumOperands() != MI1->getNumOperands())
1469 const MachineOperand &MO0 = MI0->getOperand(1);
1470 const MachineOperand &MO1 = MI1->getOperand(1);
1471 if (MO0.getOffset() != MO1.getOffset())
1474 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1475 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1476 Opcode == ARM::tLDRLIT_ga_pcrel ||
1477 Opcode == ARM::MOV_ga_pcrel ||
1478 Opcode == ARM::MOV_ga_pcrel_ldr ||
1479 Opcode == ARM::t2MOV_ga_pcrel)
1480 // Ignore the PC labels.
1481 return MO0.getGlobal() == MO1.getGlobal();
1483 const MachineFunction *MF = MI0->getParent()->getParent();
1484 const MachineConstantPool *MCP = MF->getConstantPool();
1485 int CPI0 = MO0.getIndex();
1486 int CPI1 = MO1.getIndex();
1487 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1488 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1489 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1490 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1491 if (isARMCP0 && isARMCP1) {
1492 ARMConstantPoolValue *ACPV0 =
1493 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1494 ARMConstantPoolValue *ACPV1 =
1495 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1496 return ACPV0->hasSameValue(ACPV1);
1497 } else if (!isARMCP0 && !isARMCP1) {
1498 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1501 } else if (Opcode == ARM::PICLDR) {
1502 if (MI1->getOpcode() != Opcode)
1504 if (MI0->getNumOperands() != MI1->getNumOperands())
1507 unsigned Addr0 = MI0->getOperand(1).getReg();
1508 unsigned Addr1 = MI1->getOperand(1).getReg();
1509 if (Addr0 != Addr1) {
1511 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1512 !TargetRegisterInfo::isVirtualRegister(Addr1))
1515 // This assumes SSA form.
1516 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1517 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1518 // Check if the loaded value, e.g. a constantpool of a global address, are
1520 if (!produceSameValue(Def0, Def1, MRI))
1524 for (unsigned i = 3, e = MI0->getNumOperands(); i != e; ++i) {
1525 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1526 const MachineOperand &MO0 = MI0->getOperand(i);
1527 const MachineOperand &MO1 = MI1->getOperand(i);
1528 if (!MO0.isIdenticalTo(MO1))
1534 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1537 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1538 /// determine if two loads are loading from the same base address. It should
1539 /// only return true if the base pointers are the same and the only differences
1540 /// between the two addresses is the offset. It also returns the offsets by
1543 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1544 /// is permanently disabled.
1545 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1547 int64_t &Offset2) const {
1548 // Don't worry about Thumb: just ARM and Thumb2.
1549 if (Subtarget.isThumb1Only()) return false;
1551 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1554 switch (Load1->getMachineOpcode()) {
1568 case ARM::t2LDRSHi8:
1570 case ARM::t2LDRBi12:
1571 case ARM::t2LDRSHi12:
1575 switch (Load2->getMachineOpcode()) {
1588 case ARM::t2LDRSHi8:
1590 case ARM::t2LDRBi12:
1591 case ARM::t2LDRSHi12:
1595 // Check if base addresses and chain operands match.
1596 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1597 Load1->getOperand(4) != Load2->getOperand(4))
1600 // Index should be Reg0.
1601 if (Load1->getOperand(3) != Load2->getOperand(3))
1604 // Determine the offsets.
1605 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1606 isa<ConstantSDNode>(Load2->getOperand(1))) {
1607 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1608 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1615 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1616 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1617 /// be scheduled togther. On some targets if two loads are loading from
1618 /// addresses in the same cache line, it's better if they are scheduled
1619 /// together. This function takes two integers that represent the load offsets
1620 /// from the common base address. It returns true if it decides it's desirable
1621 /// to schedule the two loads together. "NumLoads" is the number of loads that
1622 /// have already been scheduled after Load1.
1624 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1625 /// is permanently disabled.
1626 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1627 int64_t Offset1, int64_t Offset2,
1628 unsigned NumLoads) const {
1629 // Don't worry about Thumb: just ARM and Thumb2.
1630 if (Subtarget.isThumb1Only()) return false;
1632 assert(Offset2 > Offset1);
1634 if ((Offset2 - Offset1) / 8 > 64)
1637 // Check if the machine opcodes are different. If they are different
1638 // then we consider them to not be of the same base address,
1639 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1640 // In this case, they are considered to be the same because they are different
1641 // encoding forms of the same basic instruction.
1642 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1643 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1644 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1645 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1646 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1647 return false; // FIXME: overly conservative?
1649 // Four loads in a row should be sufficient.
1656 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
1657 const MachineBasicBlock *MBB,
1658 const MachineFunction &MF) const {
1659 // Debug info is never a scheduling boundary. It's necessary to be explicit
1660 // due to the special treatment of IT instructions below, otherwise a
1661 // dbg_value followed by an IT will result in the IT instruction being
1662 // considered a scheduling hazard, which is wrong. It should be the actual
1663 // instruction preceding the dbg_value instruction(s), just like it is
1664 // when debug info is not present.
1665 if (MI->isDebugValue())
1668 // Terminators and labels can't be scheduled around.
1669 if (MI->isTerminator() || MI->isPosition())
1672 // Treat the start of the IT block as a scheduling boundary, but schedule
1673 // t2IT along with all instructions following it.
1674 // FIXME: This is a big hammer. But the alternative is to add all potential
1675 // true and anti dependencies to IT block instructions as implicit operands
1676 // to the t2IT instruction. The added compile time and complexity does not
1678 MachineBasicBlock::const_iterator I = MI;
1679 // Make sure to skip any dbg_value instructions
1680 while (++I != MBB->end() && I->isDebugValue())
1682 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1685 // Don't attempt to schedule around any instruction that defines
1686 // a stack-oriented pointer, as it's unlikely to be profitable. This
1687 // saves compile time, because it doesn't require every single
1688 // stack slot reference to depend on the instruction that does the
1690 // Calls don't actually change the stack pointer, even if they have imp-defs.
1691 // No ARM calling conventions change the stack pointer. (X86 calling
1692 // conventions sometimes do).
1693 if (!MI->isCall() && MI->definesRegister(ARM::SP))
1699 bool ARMBaseInstrInfo::
1700 isProfitableToIfCvt(MachineBasicBlock &MBB,
1701 unsigned NumCycles, unsigned ExtraPredCycles,
1702 BranchProbability Probability) const {
1706 // If we are optimizing for size, see if the branch in the predecessor can be
1707 // lowered to cbn?z by the constant island lowering pass, and return false if
1708 // so. This results in a shorter instruction sequence.
1709 if (MBB.getParent()->getFunction()->optForSize()) {
1710 MachineBasicBlock *Pred = *MBB.pred_begin();
1711 if (!Pred->empty()) {
1712 MachineInstr *LastMI = &*Pred->rbegin();
1713 if (LastMI->getOpcode() == ARM::t2Bcc) {
1714 MachineBasicBlock::iterator CmpMI = LastMI;
1715 if (CmpMI != Pred->begin()) {
1717 if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1718 CmpMI->getOpcode() == ARM::t2CMPri) {
1719 unsigned Reg = CmpMI->getOperand(0).getReg();
1720 unsigned PredReg = 0;
1721 ARMCC::CondCodes P = getInstrPredicate(CmpMI, PredReg);
1722 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1723 isARMLowRegister(Reg))
1731 // Attempt to estimate the relative costs of predication versus branching.
1732 // Here we scale up each component of UnpredCost to avoid precision issue when
1733 // scaling NumCycles by Probability.
1734 const unsigned ScalingUpFactor = 1024;
1735 unsigned UnpredCost = Probability.scale(NumCycles * ScalingUpFactor);
1736 UnpredCost += ScalingUpFactor; // The branch itself
1737 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1739 return (NumCycles + ExtraPredCycles) * ScalingUpFactor <= UnpredCost;
1742 bool ARMBaseInstrInfo::
1743 isProfitableToIfCvt(MachineBasicBlock &TMBB,
1744 unsigned TCycles, unsigned TExtra,
1745 MachineBasicBlock &FMBB,
1746 unsigned FCycles, unsigned FExtra,
1747 BranchProbability Probability) const {
1748 if (!TCycles || !FCycles)
1751 // Attempt to estimate the relative costs of predication versus branching.
1752 // Here we scale up each component of UnpredCost to avoid precision issue when
1753 // scaling TCycles/FCycles by Probability.
1754 const unsigned ScalingUpFactor = 1024;
1755 unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
1756 unsigned FUnpredCost =
1757 Probability.getCompl().scale(FCycles * ScalingUpFactor);
1758 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1759 UnpredCost += 1 * ScalingUpFactor; // The branch itself
1760 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1762 return (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor <= UnpredCost;
1766 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1767 MachineBasicBlock &FMBB) const {
1768 // Reduce false anti-dependencies to let Swift's out-of-order execution
1769 // engine do its thing.
1770 return Subtarget.isSwift();
1773 /// getInstrPredicate - If instruction is predicated, returns its predicate
1774 /// condition, otherwise returns AL. It also returns the condition code
1775 /// register by reference.
1777 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) {
1778 int PIdx = MI->findFirstPredOperandIdx();
1784 PredReg = MI->getOperand(PIdx+1).getReg();
1785 return (ARMCC::CondCodes)MI->getOperand(PIdx).getImm();
1789 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1794 if (Opc == ARM::t2B)
1797 llvm_unreachable("Unknown unconditional branch opcode!");
1800 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr *MI,
1803 unsigned OpIdx2) const {
1804 switch (MI->getOpcode()) {
1806 case ARM::t2MOVCCr: {
1807 // MOVCC can be commuted by inverting the condition.
1808 unsigned PredReg = 0;
1809 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1810 // MOVCC AL can't be inverted. Shouldn't happen.
1811 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1813 MI = TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1816 // After swapping the MOVCC operands, also invert the condition.
1817 MI->getOperand(MI->findFirstPredOperandIdx())
1818 .setImm(ARMCC::getOppositeCondition(CC));
1822 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1825 /// Identify instructions that can be folded into a MOVCC instruction, and
1826 /// return the defining instruction.
1827 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1828 const MachineRegisterInfo &MRI,
1829 const TargetInstrInfo *TII) {
1830 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1832 if (!MRI.hasOneNonDBGUse(Reg))
1834 MachineInstr *MI = MRI.getVRegDef(Reg);
1837 // MI is folded into the MOVCC by predicating it.
1838 if (!MI->isPredicable())
1840 // Check if MI has any non-dead defs or physreg uses. This also detects
1841 // predicated instructions which will be reading CPSR.
1842 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1843 const MachineOperand &MO = MI->getOperand(i);
1844 // Reject frame index operands, PEI can't handle the predicated pseudos.
1845 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1849 // MI can't have any tied operands, that would conflict with predication.
1852 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1854 if (MO.isDef() && !MO.isDead())
1857 bool DontMoveAcrossStores = true;
1858 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1863 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr *MI,
1864 SmallVectorImpl<MachineOperand> &Cond,
1865 unsigned &TrueOp, unsigned &FalseOp,
1866 bool &Optimizable) const {
1867 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1868 "Unknown select instruction");
1873 // 3: Condition code.
1877 Cond.push_back(MI->getOperand(3));
1878 Cond.push_back(MI->getOperand(4));
1879 // We can always fold a def.
1885 ARMBaseInstrInfo::optimizeSelect(MachineInstr *MI,
1886 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1887 bool PreferFalse) const {
1888 assert((MI->getOpcode() == ARM::MOVCCr || MI->getOpcode() == ARM::t2MOVCCr) &&
1889 "Unknown select instruction");
1890 MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
1891 MachineInstr *DefMI = canFoldIntoMOVCC(MI->getOperand(2).getReg(), MRI, this);
1892 bool Invert = !DefMI;
1894 DefMI = canFoldIntoMOVCC(MI->getOperand(1).getReg(), MRI, this);
1898 // Find new register class to use.
1899 MachineOperand FalseReg = MI->getOperand(Invert ? 2 : 1);
1900 unsigned DestReg = MI->getOperand(0).getReg();
1901 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1902 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1905 // Create a new predicated version of DefMI.
1906 // Rfalse is the first use.
1907 MachineInstrBuilder NewMI = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
1908 DefMI->getDesc(), DestReg);
1910 // Copy all the DefMI operands, excluding its (null) predicate.
1911 const MCInstrDesc &DefDesc = DefMI->getDesc();
1912 for (unsigned i = 1, e = DefDesc.getNumOperands();
1913 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1914 NewMI.addOperand(DefMI->getOperand(i));
1916 unsigned CondCode = MI->getOperand(3).getImm();
1918 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1920 NewMI.addImm(CondCode);
1921 NewMI.addOperand(MI->getOperand(4));
1923 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1924 if (NewMI->hasOptionalDef())
1925 AddDefaultCC(NewMI);
1927 // The output register value when the predicate is false is an implicit
1928 // register operand tied to the first def.
1929 // The tie makes the register allocator ensure the FalseReg is allocated the
1930 // same register as operand 0.
1931 FalseReg.setImplicit();
1932 NewMI.addOperand(FalseReg);
1933 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1935 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1936 SeenMIs.insert(NewMI);
1937 SeenMIs.erase(DefMI);
1939 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1940 // DefMI would be invalid when tranferred inside the loop. Checking for a
1941 // loop is expensive, but at least remove kill flags if they are in different
1943 if (DefMI->getParent() != MI->getParent())
1944 NewMI->clearKillInfo();
1946 // The caller will erase MI, but not DefMI.
1947 DefMI->eraseFromParent();
1951 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
1952 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
1955 /// This will go away once we can teach tblgen how to set the optional CPSR def
1957 struct AddSubFlagsOpcodePair {
1959 uint16_t MachineOpc;
1962 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
1963 {ARM::ADDSri, ARM::ADDri},
1964 {ARM::ADDSrr, ARM::ADDrr},
1965 {ARM::ADDSrsi, ARM::ADDrsi},
1966 {ARM::ADDSrsr, ARM::ADDrsr},
1968 {ARM::SUBSri, ARM::SUBri},
1969 {ARM::SUBSrr, ARM::SUBrr},
1970 {ARM::SUBSrsi, ARM::SUBrsi},
1971 {ARM::SUBSrsr, ARM::SUBrsr},
1973 {ARM::RSBSri, ARM::RSBri},
1974 {ARM::RSBSrsi, ARM::RSBrsi},
1975 {ARM::RSBSrsr, ARM::RSBrsr},
1977 {ARM::t2ADDSri, ARM::t2ADDri},
1978 {ARM::t2ADDSrr, ARM::t2ADDrr},
1979 {ARM::t2ADDSrs, ARM::t2ADDrs},
1981 {ARM::t2SUBSri, ARM::t2SUBri},
1982 {ARM::t2SUBSrr, ARM::t2SUBrr},
1983 {ARM::t2SUBSrs, ARM::t2SUBrs},
1985 {ARM::t2RSBSri, ARM::t2RSBri},
1986 {ARM::t2RSBSrs, ARM::t2RSBrs},
1989 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
1990 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
1991 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
1992 return AddSubFlagsOpcodeMap[i].MachineOpc;
1996 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
1997 MachineBasicBlock::iterator &MBBI, DebugLoc dl,
1998 unsigned DestReg, unsigned BaseReg, int NumBytes,
1999 ARMCC::CondCodes Pred, unsigned PredReg,
2000 const ARMBaseInstrInfo &TII, unsigned MIFlags) {
2001 if (NumBytes == 0 && DestReg != BaseReg) {
2002 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2003 .addReg(BaseReg, RegState::Kill)
2004 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
2005 .setMIFlags(MIFlags);
2009 bool isSub = NumBytes < 0;
2010 if (isSub) NumBytes = -NumBytes;
2013 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2014 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2015 assert(ThisVal && "Didn't extract field correctly");
2017 // We will handle these bits from offset, clear them.
2018 NumBytes &= ~ThisVal;
2020 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2022 // Build the new ADD / SUB.
2023 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2024 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2025 .addReg(BaseReg, RegState::Kill).addImm(ThisVal)
2026 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
2027 .setMIFlags(MIFlags);
2032 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
2033 MachineFunction &MF, MachineInstr *MI,
2034 unsigned NumBytes) {
2035 // This optimisation potentially adds lots of load and store
2036 // micro-operations, it's only really a great benefit to code-size.
2037 if (!MF.getFunction()->optForMinSize())
2040 // If only one register is pushed/popped, LLVM can use an LDR/STR
2041 // instead. We can't modify those so make sure we're dealing with an
2042 // instruction we understand.
2043 bool IsPop = isPopOpcode(MI->getOpcode());
2044 bool IsPush = isPushOpcode(MI->getOpcode());
2045 if (!IsPush && !IsPop)
2048 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2049 MI->getOpcode() == ARM::VLDMDIA_UPD;
2050 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2051 MI->getOpcode() == ARM::tPOP ||
2052 MI->getOpcode() == ARM::tPOP_RET;
2054 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2055 MI->getOperand(1).getReg() == ARM::SP)) &&
2056 "trying to fold sp update into non-sp-updating push/pop");
2058 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2059 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2060 // if this is violated.
2061 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2064 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2065 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2066 int RegListIdx = IsT1PushPop ? 2 : 4;
2068 // Calculate the space we'll need in terms of registers.
2069 unsigned FirstReg = MI->getOperand(RegListIdx).getReg();
2070 unsigned RD0Reg, RegsNeeded;
2073 RegsNeeded = NumBytes / 8;
2076 RegsNeeded = NumBytes / 4;
2079 // We're going to have to strip all list operands off before
2080 // re-adding them since the order matters, so save the existing ones
2082 SmallVector<MachineOperand, 4> RegList;
2083 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2084 RegList.push_back(MI->getOperand(i));
2086 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2087 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2089 // Now try to find enough space in the reglist to allocate NumBytes.
2090 for (unsigned CurReg = FirstReg - 1; CurReg >= RD0Reg && RegsNeeded;
2093 // Pushing any register is completely harmless, mark the
2094 // register involved as undef since we don't care about it in
2096 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2097 false, false, true));
2102 // However, we can only pop an extra register if it's not live. For
2103 // registers live within the function we might clobber a return value
2104 // register; the other way a register can be live here is if it's
2106 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2107 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2108 MachineBasicBlock::LQR_Dead) {
2109 // VFP pops don't allow holes in the register list, so any skip is fatal
2110 // for our transformation. GPR pops do, so we should just keep looking.
2117 // Mark the unimportant registers as <def,dead> in the POP.
2118 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2126 // Finally we know we can profitably perform the optimisation so go
2127 // ahead: strip all existing registers off and add them back again
2128 // in the right order.
2129 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2130 MI->RemoveOperand(i);
2132 // Add the complete list back in.
2133 MachineInstrBuilder MIB(MF, &*MI);
2134 for (int i = RegList.size() - 1; i >= 0; --i)
2135 MIB.addOperand(RegList[i]);
2140 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2141 unsigned FrameReg, int &Offset,
2142 const ARMBaseInstrInfo &TII) {
2143 unsigned Opcode = MI.getOpcode();
2144 const MCInstrDesc &Desc = MI.getDesc();
2145 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2148 // Memory operands in inline assembly always use AddrMode2.
2149 if (Opcode == ARM::INLINEASM)
2150 AddrMode = ARMII::AddrMode2;
2152 if (Opcode == ARM::ADDri) {
2153 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2155 // Turn it into a move.
2156 MI.setDesc(TII.get(ARM::MOVr));
2157 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2158 MI.RemoveOperand(FrameRegIdx+1);
2161 } else if (Offset < 0) {
2164 MI.setDesc(TII.get(ARM::SUBri));
2167 // Common case: small offset, fits into instruction.
2168 if (ARM_AM::getSOImmVal(Offset) != -1) {
2169 // Replace the FrameIndex with sp / fp
2170 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2171 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2176 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2178 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2179 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2181 // We will handle these bits from offset, clear them.
2182 Offset &= ~ThisImmVal;
2184 // Get the properly encoded SOImmVal field.
2185 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2186 "Bit extraction didn't work?");
2187 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2189 unsigned ImmIdx = 0;
2191 unsigned NumBits = 0;
2194 case ARMII::AddrMode_i12: {
2195 ImmIdx = FrameRegIdx + 1;
2196 InstrOffs = MI.getOperand(ImmIdx).getImm();
2200 case ARMII::AddrMode2: {
2201 ImmIdx = FrameRegIdx+2;
2202 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2203 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2208 case ARMII::AddrMode3: {
2209 ImmIdx = FrameRegIdx+2;
2210 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2211 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2216 case ARMII::AddrMode4:
2217 case ARMII::AddrMode6:
2218 // Can't fold any offset even if it's zero.
2220 case ARMII::AddrMode5: {
2221 ImmIdx = FrameRegIdx+1;
2222 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2223 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2230 llvm_unreachable("Unsupported addressing mode!");
2233 Offset += InstrOffs * Scale;
2234 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2240 // Attempt to fold address comp. if opcode has offset bits
2242 // Common case: small offset, fits into instruction.
2243 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2244 int ImmedOffset = Offset / Scale;
2245 unsigned Mask = (1 << NumBits) - 1;
2246 if ((unsigned)Offset <= Mask * Scale) {
2247 // Replace the FrameIndex with sp
2248 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2249 // FIXME: When addrmode2 goes away, this will simplify (like the
2250 // T2 version), as the LDR.i12 versions don't need the encoding
2251 // tricks for the offset value.
2253 if (AddrMode == ARMII::AddrMode_i12)
2254 ImmedOffset = -ImmedOffset;
2256 ImmedOffset |= 1 << NumBits;
2258 ImmOp.ChangeToImmediate(ImmedOffset);
2263 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2264 ImmedOffset = ImmedOffset & Mask;
2266 if (AddrMode == ARMII::AddrMode_i12)
2267 ImmedOffset = -ImmedOffset;
2269 ImmedOffset |= 1 << NumBits;
2271 ImmOp.ChangeToImmediate(ImmedOffset);
2272 Offset &= ~(Mask*Scale);
2276 Offset = (isSub) ? -Offset : Offset;
2280 /// analyzeCompare - For a comparison instruction, return the source registers
2281 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2282 /// compares against in CmpValue. Return true if the comparison instruction
2283 /// can be analyzed.
2284 bool ARMBaseInstrInfo::
2285 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
2286 int &CmpMask, int &CmpValue) const {
2287 switch (MI->getOpcode()) {
2291 SrcReg = MI->getOperand(0).getReg();
2294 CmpValue = MI->getOperand(1).getImm();
2298 SrcReg = MI->getOperand(0).getReg();
2299 SrcReg2 = MI->getOperand(1).getReg();
2305 SrcReg = MI->getOperand(0).getReg();
2307 CmpMask = MI->getOperand(1).getImm();
2315 /// isSuitableForMask - Identify a suitable 'and' instruction that
2316 /// operates on the given source register and applies the same mask
2317 /// as a 'tst' instruction. Provide a limited look-through for copies.
2318 /// When successful, MI will hold the found instruction.
2319 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2320 int CmpMask, bool CommonUse) {
2321 switch (MI->getOpcode()) {
2324 if (CmpMask != MI->getOperand(2).getImm())
2326 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2334 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2335 /// the condition code if we modify the instructions such that flags are
2337 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2339 default: return ARMCC::AL;
2340 case ARMCC::EQ: return ARMCC::EQ;
2341 case ARMCC::NE: return ARMCC::NE;
2342 case ARMCC::HS: return ARMCC::LS;
2343 case ARMCC::LO: return ARMCC::HI;
2344 case ARMCC::HI: return ARMCC::LO;
2345 case ARMCC::LS: return ARMCC::HS;
2346 case ARMCC::GE: return ARMCC::LE;
2347 case ARMCC::LT: return ARMCC::GT;
2348 case ARMCC::GT: return ARMCC::LT;
2349 case ARMCC::LE: return ARMCC::GE;
2353 /// isRedundantFlagInstr - check whether the first instruction, whose only
2354 /// purpose is to update flags, can be made redundant.
2355 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2356 /// CMPri can be made redundant by SUBri if the operands are the same.
2357 /// This function can be extended later on.
2358 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2359 unsigned SrcReg2, int ImmValue,
2361 if ((CmpI->getOpcode() == ARM::CMPrr ||
2362 CmpI->getOpcode() == ARM::t2CMPrr) &&
2363 (OI->getOpcode() == ARM::SUBrr ||
2364 OI->getOpcode() == ARM::t2SUBrr) &&
2365 ((OI->getOperand(1).getReg() == SrcReg &&
2366 OI->getOperand(2).getReg() == SrcReg2) ||
2367 (OI->getOperand(1).getReg() == SrcReg2 &&
2368 OI->getOperand(2).getReg() == SrcReg)))
2371 if ((CmpI->getOpcode() == ARM::CMPri ||
2372 CmpI->getOpcode() == ARM::t2CMPri) &&
2373 (OI->getOpcode() == ARM::SUBri ||
2374 OI->getOpcode() == ARM::t2SUBri) &&
2375 OI->getOperand(1).getReg() == SrcReg &&
2376 OI->getOperand(2).getImm() == ImmValue)
2381 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2382 /// comparison into one that sets the zero bit in the flags register;
2383 /// Remove a redundant Compare instruction if an earlier instruction can set the
2384 /// flags in the same way as Compare.
2385 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2386 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2387 /// condition code of instructions which use the flags.
2388 bool ARMBaseInstrInfo::
2389 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
2390 int CmpMask, int CmpValue,
2391 const MachineRegisterInfo *MRI) const {
2392 // Get the unique definition of SrcReg.
2393 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2394 if (!MI) return false;
2396 // Masked compares sometimes use the same register as the corresponding 'and'.
2397 if (CmpMask != ~0) {
2398 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(MI)) {
2400 for (MachineRegisterInfo::use_instr_iterator
2401 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2403 if (UI->getParent() != CmpInstr->getParent()) continue;
2404 MachineInstr *PotentialAND = &*UI;
2405 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2406 isPredicated(PotentialAND))
2411 if (!MI) return false;
2415 // Get ready to iterate backward from CmpInstr.
2416 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2417 B = CmpInstr->getParent()->begin();
2419 // Early exit if CmpInstr is at the beginning of the BB.
2420 if (I == B) return false;
2422 // There are two possible candidates which can be changed to set CPSR:
2423 // One is MI, the other is a SUB instruction.
2424 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2425 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2426 MachineInstr *Sub = nullptr;
2428 // MI is not a candidate for CMPrr.
2430 else if (MI->getParent() != CmpInstr->getParent() || CmpValue != 0) {
2431 // Conservatively refuse to convert an instruction which isn't in the same
2432 // BB as the comparison.
2433 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2434 // Thus we cannot return here.
2435 if (CmpInstr->getOpcode() == ARM::CMPri ||
2436 CmpInstr->getOpcode() == ARM::t2CMPri)
2442 // Check that CPSR isn't set between the comparison instruction and the one we
2443 // want to change. At the same time, search for Sub.
2444 const TargetRegisterInfo *TRI = &getRegisterInfo();
2446 for (; I != E; --I) {
2447 const MachineInstr &Instr = *I;
2449 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2450 Instr.readsRegister(ARM::CPSR, TRI))
2451 // This instruction modifies or uses CPSR after the one we want to
2452 // change. We can't do this transformation.
2455 // Check whether CmpInstr can be made redundant by the current instruction.
2456 if (isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2462 // The 'and' is below the comparison instruction.
2466 // Return false if no candidates exist.
2470 // The single candidate is called MI.
2473 // We can't use a predicated instruction - it doesn't always write the flags.
2474 if (isPredicated(MI))
2477 switch (MI->getOpcode()) {
2511 case ARM::t2EORri: {
2512 // Scan forward for the use of CPSR
2513 // When checking against MI: if it's a conditional code that requires
2514 // checking of the V bit or C bit, then this is not safe to do.
2515 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2516 // If we are done with the basic block, we need to check whether CPSR is
2518 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2520 bool isSafe = false;
2522 E = CmpInstr->getParent()->end();
2523 while (!isSafe && ++I != E) {
2524 const MachineInstr &Instr = *I;
2525 for (unsigned IO = 0, EO = Instr.getNumOperands();
2526 !isSafe && IO != EO; ++IO) {
2527 const MachineOperand &MO = Instr.getOperand(IO);
2528 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2532 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2538 // Condition code is after the operand before CPSR except for VSELs.
2539 ARMCC::CondCodes CC;
2540 bool IsInstrVSel = true;
2541 switch (Instr.getOpcode()) {
2543 IsInstrVSel = false;
2544 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2565 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2566 if (NewCC == ARMCC::AL)
2568 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2569 // on CMP needs to be updated to be based on SUB.
2570 // Push the condition code operands to OperandsToUpdate.
2571 // If it is safe to remove CmpInstr, the condition code of these
2572 // operands will be modified.
2573 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2574 Sub->getOperand(2).getReg() == SrcReg) {
2575 // VSel doesn't support condition code update.
2578 OperandsToUpdate.push_back(
2579 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2582 // No Sub, so this is x = <op> y, z; cmp x, 0.
2584 case ARMCC::EQ: // Z
2585 case ARMCC::NE: // Z
2586 case ARMCC::MI: // N
2587 case ARMCC::PL: // N
2588 case ARMCC::AL: // none
2589 // CPSR can be used multiple times, we should continue.
2591 case ARMCC::HS: // C
2592 case ARMCC::LO: // C
2593 case ARMCC::VS: // V
2594 case ARMCC::VC: // V
2595 case ARMCC::HI: // C Z
2596 case ARMCC::LS: // C Z
2597 case ARMCC::GE: // N V
2598 case ARMCC::LT: // N V
2599 case ARMCC::GT: // Z N V
2600 case ARMCC::LE: // Z N V
2601 // The instruction uses the V bit or C bit which is not safe.
2608 // If CPSR is not killed nor re-defined, we should check whether it is
2609 // live-out. If it is live-out, do not optimize.
2611 MachineBasicBlock *MBB = CmpInstr->getParent();
2612 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2613 SE = MBB->succ_end(); SI != SE; ++SI)
2614 if ((*SI)->isLiveIn(ARM::CPSR))
2618 // Toggle the optional operand to CPSR.
2619 MI->getOperand(5).setReg(ARM::CPSR);
2620 MI->getOperand(5).setIsDef(true);
2621 assert(!isPredicated(MI) && "Can't use flags from predicated instruction");
2622 CmpInstr->eraseFromParent();
2624 // Modify the condition code of operands in OperandsToUpdate.
2625 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2626 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2627 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2628 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2636 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr *UseMI,
2637 MachineInstr *DefMI, unsigned Reg,
2638 MachineRegisterInfo *MRI) const {
2639 // Fold large immediates into add, sub, or, xor.
2640 unsigned DefOpc = DefMI->getOpcode();
2641 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2643 if (!DefMI->getOperand(1).isImm())
2644 // Could be t2MOVi32imm <ga:xx>
2647 if (!MRI->hasOneNonDBGUse(Reg))
2650 const MCInstrDesc &DefMCID = DefMI->getDesc();
2651 if (DefMCID.hasOptionalDef()) {
2652 unsigned NumOps = DefMCID.getNumOperands();
2653 const MachineOperand &MO = DefMI->getOperand(NumOps-1);
2654 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2655 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2660 const MCInstrDesc &UseMCID = UseMI->getDesc();
2661 if (UseMCID.hasOptionalDef()) {
2662 unsigned NumOps = UseMCID.getNumOperands();
2663 if (UseMI->getOperand(NumOps-1).getReg() == ARM::CPSR)
2664 // If the instruction sets the flag, do not attempt this optimization
2665 // since it may change the semantics of the code.
2669 unsigned UseOpc = UseMI->getOpcode();
2670 unsigned NewUseOpc = 0;
2671 uint32_t ImmVal = (uint32_t)DefMI->getOperand(1).getImm();
2672 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2673 bool Commute = false;
2675 default: return false;
2683 case ARM::t2EORrr: {
2684 Commute = UseMI->getOperand(2).getReg() != Reg;
2691 NewUseOpc = ARM::SUBri;
2697 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2699 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2700 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2703 case ARM::ADDrr: NewUseOpc = ARM::ADDri; break;
2704 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2705 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2709 case ARM::t2SUBrr: {
2713 NewUseOpc = ARM::t2SUBri;
2718 case ARM::t2EORrr: {
2719 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2721 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2722 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2725 case ARM::t2ADDrr: NewUseOpc = ARM::t2ADDri; break;
2726 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2727 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2735 unsigned OpIdx = Commute ? 2 : 1;
2736 unsigned Reg1 = UseMI->getOperand(OpIdx).getReg();
2737 bool isKill = UseMI->getOperand(OpIdx).isKill();
2738 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2739 AddDefaultCC(AddDefaultPred(BuildMI(*UseMI->getParent(),
2740 UseMI, UseMI->getDebugLoc(),
2741 get(NewUseOpc), NewReg)
2742 .addReg(Reg1, getKillRegState(isKill))
2743 .addImm(SOImmValV1)));
2744 UseMI->setDesc(get(NewUseOpc));
2745 UseMI->getOperand(1).setReg(NewReg);
2746 UseMI->getOperand(1).setIsKill();
2747 UseMI->getOperand(2).ChangeToImmediate(SOImmValV2);
2748 DefMI->eraseFromParent();
2752 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2753 const MachineInstr *MI) {
2754 switch (MI->getOpcode()) {
2756 const MCInstrDesc &Desc = MI->getDesc();
2757 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2758 assert(UOps >= 0 && "bad # UOps");
2766 unsigned ShOpVal = MI->getOperand(3).getImm();
2767 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2768 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2771 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2772 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2779 if (!MI->getOperand(2).getReg())
2782 unsigned ShOpVal = MI->getOperand(3).getImm();
2783 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2784 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2787 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2788 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2795 return (ARM_AM::getAM3Op(MI->getOperand(3).getImm()) == ARM_AM::sub) ? 3:2;
2797 case ARM::LDRSB_POST:
2798 case ARM::LDRSH_POST: {
2799 unsigned Rt = MI->getOperand(0).getReg();
2800 unsigned Rm = MI->getOperand(3).getReg();
2801 return (Rt == Rm) ? 4 : 3;
2804 case ARM::LDR_PRE_REG:
2805 case ARM::LDRB_PRE_REG: {
2806 unsigned Rt = MI->getOperand(0).getReg();
2807 unsigned Rm = MI->getOperand(3).getReg();
2810 unsigned ShOpVal = MI->getOperand(4).getImm();
2811 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2812 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2815 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2816 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2821 case ARM::STR_PRE_REG:
2822 case ARM::STRB_PRE_REG: {
2823 unsigned ShOpVal = MI->getOperand(4).getImm();
2824 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2825 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2828 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2829 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2835 case ARM::STRH_PRE: {
2836 unsigned Rt = MI->getOperand(0).getReg();
2837 unsigned Rm = MI->getOperand(3).getReg();
2842 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub)
2846 case ARM::LDR_POST_REG:
2847 case ARM::LDRB_POST_REG:
2848 case ARM::LDRH_POST: {
2849 unsigned Rt = MI->getOperand(0).getReg();
2850 unsigned Rm = MI->getOperand(3).getReg();
2851 return (Rt == Rm) ? 3 : 2;
2854 case ARM::LDR_PRE_IMM:
2855 case ARM::LDRB_PRE_IMM:
2856 case ARM::LDR_POST_IMM:
2857 case ARM::LDRB_POST_IMM:
2858 case ARM::STRB_POST_IMM:
2859 case ARM::STRB_POST_REG:
2860 case ARM::STRB_PRE_IMM:
2861 case ARM::STRH_POST:
2862 case ARM::STR_POST_IMM:
2863 case ARM::STR_POST_REG:
2864 case ARM::STR_PRE_IMM:
2867 case ARM::LDRSB_PRE:
2868 case ARM::LDRSH_PRE: {
2869 unsigned Rm = MI->getOperand(3).getReg();
2872 unsigned Rt = MI->getOperand(0).getReg();
2875 unsigned ShOpVal = MI->getOperand(4).getImm();
2876 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2877 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2880 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2881 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2887 unsigned Rt = MI->getOperand(0).getReg();
2888 unsigned Rn = MI->getOperand(2).getReg();
2889 unsigned Rm = MI->getOperand(3).getReg();
2891 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2892 return (Rt == Rn) ? 3 : 2;
2896 unsigned Rm = MI->getOperand(3).getReg();
2898 return (ARM_AM::getAM3Op(MI->getOperand(4).getImm()) == ARM_AM::sub) ?4:3;
2902 case ARM::LDRD_POST:
2903 case ARM::t2LDRD_POST:
2906 case ARM::STRD_POST:
2907 case ARM::t2STRD_POST:
2910 case ARM::LDRD_PRE: {
2911 unsigned Rt = MI->getOperand(0).getReg();
2912 unsigned Rn = MI->getOperand(3).getReg();
2913 unsigned Rm = MI->getOperand(4).getReg();
2915 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2916 return (Rt == Rn) ? 4 : 3;
2919 case ARM::t2LDRD_PRE: {
2920 unsigned Rt = MI->getOperand(0).getReg();
2921 unsigned Rn = MI->getOperand(3).getReg();
2922 return (Rt == Rn) ? 4 : 3;
2925 case ARM::STRD_PRE: {
2926 unsigned Rm = MI->getOperand(4).getReg();
2928 return (ARM_AM::getAM3Op(MI->getOperand(5).getImm()) == ARM_AM::sub) ?5:4;
2932 case ARM::t2STRD_PRE:
2935 case ARM::t2LDR_POST:
2936 case ARM::t2LDRB_POST:
2937 case ARM::t2LDRB_PRE:
2938 case ARM::t2LDRSBi12:
2939 case ARM::t2LDRSBi8:
2940 case ARM::t2LDRSBpci:
2942 case ARM::t2LDRH_POST:
2943 case ARM::t2LDRH_PRE:
2945 case ARM::t2LDRSB_POST:
2946 case ARM::t2LDRSB_PRE:
2947 case ARM::t2LDRSH_POST:
2948 case ARM::t2LDRSH_PRE:
2949 case ARM::t2LDRSHi12:
2950 case ARM::t2LDRSHi8:
2951 case ARM::t2LDRSHpci:
2955 case ARM::t2LDRDi8: {
2956 unsigned Rt = MI->getOperand(0).getReg();
2957 unsigned Rn = MI->getOperand(2).getReg();
2958 return (Rt == Rn) ? 3 : 2;
2961 case ARM::t2STRB_POST:
2962 case ARM::t2STRB_PRE:
2965 case ARM::t2STRH_POST:
2966 case ARM::t2STRH_PRE:
2968 case ARM::t2STR_POST:
2969 case ARM::t2STR_PRE:
2975 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
2976 // can't be easily determined return 0 (missing MachineMemOperand).
2978 // FIXME: The current MachineInstr design does not support relying on machine
2979 // mem operands to determine the width of a memory access. Instead, we expect
2980 // the target to provide this information based on the instruction opcode and
2981 // operands. However, using MachineMemOperand is the best solution now for
2984 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
2985 // operands. This is much more dangerous than using the MachineMemOperand
2986 // sizes because CodeGen passes can insert/remove optional machine operands. In
2987 // fact, it's totally incorrect for preRA passes and appears to be wrong for
2988 // postRA passes as well.
2990 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
2991 // machine model that calls this should handle the unknown (zero size) case.
2993 // Long term, we should require a target hook that verifies MachineMemOperand
2994 // sizes during MC lowering. That target hook should be local to MC lowering
2995 // because we can't ensure that it is aware of other MI forms. Doing this will
2996 // ensure that MachineMemOperands are correctly propagated through all passes.
2997 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr *MI) const {
2999 for (MachineInstr::mmo_iterator I = MI->memoperands_begin(),
3000 E = MI->memoperands_end(); I != E; ++I) {
3001 Size += (*I)->getSize();
3007 ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3008 const MachineInstr *MI) const {
3009 if (!ItinData || ItinData->isEmpty())
3012 const MCInstrDesc &Desc = MI->getDesc();
3013 unsigned Class = Desc.getSchedClass();
3014 int ItinUOps = ItinData->getNumMicroOps(Class);
3015 if (ItinUOps >= 0) {
3016 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3017 return getNumMicroOpsSwiftLdSt(ItinData, MI);
3022 unsigned Opc = MI->getOpcode();
3025 llvm_unreachable("Unexpected multi-uops instruction!");
3030 // The number of uOps for load / store multiple are determined by the number
3033 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3034 // same cycle. The scheduling for the first load / store must be done
3035 // separately by assuming the address is not 64-bit aligned.
3037 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3038 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3039 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3041 case ARM::VLDMDIA_UPD:
3042 case ARM::VLDMDDB_UPD:
3044 case ARM::VLDMSIA_UPD:
3045 case ARM::VLDMSDB_UPD:
3047 case ARM::VSTMDIA_UPD:
3048 case ARM::VSTMDDB_UPD:
3050 case ARM::VSTMSIA_UPD:
3051 case ARM::VSTMSDB_UPD: {
3052 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands();
3053 return (NumRegs / 2) + (NumRegs % 2) + 1;
3056 case ARM::LDMIA_RET:
3061 case ARM::LDMIA_UPD:
3062 case ARM::LDMDA_UPD:
3063 case ARM::LDMDB_UPD:
3064 case ARM::LDMIB_UPD:
3069 case ARM::STMIA_UPD:
3070 case ARM::STMDA_UPD:
3071 case ARM::STMDB_UPD:
3072 case ARM::STMIB_UPD:
3074 case ARM::tLDMIA_UPD:
3075 case ARM::tSTMIA_UPD:
3079 case ARM::t2LDMIA_RET:
3082 case ARM::t2LDMIA_UPD:
3083 case ARM::t2LDMDB_UPD:
3086 case ARM::t2STMIA_UPD:
3087 case ARM::t2STMDB_UPD: {
3088 unsigned NumRegs = MI->getNumOperands() - Desc.getNumOperands() + 1;
3089 if (Subtarget.isSwift()) {
3090 int UOps = 1 + NumRegs; // One for address computation, one for each ld / st.
3093 case ARM::VLDMDIA_UPD:
3094 case ARM::VLDMDDB_UPD:
3095 case ARM::VLDMSIA_UPD:
3096 case ARM::VLDMSDB_UPD:
3097 case ARM::VSTMDIA_UPD:
3098 case ARM::VSTMDDB_UPD:
3099 case ARM::VSTMSIA_UPD:
3100 case ARM::VSTMSDB_UPD:
3101 case ARM::LDMIA_UPD:
3102 case ARM::LDMDA_UPD:
3103 case ARM::LDMDB_UPD:
3104 case ARM::LDMIB_UPD:
3105 case ARM::STMIA_UPD:
3106 case ARM::STMDA_UPD:
3107 case ARM::STMDB_UPD:
3108 case ARM::STMIB_UPD:
3109 case ARM::tLDMIA_UPD:
3110 case ARM::tSTMIA_UPD:
3111 case ARM::t2LDMIA_UPD:
3112 case ARM::t2LDMDB_UPD:
3113 case ARM::t2STMIA_UPD:
3114 case ARM::t2STMDB_UPD:
3115 ++UOps; // One for base register writeback.
3117 case ARM::LDMIA_RET:
3119 case ARM::t2LDMIA_RET:
3120 UOps += 2; // One for base reg wb, one for write to pc.
3124 } else if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3127 // 4 registers would be issued: 2, 2.
3128 // 5 registers would be issued: 2, 2, 1.
3129 int A8UOps = (NumRegs / 2);
3133 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3134 int A9UOps = (NumRegs / 2);
3135 // If there are odd number of registers or if it's not 64-bit aligned,
3136 // then it takes an extra AGU (Address Generation Unit) cycle.
3137 if ((NumRegs % 2) ||
3138 !MI->hasOneMemOperand() ||
3139 (*MI->memoperands_begin())->getAlignment() < 8)
3143 // Assume the worst.
3151 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3152 const MCInstrDesc &DefMCID,
3154 unsigned DefIdx, unsigned DefAlign) const {
3155 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3157 // Def is the address writeback.
3158 return ItinData->getOperandCycle(DefClass, DefIdx);
3161 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3162 // (regno / 2) + (regno % 2) + 1
3163 DefCycle = RegNo / 2 + 1;
3166 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3168 bool isSLoad = false;
3170 switch (DefMCID.getOpcode()) {
3173 case ARM::VLDMSIA_UPD:
3174 case ARM::VLDMSDB_UPD:
3179 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3180 // then it takes an extra cycle.
3181 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3184 // Assume the worst.
3185 DefCycle = RegNo + 2;
3192 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3193 const MCInstrDesc &DefMCID,
3195 unsigned DefIdx, unsigned DefAlign) const {
3196 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3198 // Def is the address writeback.
3199 return ItinData->getOperandCycle(DefClass, DefIdx);
3202 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3203 // 4 registers would be issued: 1, 2, 1.
3204 // 5 registers would be issued: 1, 2, 2.
3205 DefCycle = RegNo / 2;
3208 // Result latency is issue cycle + 2: E2.
3210 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3211 DefCycle = (RegNo / 2);
3212 // If there are odd number of registers or if it's not 64-bit aligned,
3213 // then it takes an extra AGU (Address Generation Unit) cycle.
3214 if ((RegNo % 2) || DefAlign < 8)
3216 // Result latency is AGU cycles + 2.
3219 // Assume the worst.
3220 DefCycle = RegNo + 2;
3227 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3228 const MCInstrDesc &UseMCID,
3230 unsigned UseIdx, unsigned UseAlign) const {
3231 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3233 return ItinData->getOperandCycle(UseClass, UseIdx);
3236 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3237 // (regno / 2) + (regno % 2) + 1
3238 UseCycle = RegNo / 2 + 1;
3241 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3243 bool isSStore = false;
3245 switch (UseMCID.getOpcode()) {
3248 case ARM::VSTMSIA_UPD:
3249 case ARM::VSTMSDB_UPD:
3254 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3255 // then it takes an extra cycle.
3256 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3259 // Assume the worst.
3260 UseCycle = RegNo + 2;
3267 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3268 const MCInstrDesc &UseMCID,
3270 unsigned UseIdx, unsigned UseAlign) const {
3271 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3273 return ItinData->getOperandCycle(UseClass, UseIdx);
3276 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3277 UseCycle = RegNo / 2;
3282 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3283 UseCycle = (RegNo / 2);
3284 // If there are odd number of registers or if it's not 64-bit aligned,
3285 // then it takes an extra AGU (Address Generation Unit) cycle.
3286 if ((RegNo % 2) || UseAlign < 8)
3289 // Assume the worst.
3296 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3297 const MCInstrDesc &DefMCID,
3298 unsigned DefIdx, unsigned DefAlign,
3299 const MCInstrDesc &UseMCID,
3300 unsigned UseIdx, unsigned UseAlign) const {
3301 unsigned DefClass = DefMCID.getSchedClass();
3302 unsigned UseClass = UseMCID.getSchedClass();
3304 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3305 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3307 // This may be a def / use of a variable_ops instruction, the operand
3308 // latency might be determinable dynamically. Let the target try to
3311 bool LdmBypass = false;
3312 switch (DefMCID.getOpcode()) {
3314 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3318 case ARM::VLDMDIA_UPD:
3319 case ARM::VLDMDDB_UPD:
3321 case ARM::VLDMSIA_UPD:
3322 case ARM::VLDMSDB_UPD:
3323 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3326 case ARM::LDMIA_RET:
3331 case ARM::LDMIA_UPD:
3332 case ARM::LDMDA_UPD:
3333 case ARM::LDMDB_UPD:
3334 case ARM::LDMIB_UPD:
3336 case ARM::tLDMIA_UPD:
3338 case ARM::t2LDMIA_RET:
3341 case ARM::t2LDMIA_UPD:
3342 case ARM::t2LDMDB_UPD:
3344 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3349 // We can't seem to determine the result latency of the def, assume it's 2.
3353 switch (UseMCID.getOpcode()) {
3355 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3359 case ARM::VSTMDIA_UPD:
3360 case ARM::VSTMDDB_UPD:
3362 case ARM::VSTMSIA_UPD:
3363 case ARM::VSTMSDB_UPD:
3364 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3371 case ARM::STMIA_UPD:
3372 case ARM::STMDA_UPD:
3373 case ARM::STMDB_UPD:
3374 case ARM::STMIB_UPD:
3375 case ARM::tSTMIA_UPD:
3380 case ARM::t2STMIA_UPD:
3381 case ARM::t2STMDB_UPD:
3382 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3387 // Assume it's read in the first stage.
3390 UseCycle = DefCycle - UseCycle + 1;
3393 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3394 // first def operand.
3395 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3398 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3399 UseClass, UseIdx)) {
3407 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3408 const MachineInstr *MI, unsigned Reg,
3409 unsigned &DefIdx, unsigned &Dist) {
3412 MachineBasicBlock::const_iterator I = MI; ++I;
3413 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3414 assert(II->isInsideBundle() && "Empty bundle?");
3417 while (II->isInsideBundle()) {
3418 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3425 assert(Idx != -1 && "Cannot find bundled definition!");
3430 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3431 const MachineInstr *MI, unsigned Reg,
3432 unsigned &UseIdx, unsigned &Dist) {
3435 MachineBasicBlock::const_instr_iterator II = ++MI->getIterator();
3436 assert(II->isInsideBundle() && "Empty bundle?");
3437 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3439 // FIXME: This doesn't properly handle multiple uses.
3441 while (II != E && II->isInsideBundle()) {
3442 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3445 if (II->getOpcode() != ARM::t2IT)
3459 /// Return the number of cycles to add to (or subtract from) the static
3460 /// itinerary based on the def opcode and alignment. The caller will ensure that
3461 /// adjusted latency is at least one cycle.
3462 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3463 const MachineInstr *DefMI,
3464 const MCInstrDesc *DefMCID, unsigned DefAlign) {
3466 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3467 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3468 // variants are one cycle cheaper.
3469 switch (DefMCID->getOpcode()) {
3473 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3474 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3476 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3483 case ARM::t2LDRSHs: {
3484 // Thumb2 mode: lsl only.
3485 unsigned ShAmt = DefMI->getOperand(3).getImm();
3486 if (ShAmt == 0 || ShAmt == 2)
3491 } else if (Subtarget.isSwift()) {
3492 // FIXME: Properly handle all of the latency adjustments for address
3494 switch (DefMCID->getOpcode()) {
3498 unsigned ShOpVal = DefMI->getOperand(3).getImm();
3499 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3500 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3503 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3504 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3507 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3514 case ARM::t2LDRSHs: {
3515 // Thumb2 mode: lsl only.
3516 unsigned ShAmt = DefMI->getOperand(3).getImm();
3517 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3524 if (DefAlign < 8 && Subtarget.isLikeA9()) {
3525 switch (DefMCID->getOpcode()) {
3531 case ARM::VLD1q8wb_fixed:
3532 case ARM::VLD1q16wb_fixed:
3533 case ARM::VLD1q32wb_fixed:
3534 case ARM::VLD1q64wb_fixed:
3535 case ARM::VLD1q8wb_register:
3536 case ARM::VLD1q16wb_register:
3537 case ARM::VLD1q32wb_register:
3538 case ARM::VLD1q64wb_register:
3545 case ARM::VLD2d8wb_fixed:
3546 case ARM::VLD2d16wb_fixed:
3547 case ARM::VLD2d32wb_fixed:
3548 case ARM::VLD2q8wb_fixed:
3549 case ARM::VLD2q16wb_fixed:
3550 case ARM::VLD2q32wb_fixed:
3551 case ARM::VLD2d8wb_register:
3552 case ARM::VLD2d16wb_register:
3553 case ARM::VLD2d32wb_register:
3554 case ARM::VLD2q8wb_register:
3555 case ARM::VLD2q16wb_register:
3556 case ARM::VLD2q32wb_register:
3561 case ARM::VLD3d8_UPD:
3562 case ARM::VLD3d16_UPD:
3563 case ARM::VLD3d32_UPD:
3564 case ARM::VLD1d64Twb_fixed:
3565 case ARM::VLD1d64Twb_register:
3566 case ARM::VLD3q8_UPD:
3567 case ARM::VLD3q16_UPD:
3568 case ARM::VLD3q32_UPD:
3573 case ARM::VLD4d8_UPD:
3574 case ARM::VLD4d16_UPD:
3575 case ARM::VLD4d32_UPD:
3576 case ARM::VLD1d64Qwb_fixed:
3577 case ARM::VLD1d64Qwb_register:
3578 case ARM::VLD4q8_UPD:
3579 case ARM::VLD4q16_UPD:
3580 case ARM::VLD4q32_UPD:
3581 case ARM::VLD1DUPq8:
3582 case ARM::VLD1DUPq16:
3583 case ARM::VLD1DUPq32:
3584 case ARM::VLD1DUPq8wb_fixed:
3585 case ARM::VLD1DUPq16wb_fixed:
3586 case ARM::VLD1DUPq32wb_fixed:
3587 case ARM::VLD1DUPq8wb_register:
3588 case ARM::VLD1DUPq16wb_register:
3589 case ARM::VLD1DUPq32wb_register:
3590 case ARM::VLD2DUPd8:
3591 case ARM::VLD2DUPd16:
3592 case ARM::VLD2DUPd32:
3593 case ARM::VLD2DUPd8wb_fixed:
3594 case ARM::VLD2DUPd16wb_fixed:
3595 case ARM::VLD2DUPd32wb_fixed:
3596 case ARM::VLD2DUPd8wb_register:
3597 case ARM::VLD2DUPd16wb_register:
3598 case ARM::VLD2DUPd32wb_register:
3599 case ARM::VLD4DUPd8:
3600 case ARM::VLD4DUPd16:
3601 case ARM::VLD4DUPd32:
3602 case ARM::VLD4DUPd8_UPD:
3603 case ARM::VLD4DUPd16_UPD:
3604 case ARM::VLD4DUPd32_UPD:
3606 case ARM::VLD1LNd16:
3607 case ARM::VLD1LNd32:
3608 case ARM::VLD1LNd8_UPD:
3609 case ARM::VLD1LNd16_UPD:
3610 case ARM::VLD1LNd32_UPD:
3612 case ARM::VLD2LNd16:
3613 case ARM::VLD2LNd32:
3614 case ARM::VLD2LNq16:
3615 case ARM::VLD2LNq32:
3616 case ARM::VLD2LNd8_UPD:
3617 case ARM::VLD2LNd16_UPD:
3618 case ARM::VLD2LNd32_UPD:
3619 case ARM::VLD2LNq16_UPD:
3620 case ARM::VLD2LNq32_UPD:
3622 case ARM::VLD4LNd16:
3623 case ARM::VLD4LNd32:
3624 case ARM::VLD4LNq16:
3625 case ARM::VLD4LNq32:
3626 case ARM::VLD4LNd8_UPD:
3627 case ARM::VLD4LNd16_UPD:
3628 case ARM::VLD4LNd32_UPD:
3629 case ARM::VLD4LNq16_UPD:
3630 case ARM::VLD4LNq32_UPD:
3631 // If the address is not 64-bit aligned, the latencies of these
3632 // instructions increases by one.
3643 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3644 const MachineInstr *DefMI, unsigned DefIdx,
3645 const MachineInstr *UseMI,
3646 unsigned UseIdx) const {
3647 // No operand latency. The caller may fall back to getInstrLatency.
3648 if (!ItinData || ItinData->isEmpty())
3651 const MachineOperand &DefMO = DefMI->getOperand(DefIdx);
3652 unsigned Reg = DefMO.getReg();
3653 const MCInstrDesc *DefMCID = &DefMI->getDesc();
3654 const MCInstrDesc *UseMCID = &UseMI->getDesc();
3656 unsigned DefAdj = 0;
3657 if (DefMI->isBundle()) {
3658 DefMI = getBundledDefMI(&getRegisterInfo(), DefMI, Reg, DefIdx, DefAdj);
3659 DefMCID = &DefMI->getDesc();
3661 if (DefMI->isCopyLike() || DefMI->isInsertSubreg() ||
3662 DefMI->isRegSequence() || DefMI->isImplicitDef()) {
3666 unsigned UseAdj = 0;
3667 if (UseMI->isBundle()) {
3669 const MachineInstr *NewUseMI = getBundledUseMI(&getRegisterInfo(), UseMI,
3670 Reg, NewUseIdx, UseAdj);
3676 UseMCID = &UseMI->getDesc();
3679 if (Reg == ARM::CPSR) {
3680 if (DefMI->getOpcode() == ARM::FMSTAT) {
3681 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3682 return Subtarget.isLikeA9() ? 1 : 20;
3685 // CPSR set and branch can be paired in the same cycle.
3686 if (UseMI->isBranch())
3689 // Otherwise it takes the instruction latency (generally one).
3690 unsigned Latency = getInstrLatency(ItinData, DefMI);
3692 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3693 // its uses. Instructions which are otherwise scheduled between them may
3694 // incur a code size penalty (not able to use the CPSR setting 16-bit
3696 if (Latency > 0 && Subtarget.isThumb2()) {
3697 const MachineFunction *MF = DefMI->getParent()->getParent();
3698 // FIXME: Use Function::optForSize().
3699 if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3705 if (DefMO.isImplicit() || UseMI->getOperand(UseIdx).isImplicit())
3708 unsigned DefAlign = DefMI->hasOneMemOperand()
3709 ? (*DefMI->memoperands_begin())->getAlignment() : 0;
3710 unsigned UseAlign = UseMI->hasOneMemOperand()
3711 ? (*UseMI->memoperands_begin())->getAlignment() : 0;
3713 // Get the itinerary's latency if possible, and handle variable_ops.
3714 int Latency = getOperandLatency(ItinData, *DefMCID, DefIdx, DefAlign,
3715 *UseMCID, UseIdx, UseAlign);
3716 // Unable to find operand latency. The caller may resort to getInstrLatency.
3720 // Adjust for IT block position.
3721 int Adj = DefAdj + UseAdj;
3723 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3724 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3725 if (Adj >= 0 || (int)Latency > -Adj) {
3726 return Latency + Adj;
3728 // Return the itinerary latency, which may be zero but not less than zero.
3733 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3734 SDNode *DefNode, unsigned DefIdx,
3735 SDNode *UseNode, unsigned UseIdx) const {
3736 if (!DefNode->isMachineOpcode())
3739 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3741 if (isZeroCost(DefMCID.Opcode))
3744 if (!ItinData || ItinData->isEmpty())
3745 return DefMCID.mayLoad() ? 3 : 1;
3747 if (!UseNode->isMachineOpcode()) {
3748 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3749 if (Subtarget.isLikeA9() || Subtarget.isSwift())
3750 return Latency <= 2 ? 1 : Latency - 1;
3752 return Latency <= 3 ? 1 : Latency - 2;
3755 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3756 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3757 unsigned DefAlign = !DefMN->memoperands_empty()
3758 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3759 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3760 unsigned UseAlign = !UseMN->memoperands_empty()
3761 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3762 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3763 UseMCID, UseIdx, UseAlign);
3766 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3767 Subtarget.isCortexA7())) {
3768 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3769 // variants are one cycle cheaper.
3770 switch (DefMCID.getOpcode()) {
3775 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3776 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3778 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3785 case ARM::t2LDRSHs: {
3786 // Thumb2 mode: lsl only.
3788 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3789 if (ShAmt == 0 || ShAmt == 2)
3794 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3795 // FIXME: Properly handle all of the latency adjustments for address
3797 switch (DefMCID.getOpcode()) {
3802 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3803 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3805 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3806 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3808 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3815 case ARM::t2LDRSHs: {
3816 // Thumb2 mode: lsl 0-3 only.
3823 if (DefAlign < 8 && Subtarget.isLikeA9())
3824 switch (DefMCID.getOpcode()) {
3830 case ARM::VLD1q8wb_register:
3831 case ARM::VLD1q16wb_register:
3832 case ARM::VLD1q32wb_register:
3833 case ARM::VLD1q64wb_register:
3834 case ARM::VLD1q8wb_fixed:
3835 case ARM::VLD1q16wb_fixed:
3836 case ARM::VLD1q32wb_fixed:
3837 case ARM::VLD1q64wb_fixed:
3841 case ARM::VLD2q8Pseudo:
3842 case ARM::VLD2q16Pseudo:
3843 case ARM::VLD2q32Pseudo:
3844 case ARM::VLD2d8wb_fixed:
3845 case ARM::VLD2d16wb_fixed:
3846 case ARM::VLD2d32wb_fixed:
3847 case ARM::VLD2q8PseudoWB_fixed:
3848 case ARM::VLD2q16PseudoWB_fixed:
3849 case ARM::VLD2q32PseudoWB_fixed:
3850 case ARM::VLD2d8wb_register:
3851 case ARM::VLD2d16wb_register:
3852 case ARM::VLD2d32wb_register:
3853 case ARM::VLD2q8PseudoWB_register:
3854 case ARM::VLD2q16PseudoWB_register:
3855 case ARM::VLD2q32PseudoWB_register:
3856 case ARM::VLD3d8Pseudo:
3857 case ARM::VLD3d16Pseudo:
3858 case ARM::VLD3d32Pseudo:
3859 case ARM::VLD1d64TPseudo:
3860 case ARM::VLD1d64TPseudoWB_fixed:
3861 case ARM::VLD3d8Pseudo_UPD:
3862 case ARM::VLD3d16Pseudo_UPD:
3863 case ARM::VLD3d32Pseudo_UPD:
3864 case ARM::VLD3q8Pseudo_UPD:
3865 case ARM::VLD3q16Pseudo_UPD:
3866 case ARM::VLD3q32Pseudo_UPD:
3867 case ARM::VLD3q8oddPseudo:
3868 case ARM::VLD3q16oddPseudo:
3869 case ARM::VLD3q32oddPseudo:
3870 case ARM::VLD3q8oddPseudo_UPD:
3871 case ARM::VLD3q16oddPseudo_UPD:
3872 case ARM::VLD3q32oddPseudo_UPD:
3873 case ARM::VLD4d8Pseudo:
3874 case ARM::VLD4d16Pseudo:
3875 case ARM::VLD4d32Pseudo:
3876 case ARM::VLD1d64QPseudo:
3877 case ARM::VLD1d64QPseudoWB_fixed:
3878 case ARM::VLD4d8Pseudo_UPD:
3879 case ARM::VLD4d16Pseudo_UPD:
3880 case ARM::VLD4d32Pseudo_UPD:
3881 case ARM::VLD4q8Pseudo_UPD:
3882 case ARM::VLD4q16Pseudo_UPD:
3883 case ARM::VLD4q32Pseudo_UPD:
3884 case ARM::VLD4q8oddPseudo:
3885 case ARM::VLD4q16oddPseudo:
3886 case ARM::VLD4q32oddPseudo:
3887 case ARM::VLD4q8oddPseudo_UPD:
3888 case ARM::VLD4q16oddPseudo_UPD:
3889 case ARM::VLD4q32oddPseudo_UPD:
3890 case ARM::VLD1DUPq8:
3891 case ARM::VLD1DUPq16:
3892 case ARM::VLD1DUPq32:
3893 case ARM::VLD1DUPq8wb_fixed:
3894 case ARM::VLD1DUPq16wb_fixed:
3895 case ARM::VLD1DUPq32wb_fixed:
3896 case ARM::VLD1DUPq8wb_register:
3897 case ARM::VLD1DUPq16wb_register:
3898 case ARM::VLD1DUPq32wb_register:
3899 case ARM::VLD2DUPd8:
3900 case ARM::VLD2DUPd16:
3901 case ARM::VLD2DUPd32:
3902 case ARM::VLD2DUPd8wb_fixed:
3903 case ARM::VLD2DUPd16wb_fixed:
3904 case ARM::VLD2DUPd32wb_fixed:
3905 case ARM::VLD2DUPd8wb_register:
3906 case ARM::VLD2DUPd16wb_register:
3907 case ARM::VLD2DUPd32wb_register:
3908 case ARM::VLD4DUPd8Pseudo:
3909 case ARM::VLD4DUPd16Pseudo:
3910 case ARM::VLD4DUPd32Pseudo:
3911 case ARM::VLD4DUPd8Pseudo_UPD:
3912 case ARM::VLD4DUPd16Pseudo_UPD:
3913 case ARM::VLD4DUPd32Pseudo_UPD:
3914 case ARM::VLD1LNq8Pseudo:
3915 case ARM::VLD1LNq16Pseudo:
3916 case ARM::VLD1LNq32Pseudo:
3917 case ARM::VLD1LNq8Pseudo_UPD:
3918 case ARM::VLD1LNq16Pseudo_UPD:
3919 case ARM::VLD1LNq32Pseudo_UPD:
3920 case ARM::VLD2LNd8Pseudo:
3921 case ARM::VLD2LNd16Pseudo:
3922 case ARM::VLD2LNd32Pseudo:
3923 case ARM::VLD2LNq16Pseudo:
3924 case ARM::VLD2LNq32Pseudo:
3925 case ARM::VLD2LNd8Pseudo_UPD:
3926 case ARM::VLD2LNd16Pseudo_UPD:
3927 case ARM::VLD2LNd32Pseudo_UPD:
3928 case ARM::VLD2LNq16Pseudo_UPD:
3929 case ARM::VLD2LNq32Pseudo_UPD:
3930 case ARM::VLD4LNd8Pseudo:
3931 case ARM::VLD4LNd16Pseudo:
3932 case ARM::VLD4LNd32Pseudo:
3933 case ARM::VLD4LNq16Pseudo:
3934 case ARM::VLD4LNq32Pseudo:
3935 case ARM::VLD4LNd8Pseudo_UPD:
3936 case ARM::VLD4LNd16Pseudo_UPD:
3937 case ARM::VLD4LNd32Pseudo_UPD:
3938 case ARM::VLD4LNq16Pseudo_UPD:
3939 case ARM::VLD4LNq32Pseudo_UPD:
3940 // If the address is not 64-bit aligned, the latencies of these
3941 // instructions increases by one.
3949 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr *MI) const {
3950 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3951 MI->isRegSequence() || MI->isImplicitDef())
3957 const MCInstrDesc &MCID = MI->getDesc();
3959 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
3960 // When predicated, CPSR is an additional source operand for CPSR updating
3961 // instructions, this apparently increases their latencies.
3967 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
3968 const MachineInstr *MI,
3969 unsigned *PredCost) const {
3970 if (MI->isCopyLike() || MI->isInsertSubreg() ||
3971 MI->isRegSequence() || MI->isImplicitDef())
3974 // An instruction scheduler typically runs on unbundled instructions, however
3975 // other passes may query the latency of a bundled instruction.
3976 if (MI->isBundle()) {
3977 unsigned Latency = 0;
3978 MachineBasicBlock::const_instr_iterator I = MI->getIterator();
3979 MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
3980 while (++I != E && I->isInsideBundle()) {
3981 if (I->getOpcode() != ARM::t2IT)
3982 Latency += getInstrLatency(ItinData, &*I, PredCost);
3987 const MCInstrDesc &MCID = MI->getDesc();
3988 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
3989 // When predicated, CPSR is an additional source operand for CPSR updating
3990 // instructions, this apparently increases their latencies.
3993 // Be sure to call getStageLatency for an empty itinerary in case it has a
3994 // valid MinLatency property.
3996 return MI->mayLoad() ? 3 : 1;
3998 unsigned Class = MCID.getSchedClass();
4000 // For instructions with variable uops, use uops as latency.
4001 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4002 return getNumMicroOps(ItinData, MI);
4004 // For the common case, fall back on the itinerary's latency.
4005 unsigned Latency = ItinData->getStageLatency(Class);
4007 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4008 unsigned DefAlign = MI->hasOneMemOperand()
4009 ? (*MI->memoperands_begin())->getAlignment() : 0;
4010 int Adj = adjustDefLatency(Subtarget, MI, &MCID, DefAlign);
4011 if (Adj >= 0 || (int)Latency > -Adj) {
4012 return Latency + Adj;
4017 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4018 SDNode *Node) const {
4019 if (!Node->isMachineOpcode())
4022 if (!ItinData || ItinData->isEmpty())
4025 unsigned Opcode = Node->getMachineOpcode();
4028 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4035 bool ARMBaseInstrInfo::
4036 hasHighOperandLatency(const TargetSchedModel &SchedModel,
4037 const MachineRegisterInfo *MRI,
4038 const MachineInstr *DefMI, unsigned DefIdx,
4039 const MachineInstr *UseMI, unsigned UseIdx) const {
4040 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4041 unsigned UDomain = UseMI->getDesc().TSFlags & ARMII::DomainMask;
4042 if (Subtarget.isCortexA8() &&
4043 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4044 // CortexA8 VFP instructions are not pipelined.
4047 // Hoist VFP / NEON instructions with 4 or higher latency.
4049 = SchedModel.computeOperandLatency(DefMI, DefIdx, UseMI, UseIdx);
4052 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4053 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4056 bool ARMBaseInstrInfo::
4057 hasLowDefLatency(const TargetSchedModel &SchedModel,
4058 const MachineInstr *DefMI, unsigned DefIdx) const {
4059 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4060 if (!ItinData || ItinData->isEmpty())
4063 unsigned DDomain = DefMI->getDesc().TSFlags & ARMII::DomainMask;
4064 if (DDomain == ARMII::DomainGeneral) {
4065 unsigned DefClass = DefMI->getDesc().getSchedClass();
4066 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4067 return (DefCycle != -1 && DefCycle <= 2);
4072 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr *MI,
4073 StringRef &ErrInfo) const {
4074 if (convertAddSubFlagsOpcode(MI->getOpcode())) {
4075 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4081 // LoadStackGuard has so far only been implemented for MachO. Different code
4082 // sequence is needed for other targets.
4083 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4084 unsigned LoadImmOpc,
4086 Reloc::Model RM) const {
4087 MachineBasicBlock &MBB = *MI->getParent();
4088 DebugLoc DL = MI->getDebugLoc();
4089 unsigned Reg = MI->getOperand(0).getReg();
4090 const GlobalValue *GV =
4091 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4092 MachineInstrBuilder MIB;
4094 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4095 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4097 if (Subtarget.GVIsIndirectSymbol(GV, RM)) {
4098 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4099 MIB.addReg(Reg, RegState::Kill).addImm(0);
4100 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
4101 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4102 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 4, 4);
4103 MIB.addMemOperand(MMO);
4104 AddDefaultPred(MIB);
4107 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4108 MIB.addReg(Reg, RegState::Kill).addImm(0);
4109 MIB.setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
4110 AddDefaultPred(MIB);
4114 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4115 unsigned &AddSubOpc,
4116 bool &NegAcc, bool &HasLane) const {
4117 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4118 if (I == MLxEntryMap.end())
4121 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4122 MulOpc = Entry.MulOpc;
4123 AddSubOpc = Entry.AddSubOpc;
4124 NegAcc = Entry.NegAcc;
4125 HasLane = Entry.HasLane;
4129 //===----------------------------------------------------------------------===//
4130 // Execution domains.
4131 //===----------------------------------------------------------------------===//
4133 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4134 // and some can go down both. The vmov instructions go down the VFP pipeline,
4135 // but they can be changed to vorr equivalents that are executed by the NEON
4138 // We use the following execution domain numbering:
4146 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4148 std::pair<uint16_t, uint16_t>
4149 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr *MI) const {
4150 // If we don't have access to NEON instructions then we won't be able
4151 // to swizzle anything to the NEON domain. Check to make sure.
4152 if (Subtarget.hasNEON()) {
4153 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4154 // if they are not predicated.
4155 if (MI->getOpcode() == ARM::VMOVD && !isPredicated(MI))
4156 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4158 // CortexA9 is particularly picky about mixing the two and wants these
4160 if (Subtarget.isCortexA9() && !isPredicated(MI) &&
4161 (MI->getOpcode() == ARM::VMOVRS || MI->getOpcode() == ARM::VMOVSR ||
4162 MI->getOpcode() == ARM::VMOVS))
4163 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4165 // No other instructions can be swizzled, so just determine their domain.
4166 unsigned Domain = MI->getDesc().TSFlags & ARMII::DomainMask;
4168 if (Domain & ARMII::DomainNEON)
4169 return std::make_pair(ExeNEON, 0);
4171 // Certain instructions can go either way on Cortex-A8.
4172 // Treat them as NEON instructions.
4173 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4174 return std::make_pair(ExeNEON, 0);
4176 if (Domain & ARMII::DomainVFP)
4177 return std::make_pair(ExeVFP, 0);
4179 return std::make_pair(ExeGeneric, 0);
4182 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4183 unsigned SReg, unsigned &Lane) {
4184 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4187 if (DReg != ARM::NoRegister)
4191 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4193 assert(DReg && "S-register with no D super-register?");
4197 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4198 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4199 /// zero if no register needs to be defined as implicit-use.
4201 /// If the function cannot determine if an SPR should be marked implicit use or
4202 /// not, it returns false.
4204 /// This function handles cases where an instruction is being modified from taking
4205 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4206 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4207 /// lane of the DPR).
4209 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4210 /// (including the case where the DPR itself is defined), it should not.
4212 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4214 unsigned DReg, unsigned Lane,
4215 unsigned &ImplicitSReg) {
4216 // If the DPR is defined or used already, the other SPR lane will be chained
4217 // correctly, so there is nothing to be done.
4218 if (MI->definesRegister(DReg, TRI) || MI->readsRegister(DReg, TRI)) {
4223 // Otherwise we need to go searching to see if the SPR is set explicitly.
4224 ImplicitSReg = TRI->getSubReg(DReg,
4225 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4226 MachineBasicBlock::LivenessQueryResult LQR =
4227 MI->getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4229 if (LQR == MachineBasicBlock::LQR_Live)
4231 else if (LQR == MachineBasicBlock::LQR_Unknown)
4234 // If the register is known not to be live, there is no need to add an
4241 ARMBaseInstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
4242 unsigned DstReg, SrcReg, DReg;
4244 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
4245 const TargetRegisterInfo *TRI = &getRegisterInfo();
4246 switch (MI->getOpcode()) {
4248 llvm_unreachable("cannot handle opcode!");
4251 if (Domain != ExeNEON)
4254 // Zap the predicate operands.
4255 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4257 // Make sure we've got NEON instructions.
4258 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4260 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4261 DstReg = MI->getOperand(0).getReg();
4262 SrcReg = MI->getOperand(1).getReg();
4264 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4265 MI->RemoveOperand(i-1);
4267 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4268 MI->setDesc(get(ARM::VORRd));
4269 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4274 if (Domain != ExeNEON)
4276 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4278 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4279 DstReg = MI->getOperand(0).getReg();
4280 SrcReg = MI->getOperand(1).getReg();
4282 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4283 MI->RemoveOperand(i-1);
4285 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4287 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4288 // Note that DSrc has been widened and the other lane may be undef, which
4289 // contaminates the entire register.
4290 MI->setDesc(get(ARM::VGETLNi32));
4291 AddDefaultPred(MIB.addReg(DstReg, RegState::Define)
4292 .addReg(DReg, RegState::Undef)
4295 // The old source should be an implicit use, otherwise we might think it
4296 // was dead before here.
4297 MIB.addReg(SrcReg, RegState::Implicit);
4300 if (Domain != ExeNEON)
4302 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4304 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4305 DstReg = MI->getOperand(0).getReg();
4306 SrcReg = MI->getOperand(1).getReg();
4308 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4310 unsigned ImplicitSReg;
4311 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4314 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4315 MI->RemoveOperand(i-1);
4317 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4318 // Again DDst may be undefined at the beginning of this instruction.
4319 MI->setDesc(get(ARM::VSETLNi32));
4320 MIB.addReg(DReg, RegState::Define)
4321 .addReg(DReg, getUndefRegState(!MI->readsRegister(DReg, TRI)))
4324 AddDefaultPred(MIB);
4326 // The narrower destination must be marked as set to keep previous chains
4328 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4329 if (ImplicitSReg != 0)
4330 MIB.addReg(ImplicitSReg, RegState::Implicit);
4334 if (Domain != ExeNEON)
4337 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4338 DstReg = MI->getOperand(0).getReg();
4339 SrcReg = MI->getOperand(1).getReg();
4341 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4342 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4343 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4345 unsigned ImplicitSReg;
4346 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4349 for (unsigned i = MI->getDesc().getNumOperands(); i; --i)
4350 MI->RemoveOperand(i-1);
4353 // Destination can be:
4354 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4355 MI->setDesc(get(ARM::VDUPLN32d));
4356 MIB.addReg(DDst, RegState::Define)
4357 .addReg(DDst, getUndefRegState(!MI->readsRegister(DDst, TRI)))
4359 AddDefaultPred(MIB);
4361 // Neither the source or the destination are naturally represented any
4362 // more, so add them in manually.
4363 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4364 MIB.addReg(SrcReg, RegState::Implicit);
4365 if (ImplicitSReg != 0)
4366 MIB.addReg(ImplicitSReg, RegState::Implicit);
4370 // In general there's no single instruction that can perform an S <-> S
4371 // move in NEON space, but a pair of VEXT instructions *can* do the
4372 // job. It turns out that the VEXTs needed will only use DSrc once, with
4373 // the position based purely on the combination of lane-0 and lane-1
4374 // involved. For example
4375 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4376 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4377 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4378 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4380 // Pattern of the MachineInstrs is:
4381 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4382 MachineInstrBuilder NewMIB;
4383 NewMIB = BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4384 get(ARM::VEXTd32), DDst);
4386 // On the first instruction, both DSrc and DDst may be <undef> if present.
4387 // Specifically when the original instruction didn't have them as an
4389 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4390 bool CurUndef = !MI->readsRegister(CurReg, TRI);
4391 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4393 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4394 CurUndef = !MI->readsRegister(CurReg, TRI);
4395 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4398 AddDefaultPred(NewMIB);
4400 if (SrcLane == DstLane)
4401 NewMIB.addReg(SrcReg, RegState::Implicit);
4403 MI->setDesc(get(ARM::VEXTd32));
4404 MIB.addReg(DDst, RegState::Define);
4406 // On the second instruction, DDst has definitely been defined above, so
4407 // it is not <undef>. DSrc, if present, can be <undef> as above.
4408 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4409 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4410 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4412 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4413 CurUndef = CurReg == DSrc && !MI->readsRegister(CurReg, TRI);
4414 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4417 AddDefaultPred(MIB);
4419 if (SrcLane != DstLane)
4420 MIB.addReg(SrcReg, RegState::Implicit);
4422 // As before, the original destination is no longer represented, add it
4424 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4425 if (ImplicitSReg != 0)
4426 MIB.addReg(ImplicitSReg, RegState::Implicit);
4433 //===----------------------------------------------------------------------===//
4434 // Partial register updates
4435 //===----------------------------------------------------------------------===//
4437 // Swift renames NEON registers with 64-bit granularity. That means any
4438 // instruction writing an S-reg implicitly reads the containing D-reg. The
4439 // problem is mostly avoided by translating f32 operations to v2f32 operations
4440 // on D-registers, but f32 loads are still a problem.
4442 // These instructions can load an f32 into a NEON register:
4444 // VLDRS - Only writes S, partial D update.
4445 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4446 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4448 // FCONSTD can be used as a dependency-breaking instruction.
4449 unsigned ARMBaseInstrInfo::
4450 getPartialRegUpdateClearance(const MachineInstr *MI,
4452 const TargetRegisterInfo *TRI) const {
4453 if (!SwiftPartialUpdateClearance ||
4454 !(Subtarget.isSwift() || Subtarget.isCortexA15()))
4457 assert(TRI && "Need TRI instance");
4459 const MachineOperand &MO = MI->getOperand(OpNum);
4462 unsigned Reg = MO.getReg();
4465 switch(MI->getOpcode()) {
4466 // Normal instructions writing only an S-register.
4471 case ARM::VMOVv4i16:
4472 case ARM::VMOVv2i32:
4473 case ARM::VMOVv2f32:
4474 case ARM::VMOVv1i64:
4475 UseOp = MI->findRegisterUseOperandIdx(Reg, false, TRI);
4478 // Explicitly reads the dependency.
4479 case ARM::VLD1LNd32:
4486 // If this instruction actually reads a value from Reg, there is no unwanted
4488 if (UseOp != -1 && MI->getOperand(UseOp).readsReg())
4491 // We must be able to clobber the whole D-reg.
4492 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4493 // Virtual register must be a foo:ssub_0<def,undef> operand.
4494 if (!MO.getSubReg() || MI->readsVirtualRegister(Reg))
4496 } else if (ARM::SPRRegClass.contains(Reg)) {
4497 // Physical register: MI must define the full D-reg.
4498 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4500 if (!DReg || !MI->definesRegister(DReg, TRI))
4504 // MI has an unwanted D-register dependency.
4505 // Avoid defs in the previous N instructrions.
4506 return SwiftPartialUpdateClearance;
4509 // Break a partial register dependency after getPartialRegUpdateClearance
4510 // returned non-zero.
4511 void ARMBaseInstrInfo::
4512 breakPartialRegDependency(MachineBasicBlock::iterator MI,
4514 const TargetRegisterInfo *TRI) const {
4515 assert(MI && OpNum < MI->getDesc().getNumDefs() && "OpNum is not a def");
4516 assert(TRI && "Need TRI instance");
4518 const MachineOperand &MO = MI->getOperand(OpNum);
4519 unsigned Reg = MO.getReg();
4520 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4521 "Can't break virtual register dependencies.");
4522 unsigned DReg = Reg;
4524 // If MI defines an S-reg, find the corresponding D super-register.
4525 if (ARM::SPRRegClass.contains(Reg)) {
4526 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4527 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4530 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4531 assert(MI->definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4533 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4534 // the full D-register by loading the same value to both lanes. The
4535 // instruction is micro-coded with 2 uops, so don't do this until we can
4536 // properly schedule micro-coded instructions. The dispatcher stalls cause
4537 // too big regressions.
4539 // Insert the dependency-breaking FCONSTD before MI.
4540 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4541 AddDefaultPred(BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
4542 get(ARM::FCONSTD), DReg).addImm(96));
4543 MI->addRegisterKilled(DReg, TRI, true);
4546 bool ARMBaseInstrInfo::hasNOP() const {
4547 return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4550 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4551 if (MI->getNumOperands() < 4)
4553 unsigned ShOpVal = MI->getOperand(3).getImm();
4554 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4555 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4556 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4557 ((ShImm == 1 || ShImm == 2) &&
4558 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4564 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4565 const MachineInstr &MI, unsigned DefIdx,
4566 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4567 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4568 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4570 switch (MI.getOpcode()) {
4572 // dX = VMOVDRR rY, rZ
4574 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4575 // Populate the InputRegs accordingly.
4577 const MachineOperand *MOReg = &MI.getOperand(1);
4578 InputRegs.push_back(
4579 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4581 MOReg = &MI.getOperand(2);
4582 InputRegs.push_back(
4583 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4586 llvm_unreachable("Target dependent opcode missing");
4589 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4590 const MachineInstr &MI, unsigned DefIdx,
4591 RegSubRegPairAndIdx &InputReg) const {
4592 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4593 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4595 switch (MI.getOpcode()) {
4597 // rX, rY = VMOVRRD dZ
4599 // rX = EXTRACT_SUBREG dZ, ssub_0
4600 // rY = EXTRACT_SUBREG dZ, ssub_1
4601 const MachineOperand &MOReg = MI.getOperand(2);
4602 InputReg.Reg = MOReg.getReg();
4603 InputReg.SubReg = MOReg.getSubReg();
4604 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4607 llvm_unreachable("Target dependent opcode missing");
4610 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4611 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4612 RegSubRegPairAndIdx &InsertedReg) const {
4613 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4614 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4616 switch (MI.getOpcode()) {
4617 case ARM::VSETLNi32:
4618 // dX = VSETLNi32 dY, rZ, imm
4619 const MachineOperand &MOBaseReg = MI.getOperand(1);
4620 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4621 const MachineOperand &MOIndex = MI.getOperand(3);
4622 BaseReg.Reg = MOBaseReg.getReg();
4623 BaseReg.SubReg = MOBaseReg.getSubReg();
4625 InsertedReg.Reg = MOInsertedReg.getReg();
4626 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4627 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4630 llvm_unreachable("Target dependent opcode missing");