1 //===-- ARMBaseInstrInfo.cpp - ARM Instruction Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseInstrInfo.h"
15 #include "ARMBaseRegisterInfo.h"
16 #include "ARMConstantPoolValue.h"
17 #include "ARMFeatures.h"
18 #include "ARMHazardRecognizer.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMAddressingModes.h"
22 #include "MCTargetDesc/ARMBaseInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/STLExtras.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/CodeGen/LiveVariables.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFrameInfo.h"
32 #include "llvm/CodeGen/MachineFunction.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineInstrBuilder.h"
35 #include "llvm/CodeGen/MachineMemOperand.h"
36 #include "llvm/CodeGen/MachineOperand.h"
37 #include "llvm/CodeGen/MachineRegisterInfo.h"
38 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
39 #include "llvm/CodeGen/SelectionDAGNodes.h"
40 #include "llvm/CodeGen/TargetSchedule.h"
41 #include "llvm/IR/Attributes.h"
42 #include "llvm/IR/Constants.h"
43 #include "llvm/IR/DebugLoc.h"
44 #include "llvm/IR/Function.h"
45 #include "llvm/IR/GlobalValue.h"
46 #include "llvm/MC/MCAsmInfo.h"
47 #include "llvm/MC/MCInstrDesc.h"
48 #include "llvm/MC/MCInstrItineraries.h"
49 #include "llvm/Support/BranchProbability.h"
50 #include "llvm/Support/Casting.h"
51 #include "llvm/Support/CommandLine.h"
52 #include "llvm/Support/Compiler.h"
53 #include "llvm/Support/Debug.h"
54 #include "llvm/Support/ErrorHandling.h"
55 #include "llvm/Support/raw_ostream.h"
56 #include "llvm/Target/TargetInstrInfo.h"
57 #include "llvm/Target/TargetMachine.h"
58 #include "llvm/Target/TargetRegisterInfo.h"
69 #define DEBUG_TYPE "arm-instrinfo"
71 #define GET_INSTRINFO_CTOR_DTOR
72 #include "ARMGenInstrInfo.inc"
75 EnableARM3Addr("enable-arm-3-addr-conv", cl::Hidden,
76 cl::desc("Enable ARM 2-addr to 3-addr conv"));
78 /// ARM_MLxEntry - Record information about MLA / MLS instructions.
80 uint16_t MLxOpc; // MLA / MLS opcode
81 uint16_t MulOpc; // Expanded multiplication opcode
82 uint16_t AddSubOpc; // Expanded add / sub opcode
83 bool NegAcc; // True if the acc is negated before the add / sub.
84 bool HasLane; // True if instruction has an extra "lane" operand.
87 static const ARM_MLxEntry ARM_MLxTable[] = {
88 // MLxOpc, MulOpc, AddSubOpc, NegAcc, HasLane
90 { ARM::VMLAS, ARM::VMULS, ARM::VADDS, false, false },
91 { ARM::VMLSS, ARM::VMULS, ARM::VSUBS, false, false },
92 { ARM::VMLAD, ARM::VMULD, ARM::VADDD, false, false },
93 { ARM::VMLSD, ARM::VMULD, ARM::VSUBD, false, false },
94 { ARM::VNMLAS, ARM::VNMULS, ARM::VSUBS, true, false },
95 { ARM::VNMLSS, ARM::VMULS, ARM::VSUBS, true, false },
96 { ARM::VNMLAD, ARM::VNMULD, ARM::VSUBD, true, false },
97 { ARM::VNMLSD, ARM::VMULD, ARM::VSUBD, true, false },
100 { ARM::VMLAfd, ARM::VMULfd, ARM::VADDfd, false, false },
101 { ARM::VMLSfd, ARM::VMULfd, ARM::VSUBfd, false, false },
102 { ARM::VMLAfq, ARM::VMULfq, ARM::VADDfq, false, false },
103 { ARM::VMLSfq, ARM::VMULfq, ARM::VSUBfq, false, false },
104 { ARM::VMLAslfd, ARM::VMULslfd, ARM::VADDfd, false, true },
105 { ARM::VMLSslfd, ARM::VMULslfd, ARM::VSUBfd, false, true },
106 { ARM::VMLAslfq, ARM::VMULslfq, ARM::VADDfq, false, true },
107 { ARM::VMLSslfq, ARM::VMULslfq, ARM::VSUBfq, false, true },
110 ARMBaseInstrInfo::ARMBaseInstrInfo(const ARMSubtarget& STI)
111 : ARMGenInstrInfo(ARM::ADJCALLSTACKDOWN, ARM::ADJCALLSTACKUP),
113 for (unsigned i = 0, e = array_lengthof(ARM_MLxTable); i != e; ++i) {
114 if (!MLxEntryMap.insert(std::make_pair(ARM_MLxTable[i].MLxOpc, i)).second)
115 llvm_unreachable("Duplicated entries?");
116 MLxHazardOpcodes.insert(ARM_MLxTable[i].AddSubOpc);
117 MLxHazardOpcodes.insert(ARM_MLxTable[i].MulOpc);
121 // Use a ScoreboardHazardRecognizer for prepass ARM scheduling. TargetInstrImpl
122 // currently defaults to no prepass hazard recognizer.
123 ScheduleHazardRecognizer *
124 ARMBaseInstrInfo::CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
125 const ScheduleDAG *DAG) const {
126 if (usePreRAHazardRecognizer()) {
127 const InstrItineraryData *II =
128 static_cast<const ARMSubtarget *>(STI)->getInstrItineraryData();
129 return new ScoreboardHazardRecognizer(II, DAG, "pre-RA-sched");
131 return TargetInstrInfo::CreateTargetHazardRecognizer(STI, DAG);
134 ScheduleHazardRecognizer *ARMBaseInstrInfo::
135 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
136 const ScheduleDAG *DAG) const {
137 if (Subtarget.isThumb2() || Subtarget.hasVFP2())
138 return (ScheduleHazardRecognizer *)new ARMHazardRecognizer(II, DAG);
139 return TargetInstrInfo::CreateTargetPostRAHazardRecognizer(II, DAG);
142 MachineInstr *ARMBaseInstrInfo::convertToThreeAddress(
143 MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
144 // FIXME: Thumb2 support.
149 MachineFunction &MF = *MI.getParent()->getParent();
150 uint64_t TSFlags = MI.getDesc().TSFlags;
152 switch ((TSFlags & ARMII::IndexModeMask) >> ARMII::IndexModeShift) {
153 default: return nullptr;
154 case ARMII::IndexModePre:
157 case ARMII::IndexModePost:
161 // Try splitting an indexed load/store to an un-indexed one plus an add/sub
163 unsigned MemOpc = getUnindexedOpcode(MI.getOpcode());
167 MachineInstr *UpdateMI = nullptr;
168 MachineInstr *MemMI = nullptr;
169 unsigned AddrMode = (TSFlags & ARMII::AddrModeMask);
170 const MCInstrDesc &MCID = MI.getDesc();
171 unsigned NumOps = MCID.getNumOperands();
172 bool isLoad = !MI.mayStore();
173 const MachineOperand &WB = isLoad ? MI.getOperand(1) : MI.getOperand(0);
174 const MachineOperand &Base = MI.getOperand(2);
175 const MachineOperand &Offset = MI.getOperand(NumOps - 3);
176 unsigned WBReg = WB.getReg();
177 unsigned BaseReg = Base.getReg();
178 unsigned OffReg = Offset.getReg();
179 unsigned OffImm = MI.getOperand(NumOps - 2).getImm();
180 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI.getOperand(NumOps - 1).getImm();
182 default: llvm_unreachable("Unknown indexed op!");
183 case ARMII::AddrMode2: {
184 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub;
185 unsigned Amt = ARM_AM::getAM2Offset(OffImm);
187 if (ARM_AM::getSOImmVal(Amt) == -1)
188 // Can't encode it in a so_imm operand. This transformation will
189 // add more than 1 instruction. Abandon!
191 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
192 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
197 } else if (Amt != 0) {
198 ARM_AM::ShiftOpc ShOpc = ARM_AM::getAM2ShiftOpc(OffImm);
199 unsigned SOOpc = ARM_AM::getSORegOpc(ShOpc, Amt);
200 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
201 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg)
209 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
210 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
217 case ARMII::AddrMode3 : {
218 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub;
219 unsigned Amt = ARM_AM::getAM3Offset(OffImm);
221 // Immediate is 8-bits. It's guaranteed to fit in a so_imm operand.
222 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
223 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg)
229 UpdateMI = BuildMI(MF, MI.getDebugLoc(),
230 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg)
239 std::vector<MachineInstr*> NewMIs;
243 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
248 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
249 .addReg(MI.getOperand(1).getReg())
254 NewMIs.push_back(MemMI);
255 NewMIs.push_back(UpdateMI);
259 BuildMI(MF, MI.getDebugLoc(), get(MemOpc), MI.getOperand(0).getReg())
264 MemMI = BuildMI(MF, MI.getDebugLoc(), get(MemOpc))
265 .addReg(MI.getOperand(1).getReg())
271 UpdateMI->getOperand(0).setIsDead();
272 NewMIs.push_back(UpdateMI);
273 NewMIs.push_back(MemMI);
276 // Transfer LiveVariables states, kill / dead info.
278 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
279 MachineOperand &MO = MI.getOperand(i);
280 if (MO.isReg() && TargetRegisterInfo::isVirtualRegister(MO.getReg())) {
281 unsigned Reg = MO.getReg();
283 LiveVariables::VarInfo &VI = LV->getVarInfo(Reg);
285 MachineInstr *NewMI = (Reg == WBReg) ? UpdateMI : MemMI;
287 LV->addVirtualRegisterDead(Reg, *NewMI);
289 if (MO.isUse() && MO.isKill()) {
290 for (unsigned j = 0; j < 2; ++j) {
291 // Look at the two new MI's in reverse order.
292 MachineInstr *NewMI = NewMIs[j];
293 if (!NewMI->readsRegister(Reg))
295 LV->addVirtualRegisterKilled(Reg, *NewMI);
296 if (VI.removeKill(MI))
297 VI.Kills.push_back(NewMI);
305 MachineBasicBlock::iterator MBBI = MI.getIterator();
306 MFI->insert(MBBI, NewMIs[1]);
307 MFI->insert(MBBI, NewMIs[0]);
312 bool ARMBaseInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
313 MachineBasicBlock *&TBB,
314 MachineBasicBlock *&FBB,
315 SmallVectorImpl<MachineOperand> &Cond,
316 bool AllowModify) const {
320 MachineBasicBlock::iterator I = MBB.end();
321 if (I == MBB.begin())
322 return false; // Empty blocks are easy.
325 // Walk backwards from the end of the basic block until the branch is
326 // analyzed or we give up.
327 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) {
328 // Flag to be raised on unanalyzeable instructions. This is useful in cases
329 // where we want to clean up on the end of the basic block before we bail
331 bool CantAnalyze = false;
333 // Skip over DEBUG values and predicated nonterminators.
334 while (I->isDebugValue() || !I->isTerminator()) {
335 if (I == MBB.begin())
340 if (isIndirectBranchOpcode(I->getOpcode()) ||
341 isJumpTableBranchOpcode(I->getOpcode())) {
342 // Indirect branches and jump tables can't be analyzed, but we still want
343 // to clean up any instructions at the tail of the basic block.
345 } else if (isUncondBranchOpcode(I->getOpcode())) {
346 TBB = I->getOperand(0).getMBB();
347 } else if (isCondBranchOpcode(I->getOpcode())) {
348 // Bail out if we encounter multiple conditional branches.
352 assert(!FBB && "FBB should have been null.");
354 TBB = I->getOperand(0).getMBB();
355 Cond.push_back(I->getOperand(1));
356 Cond.push_back(I->getOperand(2));
357 } else if (I->isReturn()) {
358 // Returns can't be analyzed, but we should run cleanup.
359 CantAnalyze = !isPredicated(*I);
361 // We encountered other unrecognized terminator. Bail out immediately.
365 // Cleanup code - to be run for unpredicated unconditional branches and
367 if (!isPredicated(*I) &&
368 (isUncondBranchOpcode(I->getOpcode()) ||
369 isIndirectBranchOpcode(I->getOpcode()) ||
370 isJumpTableBranchOpcode(I->getOpcode()) ||
372 // Forget any previous condition branch information - it no longer applies.
376 // If we can modify the function, delete everything below this
377 // unconditional branch.
379 MachineBasicBlock::iterator DI = std::next(I);
380 while (DI != MBB.end()) {
381 MachineInstr &InstToDelete = *DI;
383 InstToDelete.eraseFromParent();
391 if (I == MBB.begin())
397 // We made it past the terminators without bailing out - we must have
398 // analyzed this branch successfully.
402 unsigned ARMBaseInstrInfo::removeBranch(MachineBasicBlock &MBB,
403 int *BytesRemoved) const {
404 assert(!BytesRemoved && "code size not handled");
406 MachineBasicBlock::iterator I = MBB.getLastNonDebugInstr();
410 if (!isUncondBranchOpcode(I->getOpcode()) &&
411 !isCondBranchOpcode(I->getOpcode()))
414 // Remove the branch.
415 I->eraseFromParent();
419 if (I == MBB.begin()) return 1;
421 if (!isCondBranchOpcode(I->getOpcode()))
424 // Remove the branch.
425 I->eraseFromParent();
429 unsigned ARMBaseInstrInfo::insertBranch(MachineBasicBlock &MBB,
430 MachineBasicBlock *TBB,
431 MachineBasicBlock *FBB,
432 ArrayRef<MachineOperand> Cond,
434 int *BytesAdded) const {
435 assert(!BytesAdded && "code size not handled");
436 ARMFunctionInfo *AFI = MBB.getParent()->getInfo<ARMFunctionInfo>();
437 int BOpc = !AFI->isThumbFunction()
438 ? ARM::B : (AFI->isThumb2Function() ? ARM::t2B : ARM::tB);
439 int BccOpc = !AFI->isThumbFunction()
440 ? ARM::Bcc : (AFI->isThumb2Function() ? ARM::t2Bcc : ARM::tBcc);
441 bool isThumb = AFI->isThumbFunction() || AFI->isThumb2Function();
443 // Shouldn't be a fall through.
444 assert(TBB && "insertBranch must not be told to insert a fallthrough");
445 assert((Cond.size() == 2 || Cond.size() == 0) &&
446 "ARM branch conditions have two components!");
448 // For conditional branches, we use addOperand to preserve CPSR flags.
451 if (Cond.empty()) { // Unconditional branch?
453 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB).add(predOps(ARMCC::AL));
455 BuildMI(&MBB, DL, get(BOpc)).addMBB(TBB);
457 BuildMI(&MBB, DL, get(BccOpc))
459 .addImm(Cond[0].getImm())
464 // Two-way conditional branch.
465 BuildMI(&MBB, DL, get(BccOpc))
467 .addImm(Cond[0].getImm())
470 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB).add(predOps(ARMCC::AL));
472 BuildMI(&MBB, DL, get(BOpc)).addMBB(FBB);
476 bool ARMBaseInstrInfo::
477 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
478 ARMCC::CondCodes CC = (ARMCC::CondCodes)(int)Cond[0].getImm();
479 Cond[0].setImm(ARMCC::getOppositeCondition(CC));
483 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
485 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
486 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
487 while (++I != E && I->isInsideBundle()) {
488 int PIdx = I->findFirstPredOperandIdx();
489 if (PIdx != -1 && I->getOperand(PIdx).getImm() != ARMCC::AL)
495 int PIdx = MI.findFirstPredOperandIdx();
496 return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
499 bool ARMBaseInstrInfo::PredicateInstruction(
500 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
501 unsigned Opc = MI.getOpcode();
502 if (isUncondBranchOpcode(Opc)) {
503 MI.setDesc(get(getMatchingCondBranchOpcode(Opc)));
504 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
505 .addImm(Pred[0].getImm())
506 .addReg(Pred[1].getReg());
510 int PIdx = MI.findFirstPredOperandIdx();
512 MachineOperand &PMO = MI.getOperand(PIdx);
513 PMO.setImm(Pred[0].getImm());
514 MI.getOperand(PIdx+1).setReg(Pred[1].getReg());
520 bool ARMBaseInstrInfo::SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
521 ArrayRef<MachineOperand> Pred2) const {
522 if (Pred1.size() > 2 || Pred2.size() > 2)
525 ARMCC::CondCodes CC1 = (ARMCC::CondCodes)Pred1[0].getImm();
526 ARMCC::CondCodes CC2 = (ARMCC::CondCodes)Pred2[0].getImm();
536 return CC2 == ARMCC::HI;
538 return CC2 == ARMCC::LO || CC2 == ARMCC::EQ;
540 return CC2 == ARMCC::GT;
542 return CC2 == ARMCC::LT;
546 bool ARMBaseInstrInfo::DefinesPredicate(
547 MachineInstr &MI, std::vector<MachineOperand> &Pred) const {
549 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
550 const MachineOperand &MO = MI.getOperand(i);
551 if ((MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) ||
552 (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)) {
561 static bool isCPSRDefined(const MachineInstr *MI) {
562 for (const auto &MO : MI->operands())
563 if (MO.isReg() && MO.getReg() == ARM::CPSR && MO.isDef() && !MO.isDead())
568 static bool isEligibleForITBlock(const MachineInstr *MI) {
569 switch (MI->getOpcode()) {
570 default: return true;
571 case ARM::tADC: // ADC (register) T1
572 case ARM::tADDi3: // ADD (immediate) T1
573 case ARM::tADDi8: // ADD (immediate) T2
574 case ARM::tADDrr: // ADD (register) T1
575 case ARM::tAND: // AND (register) T1
576 case ARM::tASRri: // ASR (immediate) T1
577 case ARM::tASRrr: // ASR (register) T1
578 case ARM::tBIC: // BIC (register) T1
579 case ARM::tEOR: // EOR (register) T1
580 case ARM::tLSLri: // LSL (immediate) T1
581 case ARM::tLSLrr: // LSL (register) T1
582 case ARM::tLSRri: // LSR (immediate) T1
583 case ARM::tLSRrr: // LSR (register) T1
584 case ARM::tMUL: // MUL T1
585 case ARM::tMVN: // MVN (register) T1
586 case ARM::tORR: // ORR (register) T1
587 case ARM::tROR: // ROR (register) T1
588 case ARM::tRSB: // RSB (immediate) T1
589 case ARM::tSBC: // SBC (register) T1
590 case ARM::tSUBi3: // SUB (immediate) T1
591 case ARM::tSUBi8: // SUB (immediate) T2
592 case ARM::tSUBrr: // SUB (register) T1
593 return !isCPSRDefined(MI);
597 /// isPredicable - Return true if the specified instruction can be predicated.
598 /// By default, this returns true for every instruction with a
599 /// PredicateOperand.
600 bool ARMBaseInstrInfo::isPredicable(const MachineInstr &MI) const {
601 if (!MI.isPredicable())
607 if (!isEligibleForITBlock(&MI))
610 const ARMFunctionInfo *AFI =
611 MI.getParent()->getParent()->getInfo<ARMFunctionInfo>();
613 if (AFI->isThumb2Function()) {
614 if (getSubtarget().restrictIT())
615 return isV8EligibleForIT(&MI);
616 } else { // non-Thumb
617 if ((MI.getDesc().TSFlags & ARMII::DomainMask) == ARMII::DomainNEON)
626 template <> bool IsCPSRDead<MachineInstr>(const MachineInstr *MI) {
627 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
628 const MachineOperand &MO = MI->getOperand(i);
629 if (!MO.isReg() || MO.isUndef() || MO.isUse())
631 if (MO.getReg() != ARM::CPSR)
636 // all definitions of CPSR are dead
640 } // end namespace llvm
642 /// GetInstSize - Return the size of the specified MachineInstr.
644 unsigned ARMBaseInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
645 const MachineBasicBlock &MBB = *MI.getParent();
646 const MachineFunction *MF = MBB.getParent();
647 const MCAsmInfo *MAI = MF->getTarget().getMCAsmInfo();
649 const MCInstrDesc &MCID = MI.getDesc();
651 return MCID.getSize();
653 // If this machine instr is an inline asm, measure it.
654 if (MI.getOpcode() == ARM::INLINEASM)
655 return getInlineAsmLength(MI.getOperand(0).getSymbolName(), *MAI);
656 unsigned Opc = MI.getOpcode();
659 // pseudo-instruction sizes are zero.
661 case TargetOpcode::BUNDLE:
662 return getInstBundleLength(MI);
663 case ARM::MOVi16_ga_pcrel:
664 case ARM::MOVTi16_ga_pcrel:
665 case ARM::t2MOVi16_ga_pcrel:
666 case ARM::t2MOVTi16_ga_pcrel:
669 case ARM::t2MOVi32imm:
671 case ARM::CONSTPOOL_ENTRY:
672 case ARM::JUMPTABLE_INSTS:
673 case ARM::JUMPTABLE_ADDRS:
674 case ARM::JUMPTABLE_TBB:
675 case ARM::JUMPTABLE_TBH:
676 // If this machine instr is a constant pool entry, its size is recorded as
678 return MI.getOperand(2).getImm();
679 case ARM::Int_eh_sjlj_longjmp:
681 case ARM::tInt_eh_sjlj_longjmp:
683 case ARM::tInt_WIN_eh_sjlj_longjmp:
685 case ARM::Int_eh_sjlj_setjmp:
686 case ARM::Int_eh_sjlj_setjmp_nofp:
688 case ARM::tInt_eh_sjlj_setjmp:
689 case ARM::t2Int_eh_sjlj_setjmp:
690 case ARM::t2Int_eh_sjlj_setjmp_nofp:
693 return MI.getOperand(1).getImm();
697 unsigned ARMBaseInstrInfo::getInstBundleLength(const MachineInstr &MI) const {
699 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
700 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
701 while (++I != E && I->isInsideBundle()) {
702 assert(!I->isBundle() && "No nested bundle!");
703 Size += getInstSizeInBytes(*I);
708 void ARMBaseInstrInfo::copyFromCPSR(MachineBasicBlock &MBB,
709 MachineBasicBlock::iterator I,
710 unsigned DestReg, bool KillSrc,
711 const ARMSubtarget &Subtarget) const {
712 unsigned Opc = Subtarget.isThumb()
713 ? (Subtarget.isMClass() ? ARM::t2MRS_M : ARM::t2MRS_AR)
716 MachineInstrBuilder MIB =
717 BuildMI(MBB, I, I->getDebugLoc(), get(Opc), DestReg);
719 // There is only 1 A/R class MRS instruction, and it always refers to
720 // APSR. However, there are lots of other possibilities on M-class cores.
721 if (Subtarget.isMClass())
724 MIB.add(predOps(ARMCC::AL))
725 .addReg(ARM::CPSR, RegState::Implicit | getKillRegState(KillSrc));
728 void ARMBaseInstrInfo::copyToCPSR(MachineBasicBlock &MBB,
729 MachineBasicBlock::iterator I,
730 unsigned SrcReg, bool KillSrc,
731 const ARMSubtarget &Subtarget) const {
732 unsigned Opc = Subtarget.isThumb()
733 ? (Subtarget.isMClass() ? ARM::t2MSR_M : ARM::t2MSR_AR)
736 MachineInstrBuilder MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Opc));
738 if (Subtarget.isMClass())
743 MIB.addReg(SrcReg, getKillRegState(KillSrc))
744 .add(predOps(ARMCC::AL))
745 .addReg(ARM::CPSR, RegState::Implicit | RegState::Define);
748 void ARMBaseInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
749 MachineBasicBlock::iterator I,
750 const DebugLoc &DL, unsigned DestReg,
751 unsigned SrcReg, bool KillSrc) const {
752 bool GPRDest = ARM::GPRRegClass.contains(DestReg);
753 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg);
755 if (GPRDest && GPRSrc) {
756 BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg)
757 .addReg(SrcReg, getKillRegState(KillSrc))
758 .add(predOps(ARMCC::AL))
763 bool SPRDest = ARM::SPRRegClass.contains(DestReg);
764 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg);
767 if (SPRDest && SPRSrc)
769 else if (GPRDest && SPRSrc)
771 else if (SPRDest && GPRSrc)
773 else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && !Subtarget.isFPOnlySP())
775 else if (ARM::QPRRegClass.contains(DestReg, SrcReg))
779 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg);
780 MIB.addReg(SrcReg, getKillRegState(KillSrc));
781 if (Opc == ARM::VORRq)
782 MIB.addReg(SrcReg, getKillRegState(KillSrc));
783 MIB.add(predOps(ARMCC::AL));
787 // Handle register classes that require multiple instructions.
788 unsigned BeginIdx = 0;
789 unsigned SubRegs = 0;
792 // Use VORRq when possible.
793 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) {
795 BeginIdx = ARM::qsub_0;
797 } else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) {
799 BeginIdx = ARM::qsub_0;
801 // Fall back to VMOVD.
802 } else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) {
804 BeginIdx = ARM::dsub_0;
806 } else if (ARM::DTripleRegClass.contains(DestReg, SrcReg)) {
808 BeginIdx = ARM::dsub_0;
810 } else if (ARM::DQuadRegClass.contains(DestReg, SrcReg)) {
812 BeginIdx = ARM::dsub_0;
814 } else if (ARM::GPRPairRegClass.contains(DestReg, SrcReg)) {
815 Opc = Subtarget.isThumb2() ? ARM::tMOVr : ARM::MOVr;
816 BeginIdx = ARM::gsub_0;
818 } else if (ARM::DPairSpcRegClass.contains(DestReg, SrcReg)) {
820 BeginIdx = ARM::dsub_0;
823 } else if (ARM::DTripleSpcRegClass.contains(DestReg, SrcReg)) {
825 BeginIdx = ARM::dsub_0;
828 } else if (ARM::DQuadSpcRegClass.contains(DestReg, SrcReg)) {
830 BeginIdx = ARM::dsub_0;
833 } else if (ARM::DPRRegClass.contains(DestReg, SrcReg) && Subtarget.isFPOnlySP()) {
835 BeginIdx = ARM::ssub_0;
837 } else if (SrcReg == ARM::CPSR) {
838 copyFromCPSR(MBB, I, DestReg, KillSrc, Subtarget);
840 } else if (DestReg == ARM::CPSR) {
841 copyToCPSR(MBB, I, SrcReg, KillSrc, Subtarget);
845 assert(Opc && "Impossible reg-to-reg copy");
847 const TargetRegisterInfo *TRI = &getRegisterInfo();
848 MachineInstrBuilder Mov;
850 // Copy register tuples backward when the first Dest reg overlaps with SrcReg.
851 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
852 BeginIdx = BeginIdx + ((SubRegs - 1) * Spacing);
856 SmallSet<unsigned, 4> DstRegs;
858 for (unsigned i = 0; i != SubRegs; ++i) {
859 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
860 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
861 assert(Dst && Src && "Bad sub-register");
863 assert(!DstRegs.count(Src) && "destructive vector copy");
866 Mov = BuildMI(MBB, I, I->getDebugLoc(), get(Opc), Dst).addReg(Src);
867 // VORR takes two source operands.
868 if (Opc == ARM::VORRq)
870 Mov = Mov.add(predOps(ARMCC::AL));
872 if (Opc == ARM::MOVr)
873 Mov = Mov.add(condCodeOp());
875 // Add implicit super-register defs and kills to the last instruction.
876 Mov->addRegisterDefined(DestReg, TRI);
878 Mov->addRegisterKilled(SrcReg, TRI);
881 const MachineInstrBuilder &
882 ARMBaseInstrInfo::AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
883 unsigned SubIdx, unsigned State,
884 const TargetRegisterInfo *TRI) const {
886 return MIB.addReg(Reg, State);
888 if (TargetRegisterInfo::isPhysicalRegister(Reg))
889 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
890 return MIB.addReg(Reg, State, SubIdx);
893 void ARMBaseInstrInfo::
894 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
895 unsigned SrcReg, bool isKill, int FI,
896 const TargetRegisterClass *RC,
897 const TargetRegisterInfo *TRI) const {
899 if (I != MBB.end()) DL = I->getDebugLoc();
900 MachineFunction &MF = *MBB.getParent();
901 MachineFrameInfo &MFI = MF.getFrameInfo();
902 unsigned Align = MFI.getObjectAlignment(FI);
904 MachineMemOperand *MMO = MF.getMachineMemOperand(
905 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOStore,
906 MFI.getObjectSize(FI), Align);
908 switch (RC->getSize()) {
910 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
911 BuildMI(MBB, I, DL, get(ARM::STRi12))
912 .addReg(SrcReg, getKillRegState(isKill))
916 .add(predOps(ARMCC::AL));
917 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
918 BuildMI(MBB, I, DL, get(ARM::VSTRS))
919 .addReg(SrcReg, getKillRegState(isKill))
923 .add(predOps(ARMCC::AL));
925 llvm_unreachable("Unknown reg class!");
928 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
929 BuildMI(MBB, I, DL, get(ARM::VSTRD))
930 .addReg(SrcReg, getKillRegState(isKill))
934 .add(predOps(ARMCC::AL));
935 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
936 if (Subtarget.hasV5TEOps()) {
937 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STRD));
938 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
939 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
940 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
941 .add(predOps(ARMCC::AL));
943 // Fallback to STM instruction, which has existed since the dawn of
945 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::STMIA))
948 .add(predOps(ARMCC::AL));
949 AddDReg(MIB, SrcReg, ARM::gsub_0, getKillRegState(isKill), TRI);
950 AddDReg(MIB, SrcReg, ARM::gsub_1, 0, TRI);
953 llvm_unreachable("Unknown reg class!");
956 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
957 // Use aligned spills if the stack can be realigned.
958 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
959 BuildMI(MBB, I, DL, get(ARM::VST1q64))
962 .addReg(SrcReg, getKillRegState(isKill))
964 .add(predOps(ARMCC::AL));
966 BuildMI(MBB, I, DL, get(ARM::VSTMQIA))
967 .addReg(SrcReg, getKillRegState(isKill))
970 .add(predOps(ARMCC::AL));
973 llvm_unreachable("Unknown reg class!");
976 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
977 // Use aligned spills if the stack can be realigned.
978 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
979 BuildMI(MBB, I, DL, get(ARM::VST1d64TPseudo))
982 .addReg(SrcReg, getKillRegState(isKill))
984 .add(predOps(ARMCC::AL));
986 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
988 .add(predOps(ARMCC::AL))
990 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
991 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
992 AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
995 llvm_unreachable("Unknown reg class!");
998 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
999 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1000 // FIXME: It's possible to only store part of the QQ register if the
1001 // spilled def has a sub-register index.
1002 BuildMI(MBB, I, DL, get(ARM::VST1d64QPseudo))
1005 .addReg(SrcReg, getKillRegState(isKill))
1007 .add(predOps(ARMCC::AL));
1009 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
1011 .add(predOps(ARMCC::AL))
1012 .addMemOperand(MMO);
1013 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1014 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1015 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1016 AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1019 llvm_unreachable("Unknown reg class!");
1022 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1023 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VSTMDIA))
1025 .add(predOps(ARMCC::AL))
1026 .addMemOperand(MMO);
1027 MIB = AddDReg(MIB, SrcReg, ARM::dsub_0, getKillRegState(isKill), TRI);
1028 MIB = AddDReg(MIB, SrcReg, ARM::dsub_1, 0, TRI);
1029 MIB = AddDReg(MIB, SrcReg, ARM::dsub_2, 0, TRI);
1030 MIB = AddDReg(MIB, SrcReg, ARM::dsub_3, 0, TRI);
1031 MIB = AddDReg(MIB, SrcReg, ARM::dsub_4, 0, TRI);
1032 MIB = AddDReg(MIB, SrcReg, ARM::dsub_5, 0, TRI);
1033 MIB = AddDReg(MIB, SrcReg, ARM::dsub_6, 0, TRI);
1034 AddDReg(MIB, SrcReg, ARM::dsub_7, 0, TRI);
1036 llvm_unreachable("Unknown reg class!");
1039 llvm_unreachable("Unknown reg class!");
1043 unsigned ARMBaseInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
1044 int &FrameIndex) const {
1045 switch (MI.getOpcode()) {
1048 case ARM::t2STRs: // FIXME: don't use t2STRs to access frame.
1049 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1050 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1051 MI.getOperand(3).getImm() == 0) {
1052 FrameIndex = MI.getOperand(1).getIndex();
1053 return MI.getOperand(0).getReg();
1061 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1062 MI.getOperand(2).getImm() == 0) {
1063 FrameIndex = MI.getOperand(1).getIndex();
1064 return MI.getOperand(0).getReg();
1068 case ARM::VST1d64TPseudo:
1069 case ARM::VST1d64QPseudo:
1070 if (MI.getOperand(0).isFI() && MI.getOperand(2).getSubReg() == 0) {
1071 FrameIndex = MI.getOperand(0).getIndex();
1072 return MI.getOperand(2).getReg();
1076 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1077 FrameIndex = MI.getOperand(1).getIndex();
1078 return MI.getOperand(0).getReg();
1086 unsigned ARMBaseInstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
1087 int &FrameIndex) const {
1088 const MachineMemOperand *Dummy;
1089 return MI.mayStore() && hasStoreToStackSlot(MI, Dummy, FrameIndex);
1092 void ARMBaseInstrInfo::
1093 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
1094 unsigned DestReg, int FI,
1095 const TargetRegisterClass *RC,
1096 const TargetRegisterInfo *TRI) const {
1098 if (I != MBB.end()) DL = I->getDebugLoc();
1099 MachineFunction &MF = *MBB.getParent();
1100 MachineFrameInfo &MFI = MF.getFrameInfo();
1101 unsigned Align = MFI.getObjectAlignment(FI);
1102 MachineMemOperand *MMO = MF.getMachineMemOperand(
1103 MachinePointerInfo::getFixedStack(MF, FI), MachineMemOperand::MOLoad,
1104 MFI.getObjectSize(FI), Align);
1106 switch (RC->getSize()) {
1108 if (ARM::GPRRegClass.hasSubClassEq(RC)) {
1109 BuildMI(MBB, I, DL, get(ARM::LDRi12), DestReg)
1113 .add(predOps(ARMCC::AL));
1115 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) {
1116 BuildMI(MBB, I, DL, get(ARM::VLDRS), DestReg)
1120 .add(predOps(ARMCC::AL));
1122 llvm_unreachable("Unknown reg class!");
1125 if (ARM::DPRRegClass.hasSubClassEq(RC)) {
1126 BuildMI(MBB, I, DL, get(ARM::VLDRD), DestReg)
1130 .add(predOps(ARMCC::AL));
1131 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) {
1132 MachineInstrBuilder MIB;
1134 if (Subtarget.hasV5TEOps()) {
1135 MIB = BuildMI(MBB, I, DL, get(ARM::LDRD));
1136 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1137 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1138 MIB.addFrameIndex(FI).addReg(0).addImm(0).addMemOperand(MMO)
1139 .add(predOps(ARMCC::AL));
1141 // Fallback to LDM instruction, which has existed since the dawn of
1143 MIB = BuildMI(MBB, I, DL, get(ARM::LDMIA))
1146 .add(predOps(ARMCC::AL));
1147 MIB = AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI);
1148 MIB = AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI);
1151 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1152 MIB.addReg(DestReg, RegState::ImplicitDefine);
1154 llvm_unreachable("Unknown reg class!");
1157 if (ARM::DPairRegClass.hasSubClassEq(RC)) {
1158 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1159 BuildMI(MBB, I, DL, get(ARM::VLD1q64), DestReg)
1163 .add(predOps(ARMCC::AL));
1165 BuildMI(MBB, I, DL, get(ARM::VLDMQIA), DestReg)
1168 .add(predOps(ARMCC::AL));
1171 llvm_unreachable("Unknown reg class!");
1174 if (ARM::DTripleRegClass.hasSubClassEq(RC)) {
1175 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1176 BuildMI(MBB, I, DL, get(ARM::VLD1d64TPseudo), DestReg)
1180 .add(predOps(ARMCC::AL));
1182 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1185 .add(predOps(ARMCC::AL));
1186 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1187 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1188 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1189 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1190 MIB.addReg(DestReg, RegState::ImplicitDefine);
1193 llvm_unreachable("Unknown reg class!");
1196 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) {
1197 if (Align >= 16 && getRegisterInfo().canRealignStack(MF)) {
1198 BuildMI(MBB, I, DL, get(ARM::VLD1d64QPseudo), DestReg)
1202 .add(predOps(ARMCC::AL));
1204 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1206 .add(predOps(ARMCC::AL))
1207 .addMemOperand(MMO);
1208 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1209 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1210 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1211 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1212 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1213 MIB.addReg(DestReg, RegState::ImplicitDefine);
1216 llvm_unreachable("Unknown reg class!");
1219 if (ARM::QQQQPRRegClass.hasSubClassEq(RC)) {
1220 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(ARM::VLDMDIA))
1222 .add(predOps(ARMCC::AL))
1223 .addMemOperand(MMO);
1224 MIB = AddDReg(MIB, DestReg, ARM::dsub_0, RegState::DefineNoRead, TRI);
1225 MIB = AddDReg(MIB, DestReg, ARM::dsub_1, RegState::DefineNoRead, TRI);
1226 MIB = AddDReg(MIB, DestReg, ARM::dsub_2, RegState::DefineNoRead, TRI);
1227 MIB = AddDReg(MIB, DestReg, ARM::dsub_3, RegState::DefineNoRead, TRI);
1228 MIB = AddDReg(MIB, DestReg, ARM::dsub_4, RegState::DefineNoRead, TRI);
1229 MIB = AddDReg(MIB, DestReg, ARM::dsub_5, RegState::DefineNoRead, TRI);
1230 MIB = AddDReg(MIB, DestReg, ARM::dsub_6, RegState::DefineNoRead, TRI);
1231 MIB = AddDReg(MIB, DestReg, ARM::dsub_7, RegState::DefineNoRead, TRI);
1232 if (TargetRegisterInfo::isPhysicalRegister(DestReg))
1233 MIB.addReg(DestReg, RegState::ImplicitDefine);
1235 llvm_unreachable("Unknown reg class!");
1238 llvm_unreachable("Unknown regclass!");
1242 unsigned ARMBaseInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
1243 int &FrameIndex) const {
1244 switch (MI.getOpcode()) {
1247 case ARM::t2LDRs: // FIXME: don't use t2LDRs to access frame.
1248 if (MI.getOperand(1).isFI() && MI.getOperand(2).isReg() &&
1249 MI.getOperand(3).isImm() && MI.getOperand(2).getReg() == 0 &&
1250 MI.getOperand(3).getImm() == 0) {
1251 FrameIndex = MI.getOperand(1).getIndex();
1252 return MI.getOperand(0).getReg();
1260 if (MI.getOperand(1).isFI() && MI.getOperand(2).isImm() &&
1261 MI.getOperand(2).getImm() == 0) {
1262 FrameIndex = MI.getOperand(1).getIndex();
1263 return MI.getOperand(0).getReg();
1267 case ARM::VLD1d64TPseudo:
1268 case ARM::VLD1d64QPseudo:
1269 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1270 FrameIndex = MI.getOperand(1).getIndex();
1271 return MI.getOperand(0).getReg();
1275 if (MI.getOperand(1).isFI() && MI.getOperand(0).getSubReg() == 0) {
1276 FrameIndex = MI.getOperand(1).getIndex();
1277 return MI.getOperand(0).getReg();
1285 unsigned ARMBaseInstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
1286 int &FrameIndex) const {
1287 const MachineMemOperand *Dummy;
1288 return MI.mayLoad() && hasLoadFromStackSlot(MI, Dummy, FrameIndex);
1291 /// \brief Expands MEMCPY to either LDMIA/STMIA or LDMIA_UPD/STMID_UPD
1292 /// depending on whether the result is used.
1293 void ARMBaseInstrInfo::expandMEMCPY(MachineBasicBlock::iterator MI) const {
1294 bool isThumb1 = Subtarget.isThumb1Only();
1295 bool isThumb2 = Subtarget.isThumb2();
1296 const ARMBaseInstrInfo *TII = Subtarget.getInstrInfo();
1298 DebugLoc dl = MI->getDebugLoc();
1299 MachineBasicBlock *BB = MI->getParent();
1301 MachineInstrBuilder LDM, STM;
1302 if (isThumb1 || !MI->getOperand(1).isDead()) {
1303 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA_UPD
1304 : isThumb1 ? ARM::tLDMIA_UPD
1306 .add(MI->getOperand(1));
1308 LDM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2LDMIA : ARM::LDMIA));
1311 if (isThumb1 || !MI->getOperand(0).isDead()) {
1312 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA_UPD
1313 : isThumb1 ? ARM::tSTMIA_UPD
1315 .add(MI->getOperand(0));
1317 STM = BuildMI(*BB, MI, dl, TII->get(isThumb2 ? ARM::t2STMIA : ARM::STMIA));
1320 LDM.add(MI->getOperand(3)).add(predOps(ARMCC::AL));
1321 STM.add(MI->getOperand(2)).add(predOps(ARMCC::AL));
1323 // Sort the scratch registers into ascending order.
1324 const TargetRegisterInfo &TRI = getRegisterInfo();
1325 SmallVector<unsigned, 6> ScratchRegs;
1326 for(unsigned I = 5; I < MI->getNumOperands(); ++I)
1327 ScratchRegs.push_back(MI->getOperand(I).getReg());
1328 std::sort(ScratchRegs.begin(), ScratchRegs.end(),
1329 [&TRI](const unsigned &Reg1,
1330 const unsigned &Reg2) -> bool {
1331 return TRI.getEncodingValue(Reg1) <
1332 TRI.getEncodingValue(Reg2);
1335 for (const auto &Reg : ScratchRegs) {
1336 LDM.addReg(Reg, RegState::Define);
1337 STM.addReg(Reg, RegState::Kill);
1343 bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1344 if (MI.getOpcode() == TargetOpcode::LOAD_STACK_GUARD) {
1345 assert(getSubtarget().getTargetTriple().isOSBinFormatMachO() &&
1346 "LOAD_STACK_GUARD currently supported only for MachO.");
1347 expandLoadStackGuard(MI);
1348 MI.getParent()->erase(MI);
1352 if (MI.getOpcode() == ARM::MEMCPY) {
1357 // This hook gets to expand COPY instructions before they become
1358 // copyPhysReg() calls. Look for VMOVS instructions that can legally be
1359 // widened to VMOVD. We prefer the VMOVD when possible because it may be
1360 // changed into a VORR that can go down the NEON pipeline.
1361 if (!MI.isCopy() || Subtarget.dontWidenVMOVS() || Subtarget.isFPOnlySP())
1364 // Look for a copy between even S-registers. That is where we keep floats
1365 // when using NEON v2f32 instructions for f32 arithmetic.
1366 unsigned DstRegS = MI.getOperand(0).getReg();
1367 unsigned SrcRegS = MI.getOperand(1).getReg();
1368 if (!ARM::SPRRegClass.contains(DstRegS, SrcRegS))
1371 const TargetRegisterInfo *TRI = &getRegisterInfo();
1372 unsigned DstRegD = TRI->getMatchingSuperReg(DstRegS, ARM::ssub_0,
1374 unsigned SrcRegD = TRI->getMatchingSuperReg(SrcRegS, ARM::ssub_0,
1376 if (!DstRegD || !SrcRegD)
1379 // We want to widen this into a DstRegD = VMOVD SrcRegD copy. This is only
1380 // legal if the COPY already defines the full DstRegD, and it isn't a
1381 // sub-register insertion.
1382 if (!MI.definesRegister(DstRegD, TRI) || MI.readsRegister(DstRegD, TRI))
1385 // A dead copy shouldn't show up here, but reject it just in case.
1386 if (MI.getOperand(0).isDead())
1389 // All clear, widen the COPY.
1390 DEBUG(dbgs() << "widening: " << MI);
1391 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
1393 // Get rid of the old <imp-def> of DstRegD. Leave it if it defines a Q-reg
1394 // or some other super-register.
1395 int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD);
1396 if (ImpDefIdx != -1)
1397 MI.RemoveOperand(ImpDefIdx);
1399 // Change the opcode and operands.
1400 MI.setDesc(get(ARM::VMOVD));
1401 MI.getOperand(0).setReg(DstRegD);
1402 MI.getOperand(1).setReg(SrcRegD);
1403 MIB.add(predOps(ARMCC::AL));
1405 // We are now reading SrcRegD instead of SrcRegS. This may upset the
1406 // register scavenger and machine verifier, so we need to indicate that we
1407 // are reading an undefined value from SrcRegD, but a proper value from
1409 MI.getOperand(1).setIsUndef();
1410 MIB.addReg(SrcRegS, RegState::Implicit);
1412 // SrcRegD may actually contain an unrelated value in the ssub_1
1413 // sub-register. Don't kill it. Only kill the ssub_0 sub-register.
1414 if (MI.getOperand(1).isKill()) {
1415 MI.getOperand(1).setIsKill(false);
1416 MI.addRegisterKilled(SrcRegS, TRI, true);
1419 DEBUG(dbgs() << "replaced by: " << MI);
1423 /// Create a copy of a const pool value. Update CPI to the new index and return
1425 static unsigned duplicateCPV(MachineFunction &MF, unsigned &CPI) {
1426 MachineConstantPool *MCP = MF.getConstantPool();
1427 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
1429 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPI];
1430 assert(MCPE.isMachineConstantPoolEntry() &&
1431 "Expecting a machine constantpool entry!");
1432 ARMConstantPoolValue *ACPV =
1433 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
1435 unsigned PCLabelId = AFI->createPICLabelUId();
1436 ARMConstantPoolValue *NewCPV = nullptr;
1438 // FIXME: The below assumes PIC relocation model and that the function
1439 // is Thumb mode (t1 or t2). PCAdjustment would be 8 for ARM mode PIC, and
1440 // zero for non-PIC in ARM or Thumb. The callers are all of thumb LDR
1441 // instructions, so that's probably OK, but is PIC always correct when
1443 if (ACPV->isGlobalValue())
1444 NewCPV = ARMConstantPoolConstant::Create(
1445 cast<ARMConstantPoolConstant>(ACPV)->getGV(), PCLabelId, ARMCP::CPValue,
1446 4, ACPV->getModifier(), ACPV->mustAddCurrentAddress());
1447 else if (ACPV->isExtSymbol())
1448 NewCPV = ARMConstantPoolSymbol::
1449 Create(MF.getFunction()->getContext(),
1450 cast<ARMConstantPoolSymbol>(ACPV)->getSymbol(), PCLabelId, 4);
1451 else if (ACPV->isBlockAddress())
1452 NewCPV = ARMConstantPoolConstant::
1453 Create(cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress(), PCLabelId,
1454 ARMCP::CPBlockAddress, 4);
1455 else if (ACPV->isLSDA())
1456 NewCPV = ARMConstantPoolConstant::Create(MF.getFunction(), PCLabelId,
1458 else if (ACPV->isMachineBasicBlock())
1459 NewCPV = ARMConstantPoolMBB::
1460 Create(MF.getFunction()->getContext(),
1461 cast<ARMConstantPoolMBB>(ACPV)->getMBB(), PCLabelId, 4);
1463 llvm_unreachable("Unexpected ARM constantpool value type!!");
1464 CPI = MCP->getConstantPoolIndex(NewCPV, MCPE.getAlignment());
1468 void ARMBaseInstrInfo::reMaterialize(MachineBasicBlock &MBB,
1469 MachineBasicBlock::iterator I,
1470 unsigned DestReg, unsigned SubIdx,
1471 const MachineInstr &Orig,
1472 const TargetRegisterInfo &TRI) const {
1473 unsigned Opcode = Orig.getOpcode();
1476 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
1477 MI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
1481 case ARM::tLDRpci_pic:
1482 case ARM::t2LDRpci_pic: {
1483 MachineFunction &MF = *MBB.getParent();
1484 unsigned CPI = Orig.getOperand(1).getIndex();
1485 unsigned PCLabelId = duplicateCPV(MF, CPI);
1486 MachineInstrBuilder MIB =
1487 BuildMI(MBB, I, Orig.getDebugLoc(), get(Opcode), DestReg)
1488 .addConstantPoolIndex(CPI)
1490 MIB->setMemRefs(Orig.memoperands_begin(), Orig.memoperands_end());
1496 MachineInstr *ARMBaseInstrInfo::duplicate(MachineInstr &Orig,
1497 MachineFunction &MF) const {
1498 MachineInstr *MI = TargetInstrInfo::duplicate(Orig, MF);
1499 switch (Orig.getOpcode()) {
1500 case ARM::tLDRpci_pic:
1501 case ARM::t2LDRpci_pic: {
1502 unsigned CPI = Orig.getOperand(1).getIndex();
1503 unsigned PCLabelId = duplicateCPV(MF, CPI);
1504 Orig.getOperand(1).setIndex(CPI);
1505 Orig.getOperand(2).setImm(PCLabelId);
1512 bool ARMBaseInstrInfo::produceSameValue(const MachineInstr &MI0,
1513 const MachineInstr &MI1,
1514 const MachineRegisterInfo *MRI) const {
1515 unsigned Opcode = MI0.getOpcode();
1516 if (Opcode == ARM::t2LDRpci ||
1517 Opcode == ARM::t2LDRpci_pic ||
1518 Opcode == ARM::tLDRpci ||
1519 Opcode == ARM::tLDRpci_pic ||
1520 Opcode == ARM::LDRLIT_ga_pcrel ||
1521 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1522 Opcode == ARM::tLDRLIT_ga_pcrel ||
1523 Opcode == ARM::MOV_ga_pcrel ||
1524 Opcode == ARM::MOV_ga_pcrel_ldr ||
1525 Opcode == ARM::t2MOV_ga_pcrel) {
1526 if (MI1.getOpcode() != Opcode)
1528 if (MI0.getNumOperands() != MI1.getNumOperands())
1531 const MachineOperand &MO0 = MI0.getOperand(1);
1532 const MachineOperand &MO1 = MI1.getOperand(1);
1533 if (MO0.getOffset() != MO1.getOffset())
1536 if (Opcode == ARM::LDRLIT_ga_pcrel ||
1537 Opcode == ARM::LDRLIT_ga_pcrel_ldr ||
1538 Opcode == ARM::tLDRLIT_ga_pcrel ||
1539 Opcode == ARM::MOV_ga_pcrel ||
1540 Opcode == ARM::MOV_ga_pcrel_ldr ||
1541 Opcode == ARM::t2MOV_ga_pcrel)
1542 // Ignore the PC labels.
1543 return MO0.getGlobal() == MO1.getGlobal();
1545 const MachineFunction *MF = MI0.getParent()->getParent();
1546 const MachineConstantPool *MCP = MF->getConstantPool();
1547 int CPI0 = MO0.getIndex();
1548 int CPI1 = MO1.getIndex();
1549 const MachineConstantPoolEntry &MCPE0 = MCP->getConstants()[CPI0];
1550 const MachineConstantPoolEntry &MCPE1 = MCP->getConstants()[CPI1];
1551 bool isARMCP0 = MCPE0.isMachineConstantPoolEntry();
1552 bool isARMCP1 = MCPE1.isMachineConstantPoolEntry();
1553 if (isARMCP0 && isARMCP1) {
1554 ARMConstantPoolValue *ACPV0 =
1555 static_cast<ARMConstantPoolValue*>(MCPE0.Val.MachineCPVal);
1556 ARMConstantPoolValue *ACPV1 =
1557 static_cast<ARMConstantPoolValue*>(MCPE1.Val.MachineCPVal);
1558 return ACPV0->hasSameValue(ACPV1);
1559 } else if (!isARMCP0 && !isARMCP1) {
1560 return MCPE0.Val.ConstVal == MCPE1.Val.ConstVal;
1563 } else if (Opcode == ARM::PICLDR) {
1564 if (MI1.getOpcode() != Opcode)
1566 if (MI0.getNumOperands() != MI1.getNumOperands())
1569 unsigned Addr0 = MI0.getOperand(1).getReg();
1570 unsigned Addr1 = MI1.getOperand(1).getReg();
1571 if (Addr0 != Addr1) {
1573 !TargetRegisterInfo::isVirtualRegister(Addr0) ||
1574 !TargetRegisterInfo::isVirtualRegister(Addr1))
1577 // This assumes SSA form.
1578 MachineInstr *Def0 = MRI->getVRegDef(Addr0);
1579 MachineInstr *Def1 = MRI->getVRegDef(Addr1);
1580 // Check if the loaded value, e.g. a constantpool of a global address, are
1582 if (!produceSameValue(*Def0, *Def1, MRI))
1586 for (unsigned i = 3, e = MI0.getNumOperands(); i != e; ++i) {
1587 // %vreg12<def> = PICLDR %vreg11, 0, pred:14, pred:%noreg
1588 const MachineOperand &MO0 = MI0.getOperand(i);
1589 const MachineOperand &MO1 = MI1.getOperand(i);
1590 if (!MO0.isIdenticalTo(MO1))
1596 return MI0.isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
1599 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
1600 /// determine if two loads are loading from the same base address. It should
1601 /// only return true if the base pointers are the same and the only differences
1602 /// between the two addresses is the offset. It also returns the offsets by
1605 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1606 /// is permanently disabled.
1607 bool ARMBaseInstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
1609 int64_t &Offset2) const {
1610 // Don't worry about Thumb: just ARM and Thumb2.
1611 if (Subtarget.isThumb1Only()) return false;
1613 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
1616 switch (Load1->getMachineOpcode()) {
1630 case ARM::t2LDRSHi8:
1632 case ARM::t2LDRBi12:
1633 case ARM::t2LDRSHi12:
1637 switch (Load2->getMachineOpcode()) {
1650 case ARM::t2LDRSHi8:
1652 case ARM::t2LDRBi12:
1653 case ARM::t2LDRSHi12:
1657 // Check if base addresses and chain operands match.
1658 if (Load1->getOperand(0) != Load2->getOperand(0) ||
1659 Load1->getOperand(4) != Load2->getOperand(4))
1662 // Index should be Reg0.
1663 if (Load1->getOperand(3) != Load2->getOperand(3))
1666 // Determine the offsets.
1667 if (isa<ConstantSDNode>(Load1->getOperand(1)) &&
1668 isa<ConstantSDNode>(Load2->getOperand(1))) {
1669 Offset1 = cast<ConstantSDNode>(Load1->getOperand(1))->getSExtValue();
1670 Offset2 = cast<ConstantSDNode>(Load2->getOperand(1))->getSExtValue();
1677 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
1678 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
1679 /// be scheduled togther. On some targets if two loads are loading from
1680 /// addresses in the same cache line, it's better if they are scheduled
1681 /// together. This function takes two integers that represent the load offsets
1682 /// from the common base address. It returns true if it decides it's desirable
1683 /// to schedule the two loads together. "NumLoads" is the number of loads that
1684 /// have already been scheduled after Load1.
1686 /// FIXME: remove this in favor of the MachineInstr interface once pre-RA-sched
1687 /// is permanently disabled.
1688 bool ARMBaseInstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
1689 int64_t Offset1, int64_t Offset2,
1690 unsigned NumLoads) const {
1691 // Don't worry about Thumb: just ARM and Thumb2.
1692 if (Subtarget.isThumb1Only()) return false;
1694 assert(Offset2 > Offset1);
1696 if ((Offset2 - Offset1) / 8 > 64)
1699 // Check if the machine opcodes are different. If they are different
1700 // then we consider them to not be of the same base address,
1701 // EXCEPT in the case of Thumb2 byte loads where one is LDRBi8 and the other LDRBi12.
1702 // In this case, they are considered to be the same because they are different
1703 // encoding forms of the same basic instruction.
1704 if ((Load1->getMachineOpcode() != Load2->getMachineOpcode()) &&
1705 !((Load1->getMachineOpcode() == ARM::t2LDRBi8 &&
1706 Load2->getMachineOpcode() == ARM::t2LDRBi12) ||
1707 (Load1->getMachineOpcode() == ARM::t2LDRBi12 &&
1708 Load2->getMachineOpcode() == ARM::t2LDRBi8)))
1709 return false; // FIXME: overly conservative?
1711 // Four loads in a row should be sufficient.
1718 bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI,
1719 const MachineBasicBlock *MBB,
1720 const MachineFunction &MF) const {
1721 // Debug info is never a scheduling boundary. It's necessary to be explicit
1722 // due to the special treatment of IT instructions below, otherwise a
1723 // dbg_value followed by an IT will result in the IT instruction being
1724 // considered a scheduling hazard, which is wrong. It should be the actual
1725 // instruction preceding the dbg_value instruction(s), just like it is
1726 // when debug info is not present.
1727 if (MI.isDebugValue())
1730 // Terminators and labels can't be scheduled around.
1731 if (MI.isTerminator() || MI.isPosition())
1734 // Treat the start of the IT block as a scheduling boundary, but schedule
1735 // t2IT along with all instructions following it.
1736 // FIXME: This is a big hammer. But the alternative is to add all potential
1737 // true and anti dependencies to IT block instructions as implicit operands
1738 // to the t2IT instruction. The added compile time and complexity does not
1740 MachineBasicBlock::const_iterator I = MI;
1741 // Make sure to skip any dbg_value instructions
1742 while (++I != MBB->end() && I->isDebugValue())
1744 if (I != MBB->end() && I->getOpcode() == ARM::t2IT)
1747 // Don't attempt to schedule around any instruction that defines
1748 // a stack-oriented pointer, as it's unlikely to be profitable. This
1749 // saves compile time, because it doesn't require every single
1750 // stack slot reference to depend on the instruction that does the
1752 // Calls don't actually change the stack pointer, even if they have imp-defs.
1753 // No ARM calling conventions change the stack pointer. (X86 calling
1754 // conventions sometimes do).
1755 if (!MI.isCall() && MI.definesRegister(ARM::SP))
1761 bool ARMBaseInstrInfo::
1762 isProfitableToIfCvt(MachineBasicBlock &MBB,
1763 unsigned NumCycles, unsigned ExtraPredCycles,
1764 BranchProbability Probability) const {
1768 // If we are optimizing for size, see if the branch in the predecessor can be
1769 // lowered to cbn?z by the constant island lowering pass, and return false if
1770 // so. This results in a shorter instruction sequence.
1771 if (MBB.getParent()->getFunction()->optForSize()) {
1772 MachineBasicBlock *Pred = *MBB.pred_begin();
1773 if (!Pred->empty()) {
1774 MachineInstr *LastMI = &*Pred->rbegin();
1775 if (LastMI->getOpcode() == ARM::t2Bcc) {
1776 MachineBasicBlock::iterator CmpMI = LastMI;
1777 if (CmpMI != Pred->begin()) {
1779 if (CmpMI->getOpcode() == ARM::tCMPi8 ||
1780 CmpMI->getOpcode() == ARM::t2CMPri) {
1781 unsigned Reg = CmpMI->getOperand(0).getReg();
1782 unsigned PredReg = 0;
1783 ARMCC::CondCodes P = getInstrPredicate(*CmpMI, PredReg);
1784 if (P == ARMCC::AL && CmpMI->getOperand(1).getImm() == 0 &&
1785 isARMLowRegister(Reg))
1792 return isProfitableToIfCvt(MBB, NumCycles, ExtraPredCycles,
1793 MBB, 0, 0, Probability);
1796 bool ARMBaseInstrInfo::
1797 isProfitableToIfCvt(MachineBasicBlock &,
1798 unsigned TCycles, unsigned TExtra,
1799 MachineBasicBlock &,
1800 unsigned FCycles, unsigned FExtra,
1801 BranchProbability Probability) const {
1805 // Attempt to estimate the relative costs of predication versus branching.
1806 // Here we scale up each component of UnpredCost to avoid precision issue when
1807 // scaling TCycles/FCycles by Probability.
1808 const unsigned ScalingUpFactor = 1024;
1809 unsigned TUnpredCost = Probability.scale(TCycles * ScalingUpFactor);
1810 unsigned FUnpredCost =
1811 Probability.getCompl().scale(FCycles * ScalingUpFactor);
1812 unsigned UnpredCost = TUnpredCost + FUnpredCost;
1813 UnpredCost += 1 * ScalingUpFactor; // The branch itself
1814 UnpredCost += Subtarget.getMispredictionPenalty() * ScalingUpFactor / 10;
1816 return (TCycles + FCycles + TExtra + FExtra) * ScalingUpFactor <= UnpredCost;
1820 ARMBaseInstrInfo::isProfitableToUnpredicate(MachineBasicBlock &TMBB,
1821 MachineBasicBlock &FMBB) const {
1822 // Reduce false anti-dependencies to let the target's out-of-order execution
1823 // engine do its thing.
1824 return Subtarget.isProfitableToUnpredicate();
1827 /// getInstrPredicate - If instruction is predicated, returns its predicate
1828 /// condition, otherwise returns AL. It also returns the condition code
1829 /// register by reference.
1830 ARMCC::CondCodes llvm::getInstrPredicate(const MachineInstr &MI,
1831 unsigned &PredReg) {
1832 int PIdx = MI.findFirstPredOperandIdx();
1838 PredReg = MI.getOperand(PIdx+1).getReg();
1839 return (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
1842 unsigned llvm::getMatchingCondBranchOpcode(unsigned Opc) {
1847 if (Opc == ARM::t2B)
1850 llvm_unreachable("Unknown unconditional branch opcode!");
1853 MachineInstr *ARMBaseInstrInfo::commuteInstructionImpl(MachineInstr &MI,
1856 unsigned OpIdx2) const {
1857 switch (MI.getOpcode()) {
1859 case ARM::t2MOVCCr: {
1860 // MOVCC can be commuted by inverting the condition.
1861 unsigned PredReg = 0;
1862 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg);
1863 // MOVCC AL can't be inverted. Shouldn't happen.
1864 if (CC == ARMCC::AL || PredReg != ARM::CPSR)
1866 MachineInstr *CommutedMI =
1867 TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1870 // After swapping the MOVCC operands, also invert the condition.
1871 CommutedMI->getOperand(CommutedMI->findFirstPredOperandIdx())
1872 .setImm(ARMCC::getOppositeCondition(CC));
1876 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
1879 /// Identify instructions that can be folded into a MOVCC instruction, and
1880 /// return the defining instruction.
1881 static MachineInstr *canFoldIntoMOVCC(unsigned Reg,
1882 const MachineRegisterInfo &MRI,
1883 const TargetInstrInfo *TII) {
1884 if (!TargetRegisterInfo::isVirtualRegister(Reg))
1886 if (!MRI.hasOneNonDBGUse(Reg))
1888 MachineInstr *MI = MRI.getVRegDef(Reg);
1891 // MI is folded into the MOVCC by predicating it.
1892 if (!MI->isPredicable())
1894 // Check if MI has any non-dead defs or physreg uses. This also detects
1895 // predicated instructions which will be reading CPSR.
1896 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) {
1897 const MachineOperand &MO = MI->getOperand(i);
1898 // Reject frame index operands, PEI can't handle the predicated pseudos.
1899 if (MO.isFI() || MO.isCPI() || MO.isJTI())
1903 // MI can't have any tied operands, that would conflict with predication.
1906 if (TargetRegisterInfo::isPhysicalRegister(MO.getReg()))
1908 if (MO.isDef() && !MO.isDead())
1911 bool DontMoveAcrossStores = true;
1912 if (!MI->isSafeToMove(/* AliasAnalysis = */ nullptr, DontMoveAcrossStores))
1917 bool ARMBaseInstrInfo::analyzeSelect(const MachineInstr &MI,
1918 SmallVectorImpl<MachineOperand> &Cond,
1919 unsigned &TrueOp, unsigned &FalseOp,
1920 bool &Optimizable) const {
1921 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
1922 "Unknown select instruction");
1927 // 3: Condition code.
1931 Cond.push_back(MI.getOperand(3));
1932 Cond.push_back(MI.getOperand(4));
1933 // We can always fold a def.
1939 ARMBaseInstrInfo::optimizeSelect(MachineInstr &MI,
1940 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
1941 bool PreferFalse) const {
1942 assert((MI.getOpcode() == ARM::MOVCCr || MI.getOpcode() == ARM::t2MOVCCr) &&
1943 "Unknown select instruction");
1944 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
1945 MachineInstr *DefMI = canFoldIntoMOVCC(MI.getOperand(2).getReg(), MRI, this);
1946 bool Invert = !DefMI;
1948 DefMI = canFoldIntoMOVCC(MI.getOperand(1).getReg(), MRI, this);
1952 // Find new register class to use.
1953 MachineOperand FalseReg = MI.getOperand(Invert ? 2 : 1);
1954 unsigned DestReg = MI.getOperand(0).getReg();
1955 const TargetRegisterClass *PreviousClass = MRI.getRegClass(FalseReg.getReg());
1956 if (!MRI.constrainRegClass(DestReg, PreviousClass))
1959 // Create a new predicated version of DefMI.
1960 // Rfalse is the first use.
1961 MachineInstrBuilder NewMI =
1962 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), DefMI->getDesc(), DestReg);
1964 // Copy all the DefMI operands, excluding its (null) predicate.
1965 const MCInstrDesc &DefDesc = DefMI->getDesc();
1966 for (unsigned i = 1, e = DefDesc.getNumOperands();
1967 i != e && !DefDesc.OpInfo[i].isPredicate(); ++i)
1968 NewMI.add(DefMI->getOperand(i));
1970 unsigned CondCode = MI.getOperand(3).getImm();
1972 NewMI.addImm(ARMCC::getOppositeCondition(ARMCC::CondCodes(CondCode)));
1974 NewMI.addImm(CondCode);
1975 NewMI.add(MI.getOperand(4));
1977 // DefMI is not the -S version that sets CPSR, so add an optional %noreg.
1978 if (NewMI->hasOptionalDef())
1979 NewMI.add(condCodeOp());
1981 // The output register value when the predicate is false is an implicit
1982 // register operand tied to the first def.
1983 // The tie makes the register allocator ensure the FalseReg is allocated the
1984 // same register as operand 0.
1985 FalseReg.setImplicit();
1986 NewMI.add(FalseReg);
1987 NewMI->tieOperands(0, NewMI->getNumOperands() - 1);
1989 // Update SeenMIs set: register newly created MI and erase removed DefMI.
1990 SeenMIs.insert(NewMI);
1991 SeenMIs.erase(DefMI);
1993 // If MI is inside a loop, and DefMI is outside the loop, then kill flags on
1994 // DefMI would be invalid when tranferred inside the loop. Checking for a
1995 // loop is expensive, but at least remove kill flags if they are in different
1997 if (DefMI->getParent() != MI.getParent())
1998 NewMI->clearKillInfo();
2000 // The caller will erase MI, but not DefMI.
2001 DefMI->eraseFromParent();
2005 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether the
2006 /// instruction is encoded with an 'S' bit is determined by the optional CPSR
2009 /// This will go away once we can teach tblgen how to set the optional CPSR def
2011 struct AddSubFlagsOpcodePair {
2013 uint16_t MachineOpc;
2016 static const AddSubFlagsOpcodePair AddSubFlagsOpcodeMap[] = {
2017 {ARM::ADDSri, ARM::ADDri},
2018 {ARM::ADDSrr, ARM::ADDrr},
2019 {ARM::ADDSrsi, ARM::ADDrsi},
2020 {ARM::ADDSrsr, ARM::ADDrsr},
2022 {ARM::SUBSri, ARM::SUBri},
2023 {ARM::SUBSrr, ARM::SUBrr},
2024 {ARM::SUBSrsi, ARM::SUBrsi},
2025 {ARM::SUBSrsr, ARM::SUBrsr},
2027 {ARM::RSBSri, ARM::RSBri},
2028 {ARM::RSBSrsi, ARM::RSBrsi},
2029 {ARM::RSBSrsr, ARM::RSBrsr},
2031 {ARM::tADDSi3, ARM::tADDi3},
2032 {ARM::tADDSi8, ARM::tADDi8},
2033 {ARM::tADDSrr, ARM::tADDrr},
2034 {ARM::tADCS, ARM::tADC},
2036 {ARM::tSUBSi3, ARM::tSUBi3},
2037 {ARM::tSUBSi8, ARM::tSUBi8},
2038 {ARM::tSUBSrr, ARM::tSUBrr},
2039 {ARM::tSBCS, ARM::tSBC},
2041 {ARM::t2ADDSri, ARM::t2ADDri},
2042 {ARM::t2ADDSrr, ARM::t2ADDrr},
2043 {ARM::t2ADDSrs, ARM::t2ADDrs},
2045 {ARM::t2SUBSri, ARM::t2SUBri},
2046 {ARM::t2SUBSrr, ARM::t2SUBrr},
2047 {ARM::t2SUBSrs, ARM::t2SUBrs},
2049 {ARM::t2RSBSri, ARM::t2RSBri},
2050 {ARM::t2RSBSrs, ARM::t2RSBrs},
2053 unsigned llvm::convertAddSubFlagsOpcode(unsigned OldOpc) {
2054 for (unsigned i = 0, e = array_lengthof(AddSubFlagsOpcodeMap); i != e; ++i)
2055 if (OldOpc == AddSubFlagsOpcodeMap[i].PseudoOpc)
2056 return AddSubFlagsOpcodeMap[i].MachineOpc;
2060 void llvm::emitARMRegPlusImmediate(MachineBasicBlock &MBB,
2061 MachineBasicBlock::iterator &MBBI,
2062 const DebugLoc &dl, unsigned DestReg,
2063 unsigned BaseReg, int NumBytes,
2064 ARMCC::CondCodes Pred, unsigned PredReg,
2065 const ARMBaseInstrInfo &TII,
2067 if (NumBytes == 0 && DestReg != BaseReg) {
2068 BuildMI(MBB, MBBI, dl, TII.get(ARM::MOVr), DestReg)
2069 .addReg(BaseReg, RegState::Kill)
2070 .add(predOps(Pred, PredReg))
2072 .setMIFlags(MIFlags);
2076 bool isSub = NumBytes < 0;
2077 if (isSub) NumBytes = -NumBytes;
2080 unsigned RotAmt = ARM_AM::getSOImmValRotate(NumBytes);
2081 unsigned ThisVal = NumBytes & ARM_AM::rotr32(0xFF, RotAmt);
2082 assert(ThisVal && "Didn't extract field correctly");
2084 // We will handle these bits from offset, clear them.
2085 NumBytes &= ~ThisVal;
2087 assert(ARM_AM::getSOImmVal(ThisVal) != -1 && "Bit extraction didn't work?");
2089 // Build the new ADD / SUB.
2090 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri;
2091 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg)
2092 .addReg(BaseReg, RegState::Kill)
2094 .add(predOps(Pred, PredReg))
2096 .setMIFlags(MIFlags);
2101 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
2102 MachineFunction &MF, MachineInstr *MI,
2103 unsigned NumBytes) {
2104 // This optimisation potentially adds lots of load and store
2105 // micro-operations, it's only really a great benefit to code-size.
2106 if (!MF.getFunction()->optForMinSize())
2109 // If only one register is pushed/popped, LLVM can use an LDR/STR
2110 // instead. We can't modify those so make sure we're dealing with an
2111 // instruction we understand.
2112 bool IsPop = isPopOpcode(MI->getOpcode());
2113 bool IsPush = isPushOpcode(MI->getOpcode());
2114 if (!IsPush && !IsPop)
2117 bool IsVFPPushPop = MI->getOpcode() == ARM::VSTMDDB_UPD ||
2118 MI->getOpcode() == ARM::VLDMDIA_UPD;
2119 bool IsT1PushPop = MI->getOpcode() == ARM::tPUSH ||
2120 MI->getOpcode() == ARM::tPOP ||
2121 MI->getOpcode() == ARM::tPOP_RET;
2123 assert((IsT1PushPop || (MI->getOperand(0).getReg() == ARM::SP &&
2124 MI->getOperand(1).getReg() == ARM::SP)) &&
2125 "trying to fold sp update into non-sp-updating push/pop");
2127 // The VFP push & pop act on D-registers, so we can only fold an adjustment
2128 // by a multiple of 8 bytes in correctly. Similarly rN is 4-bytes. Don't try
2129 // if this is violated.
2130 if (NumBytes % (IsVFPPushPop ? 8 : 4) != 0)
2133 // ARM and Thumb2 push/pop insts have explicit "sp, sp" operands (+
2134 // pred) so the list starts at 4. Thumb1 starts after the predicate.
2135 int RegListIdx = IsT1PushPop ? 2 : 4;
2137 // Calculate the space we'll need in terms of registers.
2138 unsigned RegsNeeded;
2139 const TargetRegisterClass *RegClass;
2141 RegsNeeded = NumBytes / 8;
2142 RegClass = &ARM::DPRRegClass;
2144 RegsNeeded = NumBytes / 4;
2145 RegClass = &ARM::GPRRegClass;
2148 // We're going to have to strip all list operands off before
2149 // re-adding them since the order matters, so save the existing ones
2151 SmallVector<MachineOperand, 4> RegList;
2153 // We're also going to need the first register transferred by this
2154 // instruction, which won't necessarily be the first register in the list.
2155 unsigned FirstRegEnc = -1;
2157 const TargetRegisterInfo *TRI = MF.getRegInfo().getTargetRegisterInfo();
2158 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i) {
2159 MachineOperand &MO = MI->getOperand(i);
2160 RegList.push_back(MO);
2162 if (MO.isReg() && TRI->getEncodingValue(MO.getReg()) < FirstRegEnc)
2163 FirstRegEnc = TRI->getEncodingValue(MO.getReg());
2166 const MCPhysReg *CSRegs = TRI->getCalleeSavedRegs(&MF);
2168 // Now try to find enough space in the reglist to allocate NumBytes.
2169 for (int CurRegEnc = FirstRegEnc - 1; CurRegEnc >= 0 && RegsNeeded;
2171 unsigned CurReg = RegClass->getRegister(CurRegEnc);
2173 // Pushing any register is completely harmless, mark the
2174 // register involved as undef since we don't care about it in
2176 RegList.push_back(MachineOperand::CreateReg(CurReg, false, false,
2177 false, false, true));
2182 // However, we can only pop an extra register if it's not live. For
2183 // registers live within the function we might clobber a return value
2184 // register; the other way a register can be live here is if it's
2186 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2187 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2188 MachineBasicBlock::LQR_Dead) {
2189 // VFP pops don't allow holes in the register list, so any skip is fatal
2190 // for our transformation. GPR pops do, so we should just keep looking.
2197 // Mark the unimportant registers as <def,dead> in the POP.
2198 RegList.push_back(MachineOperand::CreateReg(CurReg, true, false, false,
2206 // Finally we know we can profitably perform the optimisation so go
2207 // ahead: strip all existing registers off and add them back again
2208 // in the right order.
2209 for (int i = MI->getNumOperands() - 1; i >= RegListIdx; --i)
2210 MI->RemoveOperand(i);
2212 // Add the complete list back in.
2213 MachineInstrBuilder MIB(MF, &*MI);
2214 for (int i = RegList.size() - 1; i >= 0; --i)
2215 MIB.add(RegList[i]);
2220 bool llvm::rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
2221 unsigned FrameReg, int &Offset,
2222 const ARMBaseInstrInfo &TII) {
2223 unsigned Opcode = MI.getOpcode();
2224 const MCInstrDesc &Desc = MI.getDesc();
2225 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
2228 // Memory operands in inline assembly always use AddrMode2.
2229 if (Opcode == ARM::INLINEASM)
2230 AddrMode = ARMII::AddrMode2;
2232 if (Opcode == ARM::ADDri) {
2233 Offset += MI.getOperand(FrameRegIdx+1).getImm();
2235 // Turn it into a move.
2236 MI.setDesc(TII.get(ARM::MOVr));
2237 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2238 MI.RemoveOperand(FrameRegIdx+1);
2241 } else if (Offset < 0) {
2244 MI.setDesc(TII.get(ARM::SUBri));
2247 // Common case: small offset, fits into instruction.
2248 if (ARM_AM::getSOImmVal(Offset) != -1) {
2249 // Replace the FrameIndex with sp / fp
2250 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2251 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(Offset);
2256 // Otherwise, pull as much of the immedidate into this ADDri/SUBri
2258 unsigned RotAmt = ARM_AM::getSOImmValRotate(Offset);
2259 unsigned ThisImmVal = Offset & ARM_AM::rotr32(0xFF, RotAmt);
2261 // We will handle these bits from offset, clear them.
2262 Offset &= ~ThisImmVal;
2264 // Get the properly encoded SOImmVal field.
2265 assert(ARM_AM::getSOImmVal(ThisImmVal) != -1 &&
2266 "Bit extraction didn't work?");
2267 MI.getOperand(FrameRegIdx+1).ChangeToImmediate(ThisImmVal);
2269 unsigned ImmIdx = 0;
2271 unsigned NumBits = 0;
2274 case ARMII::AddrMode_i12:
2275 ImmIdx = FrameRegIdx + 1;
2276 InstrOffs = MI.getOperand(ImmIdx).getImm();
2279 case ARMII::AddrMode2:
2280 ImmIdx = FrameRegIdx+2;
2281 InstrOffs = ARM_AM::getAM2Offset(MI.getOperand(ImmIdx).getImm());
2282 if (ARM_AM::getAM2Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2286 case ARMII::AddrMode3:
2287 ImmIdx = FrameRegIdx+2;
2288 InstrOffs = ARM_AM::getAM3Offset(MI.getOperand(ImmIdx).getImm());
2289 if (ARM_AM::getAM3Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2293 case ARMII::AddrMode4:
2294 case ARMII::AddrMode6:
2295 // Can't fold any offset even if it's zero.
2297 case ARMII::AddrMode5:
2298 ImmIdx = FrameRegIdx+1;
2299 InstrOffs = ARM_AM::getAM5Offset(MI.getOperand(ImmIdx).getImm());
2300 if (ARM_AM::getAM5Op(MI.getOperand(ImmIdx).getImm()) == ARM_AM::sub)
2306 llvm_unreachable("Unsupported addressing mode!");
2309 Offset += InstrOffs * Scale;
2310 assert((Offset & (Scale-1)) == 0 && "Can't encode this offset!");
2316 // Attempt to fold address comp. if opcode has offset bits
2318 // Common case: small offset, fits into instruction.
2319 MachineOperand &ImmOp = MI.getOperand(ImmIdx);
2320 int ImmedOffset = Offset / Scale;
2321 unsigned Mask = (1 << NumBits) - 1;
2322 if ((unsigned)Offset <= Mask * Scale) {
2323 // Replace the FrameIndex with sp
2324 MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false);
2325 // FIXME: When addrmode2 goes away, this will simplify (like the
2326 // T2 version), as the LDR.i12 versions don't need the encoding
2327 // tricks for the offset value.
2329 if (AddrMode == ARMII::AddrMode_i12)
2330 ImmedOffset = -ImmedOffset;
2332 ImmedOffset |= 1 << NumBits;
2334 ImmOp.ChangeToImmediate(ImmedOffset);
2339 // Otherwise, it didn't fit. Pull in what we can to simplify the immed.
2340 ImmedOffset = ImmedOffset & Mask;
2342 if (AddrMode == ARMII::AddrMode_i12)
2343 ImmedOffset = -ImmedOffset;
2345 ImmedOffset |= 1 << NumBits;
2347 ImmOp.ChangeToImmediate(ImmedOffset);
2348 Offset &= ~(Mask*Scale);
2352 Offset = (isSub) ? -Offset : Offset;
2356 /// analyzeCompare - For a comparison instruction, return the source registers
2357 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2358 /// compares against in CmpValue. Return true if the comparison instruction
2359 /// can be analyzed.
2360 bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
2361 unsigned &SrcReg2, int &CmpMask,
2362 int &CmpValue) const {
2363 switch (MI.getOpcode()) {
2368 SrcReg = MI.getOperand(0).getReg();
2371 CmpValue = MI.getOperand(1).getImm();
2375 SrcReg = MI.getOperand(0).getReg();
2376 SrcReg2 = MI.getOperand(1).getReg();
2382 SrcReg = MI.getOperand(0).getReg();
2384 CmpMask = MI.getOperand(1).getImm();
2392 /// isSuitableForMask - Identify a suitable 'and' instruction that
2393 /// operates on the given source register and applies the same mask
2394 /// as a 'tst' instruction. Provide a limited look-through for copies.
2395 /// When successful, MI will hold the found instruction.
2396 static bool isSuitableForMask(MachineInstr *&MI, unsigned SrcReg,
2397 int CmpMask, bool CommonUse) {
2398 switch (MI->getOpcode()) {
2401 if (CmpMask != MI->getOperand(2).getImm())
2403 if (SrcReg == MI->getOperand(CommonUse ? 1 : 0).getReg())
2411 /// getSwappedCondition - assume the flags are set by MI(a,b), return
2412 /// the condition code if we modify the instructions such that flags are
2414 inline static ARMCC::CondCodes getSwappedCondition(ARMCC::CondCodes CC) {
2416 default: return ARMCC::AL;
2417 case ARMCC::EQ: return ARMCC::EQ;
2418 case ARMCC::NE: return ARMCC::NE;
2419 case ARMCC::HS: return ARMCC::LS;
2420 case ARMCC::LO: return ARMCC::HI;
2421 case ARMCC::HI: return ARMCC::LO;
2422 case ARMCC::LS: return ARMCC::HS;
2423 case ARMCC::GE: return ARMCC::LE;
2424 case ARMCC::LT: return ARMCC::GT;
2425 case ARMCC::GT: return ARMCC::LT;
2426 case ARMCC::LE: return ARMCC::GE;
2430 /// isRedundantFlagInstr - check whether the first instruction, whose only
2431 /// purpose is to update flags, can be made redundant.
2432 /// CMPrr can be made redundant by SUBrr if the operands are the same.
2433 /// CMPri can be made redundant by SUBri if the operands are the same.
2434 /// This function can be extended later on.
2435 inline static bool isRedundantFlagInstr(MachineInstr *CmpI, unsigned SrcReg,
2436 unsigned SrcReg2, int ImmValue,
2438 if ((CmpI->getOpcode() == ARM::CMPrr ||
2439 CmpI->getOpcode() == ARM::t2CMPrr) &&
2440 (OI->getOpcode() == ARM::SUBrr ||
2441 OI->getOpcode() == ARM::t2SUBrr) &&
2442 ((OI->getOperand(1).getReg() == SrcReg &&
2443 OI->getOperand(2).getReg() == SrcReg2) ||
2444 (OI->getOperand(1).getReg() == SrcReg2 &&
2445 OI->getOperand(2).getReg() == SrcReg)))
2448 if ((CmpI->getOpcode() == ARM::CMPri ||
2449 CmpI->getOpcode() == ARM::t2CMPri) &&
2450 (OI->getOpcode() == ARM::SUBri ||
2451 OI->getOpcode() == ARM::t2SUBri) &&
2452 OI->getOperand(1).getReg() == SrcReg &&
2453 OI->getOperand(2).getImm() == ImmValue)
2458 static bool isOptimizeCompareCandidate(MachineInstr *MI, bool &IsThumb1) {
2459 switch (MI->getOpcode()) {
2460 default: return false;
2515 /// optimizeCompareInstr - Convert the instruction supplying the argument to the
2516 /// comparison into one that sets the zero bit in the flags register;
2517 /// Remove a redundant Compare instruction if an earlier instruction can set the
2518 /// flags in the same way as Compare.
2519 /// E.g. SUBrr(r1,r2) and CMPrr(r1,r2). We also handle the case where two
2520 /// operands are swapped: SUBrr(r1,r2) and CMPrr(r2,r1), by updating the
2521 /// condition code of instructions which use the flags.
2522 bool ARMBaseInstrInfo::optimizeCompareInstr(
2523 MachineInstr &CmpInstr, unsigned SrcReg, unsigned SrcReg2, int CmpMask,
2524 int CmpValue, const MachineRegisterInfo *MRI) const {
2525 // Get the unique definition of SrcReg.
2526 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
2527 if (!MI) return false;
2529 // Masked compares sometimes use the same register as the corresponding 'and'.
2530 if (CmpMask != ~0) {
2531 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) {
2533 for (MachineRegisterInfo::use_instr_iterator
2534 UI = MRI->use_instr_begin(SrcReg), UE = MRI->use_instr_end();
2536 if (UI->getParent() != CmpInstr.getParent())
2538 MachineInstr *PotentialAND = &*UI;
2539 if (!isSuitableForMask(PotentialAND, SrcReg, CmpMask, true) ||
2540 isPredicated(*PotentialAND))
2545 if (!MI) return false;
2549 // Get ready to iterate backward from CmpInstr.
2550 MachineBasicBlock::iterator I = CmpInstr, E = MI,
2551 B = CmpInstr.getParent()->begin();
2553 // Early exit if CmpInstr is at the beginning of the BB.
2554 if (I == B) return false;
2556 // There are two possible candidates which can be changed to set CPSR:
2557 // One is MI, the other is a SUB instruction.
2558 // For CMPrr(r1,r2), we are looking for SUB(r1,r2) or SUB(r2,r1).
2559 // For CMPri(r1, CmpValue), we are looking for SUBri(r1, CmpValue).
2560 MachineInstr *Sub = nullptr;
2562 // MI is not a candidate for CMPrr.
2564 else if (MI->getParent() != CmpInstr.getParent() || CmpValue != 0) {
2565 // Conservatively refuse to convert an instruction which isn't in the same
2566 // BB as the comparison.
2567 // For CMPri w/ CmpValue != 0, a Sub may still be a candidate.
2568 // Thus we cannot return here.
2569 if (CmpInstr.getOpcode() == ARM::CMPri ||
2570 CmpInstr.getOpcode() == ARM::t2CMPri)
2576 bool IsThumb1 = false;
2577 if (MI && !isOptimizeCompareCandidate(MI, IsThumb1))
2580 // We also want to do this peephole for cases like this: if (a*b == 0),
2581 // and optimise away the CMP instruction from the generated code sequence:
2582 // MULS, MOVS, MOVS, CMP. Here the MOVS instructions load the boolean values
2583 // resulting from the select instruction, but these MOVS instructions for
2584 // Thumb1 (V6M) are flag setting and are thus preventing this optimisation.
2585 // However, if we only have MOVS instructions in between the CMP and the
2586 // other instruction (the MULS in this example), then the CPSR is dead so we
2587 // can safely reorder the sequence into: MOVS, MOVS, MULS, CMP. We do this
2588 // reordering and then continue the analysis hoping we can eliminate the
2589 // CMP. This peephole works on the vregs, so is still in SSA form. As a
2590 // consequence, the movs won't redefine/kill the MUL operands which would
2591 // make this reordering illegal.
2592 if (MI && IsThumb1) {
2594 bool CanReorder = true;
2595 const bool HasStmts = I != E;
2596 for (; I != E; --I) {
2597 if (I->getOpcode() != ARM::tMOVi8) {
2602 if (HasStmts && CanReorder) {
2603 MI = MI->removeFromParent();
2605 CmpInstr.getParent()->insert(E, MI);
2611 // Check that CPSR isn't set between the comparison instruction and the one we
2612 // want to change. At the same time, search for Sub.
2613 const TargetRegisterInfo *TRI = &getRegisterInfo();
2615 for (; I != E; --I) {
2616 const MachineInstr &Instr = *I;
2618 if (Instr.modifiesRegister(ARM::CPSR, TRI) ||
2619 Instr.readsRegister(ARM::CPSR, TRI))
2620 // This instruction modifies or uses CPSR after the one we want to
2621 // change. We can't do this transformation.
2624 // Check whether CmpInstr can be made redundant by the current instruction.
2625 if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &*I)) {
2631 // The 'and' is below the comparison instruction.
2635 // Return false if no candidates exist.
2639 // The single candidate is called MI.
2642 // We can't use a predicated instruction - it doesn't always write the flags.
2643 if (isPredicated(*MI))
2646 // Scan forward for the use of CPSR
2647 // When checking against MI: if it's a conditional code that requires
2648 // checking of the V bit or C bit, then this is not safe to do.
2649 // It is safe to remove CmpInstr if CPSR is redefined or killed.
2650 // If we are done with the basic block, we need to check whether CPSR is
2652 SmallVector<std::pair<MachineOperand*, ARMCC::CondCodes>, 4>
2654 bool isSafe = false;
2656 E = CmpInstr.getParent()->end();
2657 while (!isSafe && ++I != E) {
2658 const MachineInstr &Instr = *I;
2659 for (unsigned IO = 0, EO = Instr.getNumOperands();
2660 !isSafe && IO != EO; ++IO) {
2661 const MachineOperand &MO = Instr.getOperand(IO);
2662 if (MO.isRegMask() && MO.clobbersPhysReg(ARM::CPSR)) {
2666 if (!MO.isReg() || MO.getReg() != ARM::CPSR)
2672 // Condition code is after the operand before CPSR except for VSELs.
2673 ARMCC::CondCodes CC;
2674 bool IsInstrVSel = true;
2675 switch (Instr.getOpcode()) {
2677 IsInstrVSel = false;
2678 CC = (ARMCC::CondCodes)Instr.getOperand(IO - 1).getImm();
2699 ARMCC::CondCodes NewCC = getSwappedCondition(CC);
2700 if (NewCC == ARMCC::AL)
2702 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code based
2703 // on CMP needs to be updated to be based on SUB.
2704 // Push the condition code operands to OperandsToUpdate.
2705 // If it is safe to remove CmpInstr, the condition code of these
2706 // operands will be modified.
2707 if (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
2708 Sub->getOperand(2).getReg() == SrcReg) {
2709 // VSel doesn't support condition code update.
2712 OperandsToUpdate.push_back(
2713 std::make_pair(&((*I).getOperand(IO - 1)), NewCC));
2716 // No Sub, so this is x = <op> y, z; cmp x, 0.
2718 case ARMCC::EQ: // Z
2719 case ARMCC::NE: // Z
2720 case ARMCC::MI: // N
2721 case ARMCC::PL: // N
2722 case ARMCC::AL: // none
2723 // CPSR can be used multiple times, we should continue.
2725 case ARMCC::HS: // C
2726 case ARMCC::LO: // C
2727 case ARMCC::VS: // V
2728 case ARMCC::VC: // V
2729 case ARMCC::HI: // C Z
2730 case ARMCC::LS: // C Z
2731 case ARMCC::GE: // N V
2732 case ARMCC::LT: // N V
2733 case ARMCC::GT: // Z N V
2734 case ARMCC::LE: // Z N V
2735 // The instruction uses the V bit or C bit which is not safe.
2742 // If CPSR is not killed nor re-defined, we should check whether it is
2743 // live-out. If it is live-out, do not optimize.
2745 MachineBasicBlock *MBB = CmpInstr.getParent();
2746 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
2747 SE = MBB->succ_end(); SI != SE; ++SI)
2748 if ((*SI)->isLiveIn(ARM::CPSR))
2752 // Toggle the optional operand to CPSR (if it exists - in Thumb1 we always
2753 // set CPSR so this is represented as an explicit output)
2755 MI->getOperand(5).setReg(ARM::CPSR);
2756 MI->getOperand(5).setIsDef(true);
2758 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction");
2759 CmpInstr.eraseFromParent();
2761 // Modify the condition code of operands in OperandsToUpdate.
2762 // Since we have SUB(r1, r2) and CMP(r2, r1), the condition code needs to
2763 // be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
2764 for (unsigned i = 0, e = OperandsToUpdate.size(); i < e; i++)
2765 OperandsToUpdate[i].first->setImm(OperandsToUpdate[i].second);
2770 bool ARMBaseInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2772 MachineRegisterInfo *MRI) const {
2773 // Fold large immediates into add, sub, or, xor.
2774 unsigned DefOpc = DefMI.getOpcode();
2775 if (DefOpc != ARM::t2MOVi32imm && DefOpc != ARM::MOVi32imm)
2777 if (!DefMI.getOperand(1).isImm())
2778 // Could be t2MOVi32imm <ga:xx>
2781 if (!MRI->hasOneNonDBGUse(Reg))
2784 const MCInstrDesc &DefMCID = DefMI.getDesc();
2785 if (DefMCID.hasOptionalDef()) {
2786 unsigned NumOps = DefMCID.getNumOperands();
2787 const MachineOperand &MO = DefMI.getOperand(NumOps - 1);
2788 if (MO.getReg() == ARM::CPSR && !MO.isDead())
2789 // If DefMI defines CPSR and it is not dead, it's obviously not safe
2794 const MCInstrDesc &UseMCID = UseMI.getDesc();
2795 if (UseMCID.hasOptionalDef()) {
2796 unsigned NumOps = UseMCID.getNumOperands();
2797 if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
2798 // If the instruction sets the flag, do not attempt this optimization
2799 // since it may change the semantics of the code.
2803 unsigned UseOpc = UseMI.getOpcode();
2804 unsigned NewUseOpc = 0;
2805 uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
2806 uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
2807 bool Commute = false;
2809 default: return false;
2817 case ARM::t2EORrr: {
2818 Commute = UseMI.getOperand(2).getReg() != Reg;
2823 if (UseOpc == ARM::SUBrr && Commute)
2826 // ADD/SUB are special because they're essentially the same operation, so
2827 // we can handle a larger range of immediates.
2828 if (ARM_AM::isSOImmTwoPartVal(ImmVal))
2829 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
2830 else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
2832 NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
2835 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2836 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2840 if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
2842 SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
2843 SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
2846 case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
2847 case ARM::EORrr: NewUseOpc = ARM::EORri; break;
2852 if (UseOpc == ARM::t2SUBrr && Commute)
2855 // ADD/SUB are special because they're essentially the same operation, so
2856 // we can handle a larger range of immediates.
2857 if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2858 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2ADDri : ARM::t2SUBri;
2859 else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
2861 NewUseOpc = UseOpc == ARM::t2ADDrr ? ARM::t2SUBri : ARM::t2ADDri;
2864 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2865 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2869 if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
2871 SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
2872 SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
2875 case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
2876 case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
2883 unsigned OpIdx = Commute ? 2 : 1;
2884 unsigned Reg1 = UseMI.getOperand(OpIdx).getReg();
2885 bool isKill = UseMI.getOperand(OpIdx).isKill();
2886 unsigned NewReg = MRI->createVirtualRegister(MRI->getRegClass(Reg));
2887 BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
2889 .addReg(Reg1, getKillRegState(isKill))
2891 .add(predOps(ARMCC::AL))
2893 UseMI.setDesc(get(NewUseOpc));
2894 UseMI.getOperand(1).setReg(NewReg);
2895 UseMI.getOperand(1).setIsKill();
2896 UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
2897 DefMI.eraseFromParent();
2901 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
2902 const MachineInstr &MI) {
2903 switch (MI.getOpcode()) {
2905 const MCInstrDesc &Desc = MI.getDesc();
2906 int UOps = ItinData->getNumMicroOps(Desc.getSchedClass());
2907 assert(UOps >= 0 && "bad # UOps");
2915 unsigned ShOpVal = MI.getOperand(3).getImm();
2916 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2917 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2920 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2921 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2928 if (!MI.getOperand(2).getReg())
2931 unsigned ShOpVal = MI.getOperand(3).getImm();
2932 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2933 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2936 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2937 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2944 return (ARM_AM::getAM3Op(MI.getOperand(3).getImm()) == ARM_AM::sub) ? 3 : 2;
2946 case ARM::LDRSB_POST:
2947 case ARM::LDRSH_POST: {
2948 unsigned Rt = MI.getOperand(0).getReg();
2949 unsigned Rm = MI.getOperand(3).getReg();
2950 return (Rt == Rm) ? 4 : 3;
2953 case ARM::LDR_PRE_REG:
2954 case ARM::LDRB_PRE_REG: {
2955 unsigned Rt = MI.getOperand(0).getReg();
2956 unsigned Rm = MI.getOperand(3).getReg();
2959 unsigned ShOpVal = MI.getOperand(4).getImm();
2960 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2961 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2964 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2965 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2970 case ARM::STR_PRE_REG:
2971 case ARM::STRB_PRE_REG: {
2972 unsigned ShOpVal = MI.getOperand(4).getImm();
2973 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
2974 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
2977 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
2978 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
2984 case ARM::STRH_PRE: {
2985 unsigned Rt = MI.getOperand(0).getReg();
2986 unsigned Rm = MI.getOperand(3).getReg();
2991 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 3 : 2;
2994 case ARM::LDR_POST_REG:
2995 case ARM::LDRB_POST_REG:
2996 case ARM::LDRH_POST: {
2997 unsigned Rt = MI.getOperand(0).getReg();
2998 unsigned Rm = MI.getOperand(3).getReg();
2999 return (Rt == Rm) ? 3 : 2;
3002 case ARM::LDR_PRE_IMM:
3003 case ARM::LDRB_PRE_IMM:
3004 case ARM::LDR_POST_IMM:
3005 case ARM::LDRB_POST_IMM:
3006 case ARM::STRB_POST_IMM:
3007 case ARM::STRB_POST_REG:
3008 case ARM::STRB_PRE_IMM:
3009 case ARM::STRH_POST:
3010 case ARM::STR_POST_IMM:
3011 case ARM::STR_POST_REG:
3012 case ARM::STR_PRE_IMM:
3015 case ARM::LDRSB_PRE:
3016 case ARM::LDRSH_PRE: {
3017 unsigned Rm = MI.getOperand(3).getReg();
3020 unsigned Rt = MI.getOperand(0).getReg();
3023 unsigned ShOpVal = MI.getOperand(4).getImm();
3024 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3025 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3028 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3029 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3035 unsigned Rt = MI.getOperand(0).getReg();
3036 unsigned Rn = MI.getOperand(2).getReg();
3037 unsigned Rm = MI.getOperand(3).getReg();
3039 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3041 return (Rt == Rn) ? 3 : 2;
3045 unsigned Rm = MI.getOperand(3).getReg();
3047 return (ARM_AM::getAM3Op(MI.getOperand(4).getImm()) == ARM_AM::sub) ? 4
3052 case ARM::LDRD_POST:
3053 case ARM::t2LDRD_POST:
3056 case ARM::STRD_POST:
3057 case ARM::t2STRD_POST:
3060 case ARM::LDRD_PRE: {
3061 unsigned Rt = MI.getOperand(0).getReg();
3062 unsigned Rn = MI.getOperand(3).getReg();
3063 unsigned Rm = MI.getOperand(4).getReg();
3065 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3067 return (Rt == Rn) ? 4 : 3;
3070 case ARM::t2LDRD_PRE: {
3071 unsigned Rt = MI.getOperand(0).getReg();
3072 unsigned Rn = MI.getOperand(3).getReg();
3073 return (Rt == Rn) ? 4 : 3;
3076 case ARM::STRD_PRE: {
3077 unsigned Rm = MI.getOperand(4).getReg();
3079 return (ARM_AM::getAM3Op(MI.getOperand(5).getImm()) == ARM_AM::sub) ? 5
3084 case ARM::t2STRD_PRE:
3087 case ARM::t2LDR_POST:
3088 case ARM::t2LDRB_POST:
3089 case ARM::t2LDRB_PRE:
3090 case ARM::t2LDRSBi12:
3091 case ARM::t2LDRSBi8:
3092 case ARM::t2LDRSBpci:
3094 case ARM::t2LDRH_POST:
3095 case ARM::t2LDRH_PRE:
3097 case ARM::t2LDRSB_POST:
3098 case ARM::t2LDRSB_PRE:
3099 case ARM::t2LDRSH_POST:
3100 case ARM::t2LDRSH_PRE:
3101 case ARM::t2LDRSHi12:
3102 case ARM::t2LDRSHi8:
3103 case ARM::t2LDRSHpci:
3107 case ARM::t2LDRDi8: {
3108 unsigned Rt = MI.getOperand(0).getReg();
3109 unsigned Rn = MI.getOperand(2).getReg();
3110 return (Rt == Rn) ? 3 : 2;
3113 case ARM::t2STRB_POST:
3114 case ARM::t2STRB_PRE:
3117 case ARM::t2STRH_POST:
3118 case ARM::t2STRH_PRE:
3120 case ARM::t2STR_POST:
3121 case ARM::t2STR_PRE:
3127 // Return the number of 32-bit words loaded by LDM or stored by STM. If this
3128 // can't be easily determined return 0 (missing MachineMemOperand).
3130 // FIXME: The current MachineInstr design does not support relying on machine
3131 // mem operands to determine the width of a memory access. Instead, we expect
3132 // the target to provide this information based on the instruction opcode and
3133 // operands. However, using MachineMemOperand is the best solution now for
3136 // 1) getNumMicroOps tries to infer LDM memory width from the total number of MI
3137 // operands. This is much more dangerous than using the MachineMemOperand
3138 // sizes because CodeGen passes can insert/remove optional machine operands. In
3139 // fact, it's totally incorrect for preRA passes and appears to be wrong for
3140 // postRA passes as well.
3142 // 2) getNumLDMAddresses is only used by the scheduling machine model and any
3143 // machine model that calls this should handle the unknown (zero size) case.
3145 // Long term, we should require a target hook that verifies MachineMemOperand
3146 // sizes during MC lowering. That target hook should be local to MC lowering
3147 // because we can't ensure that it is aware of other MI forms. Doing this will
3148 // ensure that MachineMemOperands are correctly propagated through all passes.
3149 unsigned ARMBaseInstrInfo::getNumLDMAddresses(const MachineInstr &MI) const {
3151 for (MachineInstr::mmo_iterator I = MI.memoperands_begin(),
3152 E = MI.memoperands_end();
3154 Size += (*I)->getSize();
3159 static unsigned getNumMicroOpsSingleIssuePlusExtras(unsigned Opc,
3161 unsigned UOps = 1 + NumRegs; // 1 for address computation.
3165 case ARM::VLDMDIA_UPD:
3166 case ARM::VLDMDDB_UPD:
3167 case ARM::VLDMSIA_UPD:
3168 case ARM::VLDMSDB_UPD:
3169 case ARM::VSTMDIA_UPD:
3170 case ARM::VSTMDDB_UPD:
3171 case ARM::VSTMSIA_UPD:
3172 case ARM::VSTMSDB_UPD:
3173 case ARM::LDMIA_UPD:
3174 case ARM::LDMDA_UPD:
3175 case ARM::LDMDB_UPD:
3176 case ARM::LDMIB_UPD:
3177 case ARM::STMIA_UPD:
3178 case ARM::STMDA_UPD:
3179 case ARM::STMDB_UPD:
3180 case ARM::STMIB_UPD:
3181 case ARM::tLDMIA_UPD:
3182 case ARM::tSTMIA_UPD:
3183 case ARM::t2LDMIA_UPD:
3184 case ARM::t2LDMDB_UPD:
3185 case ARM::t2STMIA_UPD:
3186 case ARM::t2STMDB_UPD:
3187 ++UOps; // One for base register writeback.
3189 case ARM::LDMIA_RET:
3191 case ARM::t2LDMIA_RET:
3192 UOps += 2; // One for base reg wb, one for write to pc.
3198 unsigned ARMBaseInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
3199 const MachineInstr &MI) const {
3200 if (!ItinData || ItinData->isEmpty())
3203 const MCInstrDesc &Desc = MI.getDesc();
3204 unsigned Class = Desc.getSchedClass();
3205 int ItinUOps = ItinData->getNumMicroOps(Class);
3206 if (ItinUOps >= 0) {
3207 if (Subtarget.isSwift() && (Desc.mayLoad() || Desc.mayStore()))
3208 return getNumMicroOpsSwiftLdSt(ItinData, MI);
3213 unsigned Opc = MI.getOpcode();
3216 llvm_unreachable("Unexpected multi-uops instruction!");
3221 // The number of uOps for load / store multiple are determined by the number
3224 // On Cortex-A8, each pair of register loads / stores can be scheduled on the
3225 // same cycle. The scheduling for the first load / store must be done
3226 // separately by assuming the address is not 64-bit aligned.
3228 // On Cortex-A9, the formula is simply (#reg / 2) + (#reg % 2). If the address
3229 // is not 64-bit aligned, then AGU would take an extra cycle. For VFP / NEON
3230 // load / store multiple, the formula is (#reg / 2) + (#reg % 2) + 1.
3232 case ARM::VLDMDIA_UPD:
3233 case ARM::VLDMDDB_UPD:
3235 case ARM::VLDMSIA_UPD:
3236 case ARM::VLDMSDB_UPD:
3238 case ARM::VSTMDIA_UPD:
3239 case ARM::VSTMDDB_UPD:
3241 case ARM::VSTMSIA_UPD:
3242 case ARM::VSTMSDB_UPD: {
3243 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands();
3244 return (NumRegs / 2) + (NumRegs % 2) + 1;
3247 case ARM::LDMIA_RET:
3252 case ARM::LDMIA_UPD:
3253 case ARM::LDMDA_UPD:
3254 case ARM::LDMDB_UPD:
3255 case ARM::LDMIB_UPD:
3260 case ARM::STMIA_UPD:
3261 case ARM::STMDA_UPD:
3262 case ARM::STMDB_UPD:
3263 case ARM::STMIB_UPD:
3265 case ARM::tLDMIA_UPD:
3266 case ARM::tSTMIA_UPD:
3270 case ARM::t2LDMIA_RET:
3273 case ARM::t2LDMIA_UPD:
3274 case ARM::t2LDMDB_UPD:
3277 case ARM::t2STMIA_UPD:
3278 case ARM::t2STMDB_UPD: {
3279 unsigned NumRegs = MI.getNumOperands() - Desc.getNumOperands() + 1;
3280 switch (Subtarget.getLdStMultipleTiming()) {
3281 case ARMSubtarget::SingleIssuePlusExtras:
3282 return getNumMicroOpsSingleIssuePlusExtras(Opc, NumRegs);
3283 case ARMSubtarget::SingleIssue:
3284 // Assume the worst.
3286 case ARMSubtarget::DoubleIssue: {
3289 // 4 registers would be issued: 2, 2.
3290 // 5 registers would be issued: 2, 2, 1.
3291 unsigned UOps = (NumRegs / 2);
3296 case ARMSubtarget::DoubleIssueCheckUnalignedAccess: {
3297 unsigned UOps = (NumRegs / 2);
3298 // If there are odd number of registers or if it's not 64-bit aligned,
3299 // then it takes an extra AGU (Address Generation Unit) cycle.
3300 if ((NumRegs % 2) || !MI.hasOneMemOperand() ||
3301 (*MI.memoperands_begin())->getAlignment() < 8)
3308 llvm_unreachable("Didn't find the number of microops");
3312 ARMBaseInstrInfo::getVLDMDefCycle(const InstrItineraryData *ItinData,
3313 const MCInstrDesc &DefMCID,
3315 unsigned DefIdx, unsigned DefAlign) const {
3316 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3318 // Def is the address writeback.
3319 return ItinData->getOperandCycle(DefClass, DefIdx);
3322 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3323 // (regno / 2) + (regno % 2) + 1
3324 DefCycle = RegNo / 2 + 1;
3327 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3329 bool isSLoad = false;
3331 switch (DefMCID.getOpcode()) {
3334 case ARM::VLDMSIA_UPD:
3335 case ARM::VLDMSDB_UPD:
3340 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3341 // then it takes an extra cycle.
3342 if ((isSLoad && (RegNo % 2)) || DefAlign < 8)
3345 // Assume the worst.
3346 DefCycle = RegNo + 2;
3353 ARMBaseInstrInfo::getLDMDefCycle(const InstrItineraryData *ItinData,
3354 const MCInstrDesc &DefMCID,
3356 unsigned DefIdx, unsigned DefAlign) const {
3357 int RegNo = (int)(DefIdx+1) - DefMCID.getNumOperands() + 1;
3359 // Def is the address writeback.
3360 return ItinData->getOperandCycle(DefClass, DefIdx);
3363 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3364 // 4 registers would be issued: 1, 2, 1.
3365 // 5 registers would be issued: 1, 2, 2.
3366 DefCycle = RegNo / 2;
3369 // Result latency is issue cycle + 2: E2.
3371 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3372 DefCycle = (RegNo / 2);
3373 // If there are odd number of registers or if it's not 64-bit aligned,
3374 // then it takes an extra AGU (Address Generation Unit) cycle.
3375 if ((RegNo % 2) || DefAlign < 8)
3377 // Result latency is AGU cycles + 2.
3380 // Assume the worst.
3381 DefCycle = RegNo + 2;
3388 ARMBaseInstrInfo::getVSTMUseCycle(const InstrItineraryData *ItinData,
3389 const MCInstrDesc &UseMCID,
3391 unsigned UseIdx, unsigned UseAlign) const {
3392 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3394 return ItinData->getOperandCycle(UseClass, UseIdx);
3397 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3398 // (regno / 2) + (regno % 2) + 1
3399 UseCycle = RegNo / 2 + 1;
3402 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3404 bool isSStore = false;
3406 switch (UseMCID.getOpcode()) {
3409 case ARM::VSTMSIA_UPD:
3410 case ARM::VSTMSDB_UPD:
3415 // If there are odd number of 'S' registers or if it's not 64-bit aligned,
3416 // then it takes an extra cycle.
3417 if ((isSStore && (RegNo % 2)) || UseAlign < 8)
3420 // Assume the worst.
3421 UseCycle = RegNo + 2;
3428 ARMBaseInstrInfo::getSTMUseCycle(const InstrItineraryData *ItinData,
3429 const MCInstrDesc &UseMCID,
3431 unsigned UseIdx, unsigned UseAlign) const {
3432 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1;
3434 return ItinData->getOperandCycle(UseClass, UseIdx);
3437 if (Subtarget.isCortexA8() || Subtarget.isCortexA7()) {
3438 UseCycle = RegNo / 2;
3443 } else if (Subtarget.isLikeA9() || Subtarget.isSwift()) {
3444 UseCycle = (RegNo / 2);
3445 // If there are odd number of registers or if it's not 64-bit aligned,
3446 // then it takes an extra AGU (Address Generation Unit) cycle.
3447 if ((RegNo % 2) || UseAlign < 8)
3450 // Assume the worst.
3457 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3458 const MCInstrDesc &DefMCID,
3459 unsigned DefIdx, unsigned DefAlign,
3460 const MCInstrDesc &UseMCID,
3461 unsigned UseIdx, unsigned UseAlign) const {
3462 unsigned DefClass = DefMCID.getSchedClass();
3463 unsigned UseClass = UseMCID.getSchedClass();
3465 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands())
3466 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
3468 // This may be a def / use of a variable_ops instruction, the operand
3469 // latency might be determinable dynamically. Let the target try to
3472 bool LdmBypass = false;
3473 switch (DefMCID.getOpcode()) {
3475 DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
3479 case ARM::VLDMDIA_UPD:
3480 case ARM::VLDMDDB_UPD:
3482 case ARM::VLDMSIA_UPD:
3483 case ARM::VLDMSDB_UPD:
3484 DefCycle = getVLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3487 case ARM::LDMIA_RET:
3492 case ARM::LDMIA_UPD:
3493 case ARM::LDMDA_UPD:
3494 case ARM::LDMDB_UPD:
3495 case ARM::LDMIB_UPD:
3497 case ARM::tLDMIA_UPD:
3499 case ARM::t2LDMIA_RET:
3502 case ARM::t2LDMIA_UPD:
3503 case ARM::t2LDMDB_UPD:
3505 DefCycle = getLDMDefCycle(ItinData, DefMCID, DefClass, DefIdx, DefAlign);
3510 // We can't seem to determine the result latency of the def, assume it's 2.
3514 switch (UseMCID.getOpcode()) {
3516 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx);
3520 case ARM::VSTMDIA_UPD:
3521 case ARM::VSTMDDB_UPD:
3523 case ARM::VSTMSIA_UPD:
3524 case ARM::VSTMSDB_UPD:
3525 UseCycle = getVSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3532 case ARM::STMIA_UPD:
3533 case ARM::STMDA_UPD:
3534 case ARM::STMDB_UPD:
3535 case ARM::STMIB_UPD:
3536 case ARM::tSTMIA_UPD:
3541 case ARM::t2STMIA_UPD:
3542 case ARM::t2STMDB_UPD:
3543 UseCycle = getSTMUseCycle(ItinData, UseMCID, UseClass, UseIdx, UseAlign);
3548 // Assume it's read in the first stage.
3551 UseCycle = DefCycle - UseCycle + 1;
3554 // It's a variable_ops instruction so we can't use DefIdx here. Just use
3555 // first def operand.
3556 if (ItinData->hasPipelineForwarding(DefClass, DefMCID.getNumOperands()-1,
3559 } else if (ItinData->hasPipelineForwarding(DefClass, DefIdx,
3560 UseClass, UseIdx)) {
3568 static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI,
3569 const MachineInstr *MI, unsigned Reg,
3570 unsigned &DefIdx, unsigned &Dist) {
3573 MachineBasicBlock::const_iterator I = MI; ++I;
3574 MachineBasicBlock::const_instr_iterator II = std::prev(I.getInstrIterator());
3575 assert(II->isInsideBundle() && "Empty bundle?");
3578 while (II->isInsideBundle()) {
3579 Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI);
3586 assert(Idx != -1 && "Cannot find bundled definition!");
3591 static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI,
3592 const MachineInstr &MI, unsigned Reg,
3593 unsigned &UseIdx, unsigned &Dist) {
3596 MachineBasicBlock::const_instr_iterator II = ++MI.getIterator();
3597 assert(II->isInsideBundle() && "Empty bundle?");
3598 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
3600 // FIXME: This doesn't properly handle multiple uses.
3602 while (II != E && II->isInsideBundle()) {
3603 Idx = II->findRegisterUseOperandIdx(Reg, false, TRI);
3606 if (II->getOpcode() != ARM::t2IT)
3620 /// Return the number of cycles to add to (or subtract from) the static
3621 /// itinerary based on the def opcode and alignment. The caller will ensure that
3622 /// adjusted latency is at least one cycle.
3623 static int adjustDefLatency(const ARMSubtarget &Subtarget,
3624 const MachineInstr &DefMI,
3625 const MCInstrDesc &DefMCID, unsigned DefAlign) {
3627 if (Subtarget.isCortexA8() || Subtarget.isLikeA9() || Subtarget.isCortexA7()) {
3628 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3629 // variants are one cycle cheaper.
3630 switch (DefMCID.getOpcode()) {
3634 unsigned ShOpVal = DefMI.getOperand(3).getImm();
3635 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3637 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3644 case ARM::t2LDRSHs: {
3645 // Thumb2 mode: lsl only.
3646 unsigned ShAmt = DefMI.getOperand(3).getImm();
3647 if (ShAmt == 0 || ShAmt == 2)
3652 } else if (Subtarget.isSwift()) {
3653 // FIXME: Properly handle all of the latency adjustments for address
3655 switch (DefMCID.getOpcode()) {
3659 unsigned ShOpVal = DefMI.getOperand(3).getImm();
3660 bool isSub = ARM_AM::getAM2Op(ShOpVal) == ARM_AM::sub;
3661 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3664 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3665 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl)))
3668 ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3675 case ARM::t2LDRSHs: {
3676 // Thumb2 mode: lsl only.
3677 unsigned ShAmt = DefMI.getOperand(3).getImm();
3678 if (ShAmt == 0 || ShAmt == 1 || ShAmt == 2 || ShAmt == 3)
3685 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment()) {
3686 switch (DefMCID.getOpcode()) {
3692 case ARM::VLD1q8wb_fixed:
3693 case ARM::VLD1q16wb_fixed:
3694 case ARM::VLD1q32wb_fixed:
3695 case ARM::VLD1q64wb_fixed:
3696 case ARM::VLD1q8wb_register:
3697 case ARM::VLD1q16wb_register:
3698 case ARM::VLD1q32wb_register:
3699 case ARM::VLD1q64wb_register:
3706 case ARM::VLD2d8wb_fixed:
3707 case ARM::VLD2d16wb_fixed:
3708 case ARM::VLD2d32wb_fixed:
3709 case ARM::VLD2q8wb_fixed:
3710 case ARM::VLD2q16wb_fixed:
3711 case ARM::VLD2q32wb_fixed:
3712 case ARM::VLD2d8wb_register:
3713 case ARM::VLD2d16wb_register:
3714 case ARM::VLD2d32wb_register:
3715 case ARM::VLD2q8wb_register:
3716 case ARM::VLD2q16wb_register:
3717 case ARM::VLD2q32wb_register:
3722 case ARM::VLD3d8_UPD:
3723 case ARM::VLD3d16_UPD:
3724 case ARM::VLD3d32_UPD:
3725 case ARM::VLD1d64Twb_fixed:
3726 case ARM::VLD1d64Twb_register:
3727 case ARM::VLD3q8_UPD:
3728 case ARM::VLD3q16_UPD:
3729 case ARM::VLD3q32_UPD:
3734 case ARM::VLD4d8_UPD:
3735 case ARM::VLD4d16_UPD:
3736 case ARM::VLD4d32_UPD:
3737 case ARM::VLD1d64Qwb_fixed:
3738 case ARM::VLD1d64Qwb_register:
3739 case ARM::VLD4q8_UPD:
3740 case ARM::VLD4q16_UPD:
3741 case ARM::VLD4q32_UPD:
3742 case ARM::VLD1DUPq8:
3743 case ARM::VLD1DUPq16:
3744 case ARM::VLD1DUPq32:
3745 case ARM::VLD1DUPq8wb_fixed:
3746 case ARM::VLD1DUPq16wb_fixed:
3747 case ARM::VLD1DUPq32wb_fixed:
3748 case ARM::VLD1DUPq8wb_register:
3749 case ARM::VLD1DUPq16wb_register:
3750 case ARM::VLD1DUPq32wb_register:
3751 case ARM::VLD2DUPd8:
3752 case ARM::VLD2DUPd16:
3753 case ARM::VLD2DUPd32:
3754 case ARM::VLD2DUPd8wb_fixed:
3755 case ARM::VLD2DUPd16wb_fixed:
3756 case ARM::VLD2DUPd32wb_fixed:
3757 case ARM::VLD2DUPd8wb_register:
3758 case ARM::VLD2DUPd16wb_register:
3759 case ARM::VLD2DUPd32wb_register:
3760 case ARM::VLD4DUPd8:
3761 case ARM::VLD4DUPd16:
3762 case ARM::VLD4DUPd32:
3763 case ARM::VLD4DUPd8_UPD:
3764 case ARM::VLD4DUPd16_UPD:
3765 case ARM::VLD4DUPd32_UPD:
3767 case ARM::VLD1LNd16:
3768 case ARM::VLD1LNd32:
3769 case ARM::VLD1LNd8_UPD:
3770 case ARM::VLD1LNd16_UPD:
3771 case ARM::VLD1LNd32_UPD:
3773 case ARM::VLD2LNd16:
3774 case ARM::VLD2LNd32:
3775 case ARM::VLD2LNq16:
3776 case ARM::VLD2LNq32:
3777 case ARM::VLD2LNd8_UPD:
3778 case ARM::VLD2LNd16_UPD:
3779 case ARM::VLD2LNd32_UPD:
3780 case ARM::VLD2LNq16_UPD:
3781 case ARM::VLD2LNq32_UPD:
3783 case ARM::VLD4LNd16:
3784 case ARM::VLD4LNd32:
3785 case ARM::VLD4LNq16:
3786 case ARM::VLD4LNq32:
3787 case ARM::VLD4LNd8_UPD:
3788 case ARM::VLD4LNd16_UPD:
3789 case ARM::VLD4LNd32_UPD:
3790 case ARM::VLD4LNq16_UPD:
3791 case ARM::VLD4LNq32_UPD:
3792 // If the address is not 64-bit aligned, the latencies of these
3793 // instructions increases by one.
3801 int ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3802 const MachineInstr &DefMI,
3804 const MachineInstr &UseMI,
3805 unsigned UseIdx) const {
3806 // No operand latency. The caller may fall back to getInstrLatency.
3807 if (!ItinData || ItinData->isEmpty())
3810 const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
3811 unsigned Reg = DefMO.getReg();
3813 const MachineInstr *ResolvedDefMI = &DefMI;
3814 unsigned DefAdj = 0;
3815 if (DefMI.isBundle())
3817 getBundledDefMI(&getRegisterInfo(), &DefMI, Reg, DefIdx, DefAdj);
3818 if (ResolvedDefMI->isCopyLike() || ResolvedDefMI->isInsertSubreg() ||
3819 ResolvedDefMI->isRegSequence() || ResolvedDefMI->isImplicitDef()) {
3823 const MachineInstr *ResolvedUseMI = &UseMI;
3824 unsigned UseAdj = 0;
3825 if (UseMI.isBundle()) {
3827 getBundledUseMI(&getRegisterInfo(), UseMI, Reg, UseIdx, UseAdj);
3832 return getOperandLatencyImpl(
3833 ItinData, *ResolvedDefMI, DefIdx, ResolvedDefMI->getDesc(), DefAdj, DefMO,
3834 Reg, *ResolvedUseMI, UseIdx, ResolvedUseMI->getDesc(), UseAdj);
3837 int ARMBaseInstrInfo::getOperandLatencyImpl(
3838 const InstrItineraryData *ItinData, const MachineInstr &DefMI,
3839 unsigned DefIdx, const MCInstrDesc &DefMCID, unsigned DefAdj,
3840 const MachineOperand &DefMO, unsigned Reg, const MachineInstr &UseMI,
3841 unsigned UseIdx, const MCInstrDesc &UseMCID, unsigned UseAdj) const {
3842 if (Reg == ARM::CPSR) {
3843 if (DefMI.getOpcode() == ARM::FMSTAT) {
3844 // fpscr -> cpsr stalls over 20 cycles on A8 (and earlier?)
3845 return Subtarget.isLikeA9() ? 1 : 20;
3848 // CPSR set and branch can be paired in the same cycle.
3849 if (UseMI.isBranch())
3852 // Otherwise it takes the instruction latency (generally one).
3853 unsigned Latency = getInstrLatency(ItinData, DefMI);
3855 // For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
3856 // its uses. Instructions which are otherwise scheduled between them may
3857 // incur a code size penalty (not able to use the CPSR setting 16-bit
3859 if (Latency > 0 && Subtarget.isThumb2()) {
3860 const MachineFunction *MF = DefMI.getParent()->getParent();
3861 // FIXME: Use Function::optForSize().
3862 if (MF->getFunction()->hasFnAttribute(Attribute::OptimizeForSize))
3868 if (DefMO.isImplicit() || UseMI.getOperand(UseIdx).isImplicit())
3871 unsigned DefAlign = DefMI.hasOneMemOperand()
3872 ? (*DefMI.memoperands_begin())->getAlignment()
3874 unsigned UseAlign = UseMI.hasOneMemOperand()
3875 ? (*UseMI.memoperands_begin())->getAlignment()
3878 // Get the itinerary's latency if possible, and handle variable_ops.
3879 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign, UseMCID,
3881 // Unable to find operand latency. The caller may resort to getInstrLatency.
3885 // Adjust for IT block position.
3886 int Adj = DefAdj + UseAdj;
3888 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
3889 Adj += adjustDefLatency(Subtarget, DefMI, DefMCID, DefAlign);
3890 if (Adj >= 0 || (int)Latency > -Adj) {
3891 return Latency + Adj;
3893 // Return the itinerary latency, which may be zero but not less than zero.
3898 ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
3899 SDNode *DefNode, unsigned DefIdx,
3900 SDNode *UseNode, unsigned UseIdx) const {
3901 if (!DefNode->isMachineOpcode())
3904 const MCInstrDesc &DefMCID = get(DefNode->getMachineOpcode());
3906 if (isZeroCost(DefMCID.Opcode))
3909 if (!ItinData || ItinData->isEmpty())
3910 return DefMCID.mayLoad() ? 3 : 1;
3912 if (!UseNode->isMachineOpcode()) {
3913 int Latency = ItinData->getOperandCycle(DefMCID.getSchedClass(), DefIdx);
3914 int Adj = Subtarget.getPreISelOperandLatencyAdjustment();
3915 int Threshold = 1 + Adj;
3916 return Latency <= Threshold ? 1 : Latency - Adj;
3919 const MCInstrDesc &UseMCID = get(UseNode->getMachineOpcode());
3920 const MachineSDNode *DefMN = dyn_cast<MachineSDNode>(DefNode);
3921 unsigned DefAlign = !DefMN->memoperands_empty()
3922 ? (*DefMN->memoperands_begin())->getAlignment() : 0;
3923 const MachineSDNode *UseMN = dyn_cast<MachineSDNode>(UseNode);
3924 unsigned UseAlign = !UseMN->memoperands_empty()
3925 ? (*UseMN->memoperands_begin())->getAlignment() : 0;
3926 int Latency = getOperandLatency(ItinData, DefMCID, DefIdx, DefAlign,
3927 UseMCID, UseIdx, UseAlign);
3930 (Subtarget.isCortexA8() || Subtarget.isLikeA9() ||
3931 Subtarget.isCortexA7())) {
3932 // FIXME: Shifter op hack: no shift (i.e. [r +/- r]) or [r + r << 2]
3933 // variants are one cycle cheaper.
3934 switch (DefMCID.getOpcode()) {
3939 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3940 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3942 (ShImm == 2 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3949 case ARM::t2LDRSHs: {
3950 // Thumb2 mode: lsl only.
3952 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3953 if (ShAmt == 0 || ShAmt == 2)
3958 } else if (DefIdx == 0 && Latency > 2 && Subtarget.isSwift()) {
3959 // FIXME: Properly handle all of the latency adjustments for address
3961 switch (DefMCID.getOpcode()) {
3966 cast<ConstantSDNode>(DefNode->getOperand(2))->getZExtValue();
3967 unsigned ShImm = ARM_AM::getAM2Offset(ShOpVal);
3969 ((ShImm == 1 || ShImm == 2 || ShImm == 3) &&
3970 ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsl))
3972 else if (ShImm == 1 && ARM_AM::getAM2ShiftOpc(ShOpVal) == ARM_AM::lsr)
3980 // Thumb2 mode: lsl 0-3 only.
3986 if (DefAlign < 8 && Subtarget.checkVLDnAccessAlignment())
3987 switch (DefMCID.getOpcode()) {
3993 case ARM::VLD1q8wb_register:
3994 case ARM::VLD1q16wb_register:
3995 case ARM::VLD1q32wb_register:
3996 case ARM::VLD1q64wb_register:
3997 case ARM::VLD1q8wb_fixed:
3998 case ARM::VLD1q16wb_fixed:
3999 case ARM::VLD1q32wb_fixed:
4000 case ARM::VLD1q64wb_fixed:
4004 case ARM::VLD2q8Pseudo:
4005 case ARM::VLD2q16Pseudo:
4006 case ARM::VLD2q32Pseudo:
4007 case ARM::VLD2d8wb_fixed:
4008 case ARM::VLD2d16wb_fixed:
4009 case ARM::VLD2d32wb_fixed:
4010 case ARM::VLD2q8PseudoWB_fixed:
4011 case ARM::VLD2q16PseudoWB_fixed:
4012 case ARM::VLD2q32PseudoWB_fixed:
4013 case ARM::VLD2d8wb_register:
4014 case ARM::VLD2d16wb_register:
4015 case ARM::VLD2d32wb_register:
4016 case ARM::VLD2q8PseudoWB_register:
4017 case ARM::VLD2q16PseudoWB_register:
4018 case ARM::VLD2q32PseudoWB_register:
4019 case ARM::VLD3d8Pseudo:
4020 case ARM::VLD3d16Pseudo:
4021 case ARM::VLD3d32Pseudo:
4022 case ARM::VLD1d64TPseudo:
4023 case ARM::VLD1d64TPseudoWB_fixed:
4024 case ARM::VLD3d8Pseudo_UPD:
4025 case ARM::VLD3d16Pseudo_UPD:
4026 case ARM::VLD3d32Pseudo_UPD:
4027 case ARM::VLD3q8Pseudo_UPD:
4028 case ARM::VLD3q16Pseudo_UPD:
4029 case ARM::VLD3q32Pseudo_UPD:
4030 case ARM::VLD3q8oddPseudo:
4031 case ARM::VLD3q16oddPseudo:
4032 case ARM::VLD3q32oddPseudo:
4033 case ARM::VLD3q8oddPseudo_UPD:
4034 case ARM::VLD3q16oddPseudo_UPD:
4035 case ARM::VLD3q32oddPseudo_UPD:
4036 case ARM::VLD4d8Pseudo:
4037 case ARM::VLD4d16Pseudo:
4038 case ARM::VLD4d32Pseudo:
4039 case ARM::VLD1d64QPseudo:
4040 case ARM::VLD1d64QPseudoWB_fixed:
4041 case ARM::VLD4d8Pseudo_UPD:
4042 case ARM::VLD4d16Pseudo_UPD:
4043 case ARM::VLD4d32Pseudo_UPD:
4044 case ARM::VLD4q8Pseudo_UPD:
4045 case ARM::VLD4q16Pseudo_UPD:
4046 case ARM::VLD4q32Pseudo_UPD:
4047 case ARM::VLD4q8oddPseudo:
4048 case ARM::VLD4q16oddPseudo:
4049 case ARM::VLD4q32oddPseudo:
4050 case ARM::VLD4q8oddPseudo_UPD:
4051 case ARM::VLD4q16oddPseudo_UPD:
4052 case ARM::VLD4q32oddPseudo_UPD:
4053 case ARM::VLD1DUPq8:
4054 case ARM::VLD1DUPq16:
4055 case ARM::VLD1DUPq32:
4056 case ARM::VLD1DUPq8wb_fixed:
4057 case ARM::VLD1DUPq16wb_fixed:
4058 case ARM::VLD1DUPq32wb_fixed:
4059 case ARM::VLD1DUPq8wb_register:
4060 case ARM::VLD1DUPq16wb_register:
4061 case ARM::VLD1DUPq32wb_register:
4062 case ARM::VLD2DUPd8:
4063 case ARM::VLD2DUPd16:
4064 case ARM::VLD2DUPd32:
4065 case ARM::VLD2DUPd8wb_fixed:
4066 case ARM::VLD2DUPd16wb_fixed:
4067 case ARM::VLD2DUPd32wb_fixed:
4068 case ARM::VLD2DUPd8wb_register:
4069 case ARM::VLD2DUPd16wb_register:
4070 case ARM::VLD2DUPd32wb_register:
4071 case ARM::VLD4DUPd8Pseudo:
4072 case ARM::VLD4DUPd16Pseudo:
4073 case ARM::VLD4DUPd32Pseudo:
4074 case ARM::VLD4DUPd8Pseudo_UPD:
4075 case ARM::VLD4DUPd16Pseudo_UPD:
4076 case ARM::VLD4DUPd32Pseudo_UPD:
4077 case ARM::VLD1LNq8Pseudo:
4078 case ARM::VLD1LNq16Pseudo:
4079 case ARM::VLD1LNq32Pseudo:
4080 case ARM::VLD1LNq8Pseudo_UPD:
4081 case ARM::VLD1LNq16Pseudo_UPD:
4082 case ARM::VLD1LNq32Pseudo_UPD:
4083 case ARM::VLD2LNd8Pseudo:
4084 case ARM::VLD2LNd16Pseudo:
4085 case ARM::VLD2LNd32Pseudo:
4086 case ARM::VLD2LNq16Pseudo:
4087 case ARM::VLD2LNq32Pseudo:
4088 case ARM::VLD2LNd8Pseudo_UPD:
4089 case ARM::VLD2LNd16Pseudo_UPD:
4090 case ARM::VLD2LNd32Pseudo_UPD:
4091 case ARM::VLD2LNq16Pseudo_UPD:
4092 case ARM::VLD2LNq32Pseudo_UPD:
4093 case ARM::VLD4LNd8Pseudo:
4094 case ARM::VLD4LNd16Pseudo:
4095 case ARM::VLD4LNd32Pseudo:
4096 case ARM::VLD4LNq16Pseudo:
4097 case ARM::VLD4LNq32Pseudo:
4098 case ARM::VLD4LNd8Pseudo_UPD:
4099 case ARM::VLD4LNd16Pseudo_UPD:
4100 case ARM::VLD4LNd32Pseudo_UPD:
4101 case ARM::VLD4LNq16Pseudo_UPD:
4102 case ARM::VLD4LNq32Pseudo_UPD:
4103 // If the address is not 64-bit aligned, the latencies of these
4104 // instructions increases by one.
4112 unsigned ARMBaseInstrInfo::getPredicationCost(const MachineInstr &MI) const {
4113 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4120 const MCInstrDesc &MCID = MI.getDesc();
4122 if (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)) {
4123 // When predicated, CPSR is an additional source operand for CPSR updating
4124 // instructions, this apparently increases their latencies.
4130 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4131 const MachineInstr &MI,
4132 unsigned *PredCost) const {
4133 if (MI.isCopyLike() || MI.isInsertSubreg() || MI.isRegSequence() ||
4137 // An instruction scheduler typically runs on unbundled instructions, however
4138 // other passes may query the latency of a bundled instruction.
4139 if (MI.isBundle()) {
4140 unsigned Latency = 0;
4141 MachineBasicBlock::const_instr_iterator I = MI.getIterator();
4142 MachineBasicBlock::const_instr_iterator E = MI.getParent()->instr_end();
4143 while (++I != E && I->isInsideBundle()) {
4144 if (I->getOpcode() != ARM::t2IT)
4145 Latency += getInstrLatency(ItinData, *I, PredCost);
4150 const MCInstrDesc &MCID = MI.getDesc();
4151 if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
4152 // When predicated, CPSR is an additional source operand for CPSR updating
4153 // instructions, this apparently increases their latencies.
4156 // Be sure to call getStageLatency for an empty itinerary in case it has a
4157 // valid MinLatency property.
4159 return MI.mayLoad() ? 3 : 1;
4161 unsigned Class = MCID.getSchedClass();
4163 // For instructions with variable uops, use uops as latency.
4164 if (!ItinData->isEmpty() && ItinData->getNumMicroOps(Class) < 0)
4165 return getNumMicroOps(ItinData, MI);
4167 // For the common case, fall back on the itinerary's latency.
4168 unsigned Latency = ItinData->getStageLatency(Class);
4170 // Adjust for dynamic def-side opcode variants not captured by the itinerary.
4172 MI.hasOneMemOperand() ? (*MI.memoperands_begin())->getAlignment() : 0;
4173 int Adj = adjustDefLatency(Subtarget, MI, MCID, DefAlign);
4174 if (Adj >= 0 || (int)Latency > -Adj) {
4175 return Latency + Adj;
4180 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
4181 SDNode *Node) const {
4182 if (!Node->isMachineOpcode())
4185 if (!ItinData || ItinData->isEmpty())
4188 unsigned Opcode = Node->getMachineOpcode();
4191 return ItinData->getStageLatency(get(Opcode).getSchedClass());
4198 bool ARMBaseInstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
4199 const MachineRegisterInfo *MRI,
4200 const MachineInstr &DefMI,
4202 const MachineInstr &UseMI,
4203 unsigned UseIdx) const {
4204 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4205 unsigned UDomain = UseMI.getDesc().TSFlags & ARMII::DomainMask;
4206 if (Subtarget.nonpipelinedVFP() &&
4207 (DDomain == ARMII::DomainVFP || UDomain == ARMII::DomainVFP))
4210 // Hoist VFP / NEON instructions with 4 or higher latency.
4212 SchedModel.computeOperandLatency(&DefMI, DefIdx, &UseMI, UseIdx);
4215 return DDomain == ARMII::DomainVFP || DDomain == ARMII::DomainNEON ||
4216 UDomain == ARMII::DomainVFP || UDomain == ARMII::DomainNEON;
4219 bool ARMBaseInstrInfo::hasLowDefLatency(const TargetSchedModel &SchedModel,
4220 const MachineInstr &DefMI,
4221 unsigned DefIdx) const {
4222 const InstrItineraryData *ItinData = SchedModel.getInstrItineraries();
4223 if (!ItinData || ItinData->isEmpty())
4226 unsigned DDomain = DefMI.getDesc().TSFlags & ARMII::DomainMask;
4227 if (DDomain == ARMII::DomainGeneral) {
4228 unsigned DefClass = DefMI.getDesc().getSchedClass();
4229 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
4230 return (DefCycle != -1 && DefCycle <= 2);
4235 bool ARMBaseInstrInfo::verifyInstruction(const MachineInstr &MI,
4236 StringRef &ErrInfo) const {
4237 if (convertAddSubFlagsOpcode(MI.getOpcode())) {
4238 ErrInfo = "Pseudo flag setting opcodes only exist in Selection DAG";
4244 // LoadStackGuard has so far only been implemented for MachO. Different code
4245 // sequence is needed for other targets.
4246 void ARMBaseInstrInfo::expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
4247 unsigned LoadImmOpc,
4248 unsigned LoadOpc) const {
4249 assert(!Subtarget.isROPI() && !Subtarget.isRWPI() &&
4250 "ROPI/RWPI not currently supported with stack guard");
4252 MachineBasicBlock &MBB = *MI->getParent();
4253 DebugLoc DL = MI->getDebugLoc();
4254 unsigned Reg = MI->getOperand(0).getReg();
4255 const GlobalValue *GV =
4256 cast<GlobalValue>((*MI->memoperands_begin())->getValue());
4257 MachineInstrBuilder MIB;
4259 BuildMI(MBB, MI, DL, get(LoadImmOpc), Reg)
4260 .addGlobalAddress(GV, 0, ARMII::MO_NONLAZY);
4262 if (Subtarget.isGVIndirectSymbol(GV)) {
4263 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4264 MIB.addReg(Reg, RegState::Kill).addImm(0);
4265 auto Flags = MachineMemOperand::MOLoad |
4266 MachineMemOperand::MODereferenceable |
4267 MachineMemOperand::MOInvariant;
4268 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4269 MachinePointerInfo::getGOT(*MBB.getParent()), Flags, 4, 4);
4270 MIB.addMemOperand(MMO).add(predOps(ARMCC::AL));
4273 MIB = BuildMI(MBB, MI, DL, get(LoadOpc), Reg);
4274 MIB.addReg(Reg, RegState::Kill)
4276 .setMemRefs(MI->memoperands_begin(), MI->memoperands_end())
4277 .add(predOps(ARMCC::AL));
4281 ARMBaseInstrInfo::isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
4282 unsigned &AddSubOpc,
4283 bool &NegAcc, bool &HasLane) const {
4284 DenseMap<unsigned, unsigned>::const_iterator I = MLxEntryMap.find(Opcode);
4285 if (I == MLxEntryMap.end())
4288 const ARM_MLxEntry &Entry = ARM_MLxTable[I->second];
4289 MulOpc = Entry.MulOpc;
4290 AddSubOpc = Entry.AddSubOpc;
4291 NegAcc = Entry.NegAcc;
4292 HasLane = Entry.HasLane;
4296 //===----------------------------------------------------------------------===//
4297 // Execution domains.
4298 //===----------------------------------------------------------------------===//
4300 // Some instructions go down the NEON pipeline, some go down the VFP pipeline,
4301 // and some can go down both. The vmov instructions go down the VFP pipeline,
4302 // but they can be changed to vorr equivalents that are executed by the NEON
4305 // We use the following execution domain numbering:
4314 // Also see ARMInstrFormats.td and Domain* enums in ARMBaseInfo.h
4316 std::pair<uint16_t, uint16_t>
4317 ARMBaseInstrInfo::getExecutionDomain(const MachineInstr &MI) const {
4318 // If we don't have access to NEON instructions then we won't be able
4319 // to swizzle anything to the NEON domain. Check to make sure.
4320 if (Subtarget.hasNEON()) {
4321 // VMOVD, VMOVRS and VMOVSR are VFP instructions, but can be changed to NEON
4322 // if they are not predicated.
4323 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI))
4324 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4326 // CortexA9 is particularly picky about mixing the two and wants these
4328 if (Subtarget.useNEONForFPMovs() && !isPredicated(MI) &&
4329 (MI.getOpcode() == ARM::VMOVRS || MI.getOpcode() == ARM::VMOVSR ||
4330 MI.getOpcode() == ARM::VMOVS))
4331 return std::make_pair(ExeVFP, (1 << ExeVFP) | (1 << ExeNEON));
4333 // No other instructions can be swizzled, so just determine their domain.
4334 unsigned Domain = MI.getDesc().TSFlags & ARMII::DomainMask;
4336 if (Domain & ARMII::DomainNEON)
4337 return std::make_pair(ExeNEON, 0);
4339 // Certain instructions can go either way on Cortex-A8.
4340 // Treat them as NEON instructions.
4341 if ((Domain & ARMII::DomainNEONA8) && Subtarget.isCortexA8())
4342 return std::make_pair(ExeNEON, 0);
4344 if (Domain & ARMII::DomainVFP)
4345 return std::make_pair(ExeVFP, 0);
4347 return std::make_pair(ExeGeneric, 0);
4350 static unsigned getCorrespondingDRegAndLane(const TargetRegisterInfo *TRI,
4351 unsigned SReg, unsigned &Lane) {
4352 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_0, &ARM::DPRRegClass);
4355 if (DReg != ARM::NoRegister)
4359 DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1, &ARM::DPRRegClass);
4361 assert(DReg && "S-register with no D super-register?");
4365 /// getImplicitSPRUseForDPRUse - Given a use of a DPR register and lane,
4366 /// set ImplicitSReg to a register number that must be marked as implicit-use or
4367 /// zero if no register needs to be defined as implicit-use.
4369 /// If the function cannot determine if an SPR should be marked implicit use or
4370 /// not, it returns false.
4372 /// This function handles cases where an instruction is being modified from taking
4373 /// an SPR to a DPR[Lane]. A use of the DPR is being added, which may conflict
4374 /// with an earlier def of an SPR corresponding to DPR[Lane^1] (i.e. the other
4375 /// lane of the DPR).
4377 /// If the other SPR is defined, an implicit-use of it should be added. Else,
4378 /// (including the case where the DPR itself is defined), it should not.
4380 static bool getImplicitSPRUseForDPRUse(const TargetRegisterInfo *TRI,
4381 MachineInstr &MI, unsigned DReg,
4382 unsigned Lane, unsigned &ImplicitSReg) {
4383 // If the DPR is defined or used already, the other SPR lane will be chained
4384 // correctly, so there is nothing to be done.
4385 if (MI.definesRegister(DReg, TRI) || MI.readsRegister(DReg, TRI)) {
4390 // Otherwise we need to go searching to see if the SPR is set explicitly.
4391 ImplicitSReg = TRI->getSubReg(DReg,
4392 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1);
4393 MachineBasicBlock::LivenessQueryResult LQR =
4394 MI.getParent()->computeRegisterLiveness(TRI, ImplicitSReg, MI);
4396 if (LQR == MachineBasicBlock::LQR_Live)
4398 else if (LQR == MachineBasicBlock::LQR_Unknown)
4401 // If the register is known not to be live, there is no need to add an
4407 void ARMBaseInstrInfo::setExecutionDomain(MachineInstr &MI,
4408 unsigned Domain) const {
4409 unsigned DstReg, SrcReg, DReg;
4411 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
4412 const TargetRegisterInfo *TRI = &getRegisterInfo();
4413 switch (MI.getOpcode()) {
4415 llvm_unreachable("cannot handle opcode!");
4418 if (Domain != ExeNEON)
4421 // Zap the predicate operands.
4422 assert(!isPredicated(MI) && "Cannot predicate a VORRd");
4424 // Make sure we've got NEON instructions.
4425 assert(Subtarget.hasNEON() && "VORRd requires NEON");
4427 // Source instruction is %DDst = VMOVD %DSrc, 14, %noreg (; implicits)
4428 DstReg = MI.getOperand(0).getReg();
4429 SrcReg = MI.getOperand(1).getReg();
4431 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4432 MI.RemoveOperand(i - 1);
4434 // Change to a %DDst = VORRd %DSrc, %DSrc, 14, %noreg (; implicits)
4435 MI.setDesc(get(ARM::VORRd));
4436 MIB.addReg(DstReg, RegState::Define)
4439 .add(predOps(ARMCC::AL));
4442 if (Domain != ExeNEON)
4444 assert(!isPredicated(MI) && "Cannot predicate a VGETLN");
4446 // Source instruction is %RDst = VMOVRS %SSrc, 14, %noreg (; implicits)
4447 DstReg = MI.getOperand(0).getReg();
4448 SrcReg = MI.getOperand(1).getReg();
4450 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4451 MI.RemoveOperand(i - 1);
4453 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane);
4455 // Convert to %RDst = VGETLNi32 %DSrc, Lane, 14, %noreg (; imps)
4456 // Note that DSrc has been widened and the other lane may be undef, which
4457 // contaminates the entire register.
4458 MI.setDesc(get(ARM::VGETLNi32));
4459 MIB.addReg(DstReg, RegState::Define)
4460 .addReg(DReg, RegState::Undef)
4462 .add(predOps(ARMCC::AL));
4464 // The old source should be an implicit use, otherwise we might think it
4465 // was dead before here.
4466 MIB.addReg(SrcReg, RegState::Implicit);
4469 if (Domain != ExeNEON)
4471 assert(!isPredicated(MI) && "Cannot predicate a VSETLN");
4473 // Source instruction is %SDst = VMOVSR %RSrc, 14, %noreg (; implicits)
4474 DstReg = MI.getOperand(0).getReg();
4475 SrcReg = MI.getOperand(1).getReg();
4477 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane);
4479 unsigned ImplicitSReg;
4480 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg))
4483 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4484 MI.RemoveOperand(i - 1);
4486 // Convert to %DDst = VSETLNi32 %DDst, %RSrc, Lane, 14, %noreg (; imps)
4487 // Again DDst may be undefined at the beginning of this instruction.
4488 MI.setDesc(get(ARM::VSETLNi32));
4489 MIB.addReg(DReg, RegState::Define)
4490 .addReg(DReg, getUndefRegState(!MI.readsRegister(DReg, TRI)))
4493 .add(predOps(ARMCC::AL));
4495 // The narrower destination must be marked as set to keep previous chains
4497 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4498 if (ImplicitSReg != 0)
4499 MIB.addReg(ImplicitSReg, RegState::Implicit);
4503 if (Domain != ExeNEON)
4506 // Source instruction is %SDst = VMOVS %SSrc, 14, %noreg (; implicits)
4507 DstReg = MI.getOperand(0).getReg();
4508 SrcReg = MI.getOperand(1).getReg();
4510 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc;
4511 DDst = getCorrespondingDRegAndLane(TRI, DstReg, DstLane);
4512 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane);
4514 unsigned ImplicitSReg;
4515 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg))
4518 for (unsigned i = MI.getDesc().getNumOperands(); i; --i)
4519 MI.RemoveOperand(i - 1);
4522 // Destination can be:
4523 // %DDst = VDUPLN32d %DDst, Lane, 14, %noreg (; implicits)
4524 MI.setDesc(get(ARM::VDUPLN32d));
4525 MIB.addReg(DDst, RegState::Define)
4526 .addReg(DDst, getUndefRegState(!MI.readsRegister(DDst, TRI)))
4528 .add(predOps(ARMCC::AL));
4530 // Neither the source or the destination are naturally represented any
4531 // more, so add them in manually.
4532 MIB.addReg(DstReg, RegState::Implicit | RegState::Define);
4533 MIB.addReg(SrcReg, RegState::Implicit);
4534 if (ImplicitSReg != 0)
4535 MIB.addReg(ImplicitSReg, RegState::Implicit);
4539 // In general there's no single instruction that can perform an S <-> S
4540 // move in NEON space, but a pair of VEXT instructions *can* do the
4541 // job. It turns out that the VEXTs needed will only use DSrc once, with
4542 // the position based purely on the combination of lane-0 and lane-1
4543 // involved. For example
4544 // vmov s0, s2 -> vext.32 d0, d0, d1, #1 vext.32 d0, d0, d0, #1
4545 // vmov s1, s3 -> vext.32 d0, d1, d0, #1 vext.32 d0, d0, d0, #1
4546 // vmov s0, s3 -> vext.32 d0, d0, d0, #1 vext.32 d0, d1, d0, #1
4547 // vmov s1, s2 -> vext.32 d0, d0, d0, #1 vext.32 d0, d0, d1, #1
4549 // Pattern of the MachineInstrs is:
4550 // %DDst = VEXTd32 %DSrc1, %DSrc2, Lane, 14, %noreg (;implicits)
4551 MachineInstrBuilder NewMIB;
4552 NewMIB = BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::VEXTd32),
4555 // On the first instruction, both DSrc and DDst may be <undef> if present.
4556 // Specifically when the original instruction didn't have them as an
4558 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst;
4559 bool CurUndef = !MI.readsRegister(CurReg, TRI);
4560 NewMIB.addReg(CurReg, getUndefRegState(CurUndef));
4562 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst;
4563 CurUndef = !MI.readsRegister(CurReg, TRI);
4564 NewMIB.addReg(CurReg, getUndefRegState(CurUndef))
4566 .add(predOps(ARMCC::AL));
4568 if (SrcLane == DstLane)
4569 NewMIB.addReg(SrcReg, RegState::Implicit);
4571 MI.setDesc(get(ARM::VEXTd32));
4572 MIB.addReg(DDst, RegState::Define);
4574 // On the second instruction, DDst has definitely been defined above, so
4575 // it is not <undef>. DSrc, if present, can be <undef> as above.
4576 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst;
4577 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4578 MIB.addReg(CurReg, getUndefRegState(CurUndef));
4580 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst;
4581 CurUndef = CurReg == DSrc && !MI.readsRegister(CurReg, TRI);
4582 MIB.addReg(CurReg, getUndefRegState(CurUndef))
4584 .add(predOps(ARMCC::AL));
4586 if (SrcLane != DstLane)
4587 MIB.addReg(SrcReg, RegState::Implicit);
4589 // As before, the original destination is no longer represented, add it
4591 MIB.addReg(DstReg, RegState::Define | RegState::Implicit);
4592 if (ImplicitSReg != 0)
4593 MIB.addReg(ImplicitSReg, RegState::Implicit);
4599 //===----------------------------------------------------------------------===//
4600 // Partial register updates
4601 //===----------------------------------------------------------------------===//
4603 // Swift renames NEON registers with 64-bit granularity. That means any
4604 // instruction writing an S-reg implicitly reads the containing D-reg. The
4605 // problem is mostly avoided by translating f32 operations to v2f32 operations
4606 // on D-registers, but f32 loads are still a problem.
4608 // These instructions can load an f32 into a NEON register:
4610 // VLDRS - Only writes S, partial D update.
4611 // VLD1LNd32 - Writes all D-regs, explicit partial D update, 2 uops.
4612 // VLD1DUPd32 - Writes all D-regs, no partial reg update, 2 uops.
4614 // FCONSTD can be used as a dependency-breaking instruction.
4615 unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance(
4616 const MachineInstr &MI, unsigned OpNum,
4617 const TargetRegisterInfo *TRI) const {
4618 auto PartialUpdateClearance = Subtarget.getPartialUpdateClearance();
4619 if (!PartialUpdateClearance)
4622 assert(TRI && "Need TRI instance");
4624 const MachineOperand &MO = MI.getOperand(OpNum);
4627 unsigned Reg = MO.getReg();
4630 switch (MI.getOpcode()) {
4631 // Normal instructions writing only an S-register.
4636 case ARM::VMOVv4i16:
4637 case ARM::VMOVv2i32:
4638 case ARM::VMOVv2f32:
4639 case ARM::VMOVv1i64:
4640 UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI);
4643 // Explicitly reads the dependency.
4644 case ARM::VLD1LNd32:
4651 // If this instruction actually reads a value from Reg, there is no unwanted
4653 if (UseOp != -1 && MI.getOperand(UseOp).readsReg())
4656 // We must be able to clobber the whole D-reg.
4657 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
4658 // Virtual register must be a foo:ssub_0<def,undef> operand.
4659 if (!MO.getSubReg() || MI.readsVirtualRegister(Reg))
4661 } else if (ARM::SPRRegClass.contains(Reg)) {
4662 // Physical register: MI must define the full D-reg.
4663 unsigned DReg = TRI->getMatchingSuperReg(Reg, ARM::ssub_0,
4665 if (!DReg || !MI.definesRegister(DReg, TRI))
4669 // MI has an unwanted D-register dependency.
4670 // Avoid defs in the previous N instructrions.
4671 return PartialUpdateClearance;
4674 // Break a partial register dependency after getPartialRegUpdateClearance
4675 // returned non-zero.
4676 void ARMBaseInstrInfo::breakPartialRegDependency(
4677 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
4678 assert(OpNum < MI.getDesc().getNumDefs() && "OpNum is not a def");
4679 assert(TRI && "Need TRI instance");
4681 const MachineOperand &MO = MI.getOperand(OpNum);
4682 unsigned Reg = MO.getReg();
4683 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
4684 "Can't break virtual register dependencies.");
4685 unsigned DReg = Reg;
4687 // If MI defines an S-reg, find the corresponding D super-register.
4688 if (ARM::SPRRegClass.contains(Reg)) {
4689 DReg = ARM::D0 + (Reg - ARM::S0) / 2;
4690 assert(TRI->isSuperRegister(Reg, DReg) && "Register enums broken");
4693 assert(ARM::DPRRegClass.contains(DReg) && "Can only break D-reg deps");
4694 assert(MI.definesRegister(DReg, TRI) && "MI doesn't clobber full D-reg");
4696 // FIXME: In some cases, VLDRS can be changed to a VLD1DUPd32 which defines
4697 // the full D-register by loading the same value to both lanes. The
4698 // instruction is micro-coded with 2 uops, so don't do this until we can
4699 // properly schedule micro-coded instructions. The dispatcher stalls cause
4700 // too big regressions.
4702 // Insert the dependency-breaking FCONSTD before MI.
4703 // 96 is the encoding of 0.5, but the actual value doesn't matter here.
4704 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(ARM::FCONSTD), DReg)
4706 .add(predOps(ARMCC::AL));
4707 MI.addRegisterKilled(DReg, TRI, true);
4710 bool ARMBaseInstrInfo::hasNOP() const {
4711 return Subtarget.getFeatureBits()[ARM::HasV6KOps];
4714 bool ARMBaseInstrInfo::isSwiftFastImmShift(const MachineInstr *MI) const {
4715 if (MI->getNumOperands() < 4)
4717 unsigned ShOpVal = MI->getOperand(3).getImm();
4718 unsigned ShImm = ARM_AM::getSORegOffset(ShOpVal);
4719 // Swift supports faster shifts for: lsl 2, lsl 1, and lsr 1.
4720 if ((ShImm == 1 && ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsr) ||
4721 ((ShImm == 1 || ShImm == 2) &&
4722 ARM_AM::getSORegShOp(ShOpVal) == ARM_AM::lsl))
4728 bool ARMBaseInstrInfo::getRegSequenceLikeInputs(
4729 const MachineInstr &MI, unsigned DefIdx,
4730 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const {
4731 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4732 assert(MI.isRegSequenceLike() && "Invalid kind of instruction");
4734 switch (MI.getOpcode()) {
4736 // dX = VMOVDRR rY, rZ
4738 // dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1
4739 // Populate the InputRegs accordingly.
4741 const MachineOperand *MOReg = &MI.getOperand(1);
4742 InputRegs.push_back(
4743 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_0));
4745 MOReg = &MI.getOperand(2);
4746 InputRegs.push_back(
4747 RegSubRegPairAndIdx(MOReg->getReg(), MOReg->getSubReg(), ARM::ssub_1));
4750 llvm_unreachable("Target dependent opcode missing");
4753 bool ARMBaseInstrInfo::getExtractSubregLikeInputs(
4754 const MachineInstr &MI, unsigned DefIdx,
4755 RegSubRegPairAndIdx &InputReg) const {
4756 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4757 assert(MI.isExtractSubregLike() && "Invalid kind of instruction");
4759 switch (MI.getOpcode()) {
4761 // rX, rY = VMOVRRD dZ
4763 // rX = EXTRACT_SUBREG dZ, ssub_0
4764 // rY = EXTRACT_SUBREG dZ, ssub_1
4765 const MachineOperand &MOReg = MI.getOperand(2);
4766 InputReg.Reg = MOReg.getReg();
4767 InputReg.SubReg = MOReg.getSubReg();
4768 InputReg.SubIdx = DefIdx == 0 ? ARM::ssub_0 : ARM::ssub_1;
4771 llvm_unreachable("Target dependent opcode missing");
4774 bool ARMBaseInstrInfo::getInsertSubregLikeInputs(
4775 const MachineInstr &MI, unsigned DefIdx, RegSubRegPair &BaseReg,
4776 RegSubRegPairAndIdx &InsertedReg) const {
4777 assert(DefIdx < MI.getDesc().getNumDefs() && "Invalid definition index");
4778 assert(MI.isInsertSubregLike() && "Invalid kind of instruction");
4780 switch (MI.getOpcode()) {
4781 case ARM::VSETLNi32:
4782 // dX = VSETLNi32 dY, rZ, imm
4783 const MachineOperand &MOBaseReg = MI.getOperand(1);
4784 const MachineOperand &MOInsertedReg = MI.getOperand(2);
4785 const MachineOperand &MOIndex = MI.getOperand(3);
4786 BaseReg.Reg = MOBaseReg.getReg();
4787 BaseReg.SubReg = MOBaseReg.getSubReg();
4789 InsertedReg.Reg = MOInsertedReg.getReg();
4790 InsertedReg.SubReg = MOInsertedReg.getSubReg();
4791 InsertedReg.SubIdx = MOIndex.getImm() == 0 ? ARM::ssub_0 : ARM::ssub_1;
4794 llvm_unreachable("Target dependent opcode missing");