1 //===-- ARMBaseInstrInfo.h - ARM Base Instruction Information ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Base ARM implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/ADT/DenseMap.h"
19 #include "llvm/ADT/SmallSet.h"
20 #include "llvm/CodeGen/MachineBasicBlock.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineOperand.h"
24 #include "llvm/CodeGen/TargetInstrInfo.h"
28 #define GET_INSTRINFO_HEADER
29 #include "ARMGenInstrInfo.inc"
33 class ARMBaseRegisterInfo;
36 class ARMBaseInstrInfo : public ARMGenInstrInfo {
37 const ARMSubtarget &Subtarget;
40 // Can be only subclassed.
41 explicit ARMBaseInstrInfo(const ARMSubtarget &STI);
43 void expandLoadStackGuardBase(MachineBasicBlock::iterator MI,
44 unsigned LoadImmOpc, unsigned LoadOpc) const;
46 /// Build the equivalent inputs of a REG_SEQUENCE for the given \p MI
48 /// \p [out] InputRegs of the equivalent REG_SEQUENCE. Each element of
49 /// the list is modeled as <Reg:SubReg, SubIdx>.
50 /// E.g., REG_SEQUENCE %1:sub1, sub0, %2, sub1 would produce
55 /// \returns true if it is possible to build such an input sequence
56 /// with the pair \p MI, \p DefIdx. False otherwise.
58 /// \pre MI.isRegSequenceLike().
59 bool getRegSequenceLikeInputs(
60 const MachineInstr &MI, unsigned DefIdx,
61 SmallVectorImpl<RegSubRegPairAndIdx> &InputRegs) const override;
63 /// Build the equivalent inputs of a EXTRACT_SUBREG for the given \p MI
65 /// \p [out] InputReg of the equivalent EXTRACT_SUBREG.
66 /// E.g., EXTRACT_SUBREG %1:sub1, sub0, sub1 would produce:
69 /// \returns true if it is possible to build such an input sequence
70 /// with the pair \p MI, \p DefIdx. False otherwise.
72 /// \pre MI.isExtractSubregLike().
73 bool getExtractSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
74 RegSubRegPairAndIdx &InputReg) const override;
76 /// Build the equivalent inputs of a INSERT_SUBREG for the given \p MI
78 /// \p [out] BaseReg and \p [out] InsertedReg contain
79 /// the equivalent inputs of INSERT_SUBREG.
80 /// E.g., INSERT_SUBREG %0:sub0, %1:sub1, sub3 would produce:
81 /// - BaseReg: %0:sub0
82 /// - InsertedReg: %1:sub1, sub3
84 /// \returns true if it is possible to build such an input sequence
85 /// with the pair \p MI, \p DefIdx. False otherwise.
87 /// \pre MI.isInsertSubregLike().
89 getInsertSubregLikeInputs(const MachineInstr &MI, unsigned DefIdx,
90 RegSubRegPair &BaseReg,
91 RegSubRegPairAndIdx &InsertedReg) const override;
93 /// Commutes the operands in the given instruction.
94 /// The commutable operands are specified by their indices OpIdx1 and OpIdx2.
96 /// Do not call this method for a non-commutable instruction or for
97 /// non-commutable pair of operand indices OpIdx1 and OpIdx2.
98 /// Even though the instruction is commutable, the method may still
99 /// fail to commute the operands, null pointer is returned in such cases.
100 MachineInstr *commuteInstructionImpl(MachineInstr &MI, bool NewMI,
102 unsigned OpIdx2) const override;
105 // Return whether the target has an explicit NOP encoding.
108 // Return the non-pre/post incrementing version of 'Opc'. Return 0
109 // if there is not such an opcode.
110 virtual unsigned getUnindexedOpcode(unsigned Opc) const = 0;
112 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
114 LiveVariables *LV) const override;
116 virtual const ARMBaseRegisterInfo &getRegisterInfo() const = 0;
117 const ARMSubtarget &getSubtarget() const { return Subtarget; }
119 ScheduleHazardRecognizer *
120 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
121 const ScheduleDAG *DAG) const override;
123 ScheduleHazardRecognizer *
124 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
125 const ScheduleDAG *DAG) const override;
128 bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
129 MachineBasicBlock *&FBB,
130 SmallVectorImpl<MachineOperand> &Cond,
131 bool AllowModify = false) const override;
132 unsigned removeBranch(MachineBasicBlock &MBB,
133 int *BytesRemoved = nullptr) const override;
134 unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
135 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
137 int *BytesAdded = nullptr) const override;
140 reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
142 // Predication support.
143 bool isPredicated(const MachineInstr &MI) const override;
145 ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
146 int PIdx = MI.findFirstPredOperandIdx();
147 return PIdx != -1 ? (ARMCC::CondCodes)MI.getOperand(PIdx).getImm()
151 bool PredicateInstruction(MachineInstr &MI,
152 ArrayRef<MachineOperand> Pred) const override;
154 bool SubsumesPredicate(ArrayRef<MachineOperand> Pred1,
155 ArrayRef<MachineOperand> Pred2) const override;
157 bool DefinesPredicate(MachineInstr &MI,
158 std::vector<MachineOperand> &Pred) const override;
160 bool isPredicable(const MachineInstr &MI) const override;
162 // CPSR defined in instruction
163 static bool isCPSRDefined(const MachineInstr &MI);
164 bool isAddrMode3OpImm(const MachineInstr &MI, unsigned Op) const;
165 bool isAddrMode3OpMinusReg(const MachineInstr &MI, unsigned Op) const;
167 // Load, scaled register offset
168 bool isLdstScaledReg(const MachineInstr &MI, unsigned Op) const;
169 // Load, scaled register offset, not plus LSL2
170 bool isLdstScaledRegNotPlusLsl2(const MachineInstr &MI, unsigned Op) const;
171 // Minus reg for ldstso addr mode
172 bool isLdstSoMinusReg(const MachineInstr &MI, unsigned Op) const;
173 // Scaled register offset in address mode 2
174 bool isAm2ScaledReg(const MachineInstr &MI, unsigned Op) const;
175 // Load multiple, base reg in list
176 bool isLDMBaseRegInList(const MachineInstr &MI) const;
177 // get LDM variable defs size
178 unsigned getLDMVariableDefsSize(const MachineInstr &MI) const;
180 /// GetInstSize - Returns the size of the specified MachineInstr.
182 unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
184 unsigned isLoadFromStackSlot(const MachineInstr &MI,
185 int &FrameIndex) const override;
186 unsigned isStoreToStackSlot(const MachineInstr &MI,
187 int &FrameIndex) const override;
188 unsigned isLoadFromStackSlotPostFE(const MachineInstr &MI,
189 int &FrameIndex) const override;
190 unsigned isStoreToStackSlotPostFE(const MachineInstr &MI,
191 int &FrameIndex) const override;
193 void copyToCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
194 unsigned SrcReg, bool KillSrc,
195 const ARMSubtarget &Subtarget) const;
196 void copyFromCPSR(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
197 unsigned DestReg, bool KillSrc,
198 const ARMSubtarget &Subtarget) const;
200 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
201 const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
202 bool KillSrc) const override;
204 void storeRegToStackSlot(MachineBasicBlock &MBB,
205 MachineBasicBlock::iterator MBBI,
206 unsigned SrcReg, bool isKill, int FrameIndex,
207 const TargetRegisterClass *RC,
208 const TargetRegisterInfo *TRI) const override;
210 void loadRegFromStackSlot(MachineBasicBlock &MBB,
211 MachineBasicBlock::iterator MBBI,
212 unsigned DestReg, int FrameIndex,
213 const TargetRegisterClass *RC,
214 const TargetRegisterInfo *TRI) const override;
216 bool expandPostRAPseudo(MachineInstr &MI) const override;
218 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
219 unsigned DestReg, unsigned SubIdx,
220 const MachineInstr &Orig,
221 const TargetRegisterInfo &TRI) const override;
224 duplicate(MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
225 const MachineInstr &Orig) const override;
227 const MachineInstrBuilder &AddDReg(MachineInstrBuilder &MIB, unsigned Reg,
228 unsigned SubIdx, unsigned State,
229 const TargetRegisterInfo *TRI) const;
231 bool produceSameValue(const MachineInstr &MI0, const MachineInstr &MI1,
232 const MachineRegisterInfo *MRI) const override;
234 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler to
235 /// determine if two loads are loading from the same base address. It should
236 /// only return true if the base pointers are the same and the only
237 /// differences between the two addresses is the offset. It also returns the
238 /// offsets by reference.
239 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
240 int64_t &Offset2) const override;
242 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
243 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads
244 /// should be scheduled togther. On some targets if two loads are loading from
245 /// addresses in the same cache line, it's better if they are scheduled
246 /// together. This function takes two integers that represent the load offsets
247 /// from the common base address. It returns true if it decides it's desirable
248 /// to schedule the two loads together. "NumLoads" is the number of loads that
249 /// have already been scheduled after Load1.
250 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
251 int64_t Offset1, int64_t Offset2,
252 unsigned NumLoads) const override;
254 bool isSchedulingBoundary(const MachineInstr &MI,
255 const MachineBasicBlock *MBB,
256 const MachineFunction &MF) const override;
258 bool isProfitableToIfCvt(MachineBasicBlock &MBB,
259 unsigned NumCycles, unsigned ExtraPredCycles,
260 BranchProbability Probability) const override;
262 bool isProfitableToIfCvt(MachineBasicBlock &TMBB, unsigned NumT,
263 unsigned ExtraT, MachineBasicBlock &FMBB,
264 unsigned NumF, unsigned ExtraF,
265 BranchProbability Probability) const override;
267 bool isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
268 BranchProbability Probability) const override {
269 return NumCycles == 1;
272 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
273 MachineBasicBlock &FMBB) const override;
275 /// analyzeCompare - For a comparison instruction, return the source registers
276 /// in SrcReg and SrcReg2 if having two register operands, and the value it
277 /// compares against in CmpValue. Return true if the comparison instruction
279 bool analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
280 unsigned &SrcReg2, int &CmpMask,
281 int &CmpValue) const override;
283 /// optimizeCompareInstr - Convert the instruction to set the zero flag so
284 /// that we can remove a "comparison with zero"; Remove a redundant CMP
285 /// instruction if the flags can be updated in the same way by an earlier
286 /// instruction such as SUB.
287 bool optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
288 unsigned SrcReg2, int CmpMask, int CmpValue,
289 const MachineRegisterInfo *MRI) const override;
291 bool analyzeSelect(const MachineInstr &MI,
292 SmallVectorImpl<MachineOperand> &Cond, unsigned &TrueOp,
293 unsigned &FalseOp, bool &Optimizable) const override;
295 MachineInstr *optimizeSelect(MachineInstr &MI,
296 SmallPtrSetImpl<MachineInstr *> &SeenMIs,
297 bool) const override;
299 /// FoldImmediate - 'Reg' is known to be defined by a move immediate
300 /// instruction, try to fold the immediate into the use instruction.
301 bool FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, unsigned Reg,
302 MachineRegisterInfo *MRI) const override;
304 unsigned getNumMicroOps(const InstrItineraryData *ItinData,
305 const MachineInstr &MI) const override;
307 int getOperandLatency(const InstrItineraryData *ItinData,
308 const MachineInstr &DefMI, unsigned DefIdx,
309 const MachineInstr &UseMI,
310 unsigned UseIdx) const override;
311 int getOperandLatency(const InstrItineraryData *ItinData,
312 SDNode *DefNode, unsigned DefIdx,
313 SDNode *UseNode, unsigned UseIdx) const override;
315 /// VFP/NEON execution domains.
316 std::pair<uint16_t, uint16_t>
317 getExecutionDomain(const MachineInstr &MI) const override;
318 void setExecutionDomain(MachineInstr &MI, unsigned Domain) const override;
321 getPartialRegUpdateClearance(const MachineInstr &, unsigned,
322 const TargetRegisterInfo *) const override;
323 void breakPartialRegDependency(MachineInstr &, unsigned,
324 const TargetRegisterInfo *TRI) const override;
326 /// Get the number of addresses by LDM or VLDM or zero for unknown.
327 unsigned getNumLDMAddresses(const MachineInstr &MI) const;
330 unsigned getInstBundleLength(const MachineInstr &MI) const;
332 int getVLDMDefCycle(const InstrItineraryData *ItinData,
333 const MCInstrDesc &DefMCID,
335 unsigned DefIdx, unsigned DefAlign) const;
336 int getLDMDefCycle(const InstrItineraryData *ItinData,
337 const MCInstrDesc &DefMCID,
339 unsigned DefIdx, unsigned DefAlign) const;
340 int getVSTMUseCycle(const InstrItineraryData *ItinData,
341 const MCInstrDesc &UseMCID,
343 unsigned UseIdx, unsigned UseAlign) const;
344 int getSTMUseCycle(const InstrItineraryData *ItinData,
345 const MCInstrDesc &UseMCID,
347 unsigned UseIdx, unsigned UseAlign) const;
348 int getOperandLatency(const InstrItineraryData *ItinData,
349 const MCInstrDesc &DefMCID,
350 unsigned DefIdx, unsigned DefAlign,
351 const MCInstrDesc &UseMCID,
352 unsigned UseIdx, unsigned UseAlign) const;
354 int getOperandLatencyImpl(const InstrItineraryData *ItinData,
355 const MachineInstr &DefMI, unsigned DefIdx,
356 const MCInstrDesc &DefMCID, unsigned DefAdj,
357 const MachineOperand &DefMO, unsigned Reg,
358 const MachineInstr &UseMI, unsigned UseIdx,
359 const MCInstrDesc &UseMCID, unsigned UseAdj) const;
361 unsigned getPredicationCost(const MachineInstr &MI) const override;
363 unsigned getInstrLatency(const InstrItineraryData *ItinData,
364 const MachineInstr &MI,
365 unsigned *PredCost = nullptr) const override;
367 int getInstrLatency(const InstrItineraryData *ItinData,
368 SDNode *Node) const override;
370 bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
371 const MachineRegisterInfo *MRI,
372 const MachineInstr &DefMI, unsigned DefIdx,
373 const MachineInstr &UseMI,
374 unsigned UseIdx) const override;
375 bool hasLowDefLatency(const TargetSchedModel &SchedModel,
376 const MachineInstr &DefMI,
377 unsigned DefIdx) const override;
379 /// verifyInstruction - Perform target specific instruction verification.
380 bool verifyInstruction(const MachineInstr &MI,
381 StringRef &ErrInfo) const override;
383 virtual void expandLoadStackGuard(MachineBasicBlock::iterator MI) const = 0;
385 void expandMEMCPY(MachineBasicBlock::iterator) const;
388 /// Modeling special VFP / NEON fp MLA / MLS hazards.
390 /// MLxEntryMap - Map fp MLA / MLS to the corresponding entry in the internal
392 DenseMap<unsigned, unsigned> MLxEntryMap;
394 /// MLxHazardOpcodes - Set of add / sub and multiply opcodes that would cause
395 /// stalls when scheduled together with fp MLA / MLS opcodes.
396 SmallSet<unsigned, 16> MLxHazardOpcodes;
399 /// isFpMLxInstruction - Return true if the specified opcode is a fp MLA / MLS
401 bool isFpMLxInstruction(unsigned Opcode) const {
402 return MLxEntryMap.count(Opcode);
405 /// isFpMLxInstruction - This version also returns the multiply opcode and the
406 /// addition / subtraction opcode to expand to. Return true for 'HasLane' for
407 /// the MLX instructions with an extra lane operand.
408 bool isFpMLxInstruction(unsigned Opcode, unsigned &MulOpc,
409 unsigned &AddSubOpc, bool &NegAcc,
410 bool &HasLane) const;
412 /// canCauseFpMLxStall - Return true if an instruction of the specified opcode
413 /// will cause stalls when scheduled after (within 4-cycle window) a fp
414 /// MLA / MLS instruction.
415 bool canCauseFpMLxStall(unsigned Opcode) const {
416 return MLxHazardOpcodes.count(Opcode);
419 /// Returns true if the instruction has a shift by immediate that can be
420 /// executed in one cycle less.
421 bool isSwiftFastImmShift(const MachineInstr *MI) const;
423 /// Returns predicate register associated with the given frame instruction.
424 unsigned getFramePred(const MachineInstr &MI) const {
425 assert(isFrameInstr(MI));
426 // Operands of ADJCALLSTACKDOWN/ADJCALLSTACKUP:
427 // - argument declared in the pattern:
429 // 1 - arg of CALLSEQ_START/CALLSEQ_END
430 // 2 - predicate code (like ARMCC::AL)
431 // - added by predOps:
433 return MI.getOperand(3).getReg();
437 /// Get the operands corresponding to the given \p Pred value. By default, the
438 /// predicate register is assumed to be 0 (no register), but you can pass in a
439 /// \p PredReg if that is not the case.
440 static inline std::array<MachineOperand, 2> predOps(ARMCC::CondCodes Pred,
441 unsigned PredReg = 0) {
442 return {{MachineOperand::CreateImm(static_cast<int64_t>(Pred)),
443 MachineOperand::CreateReg(PredReg, false)}};
446 /// Get the operand corresponding to the conditional code result. By default,
447 /// this is 0 (no register).
448 static inline MachineOperand condCodeOp(unsigned CCReg = 0) {
449 return MachineOperand::CreateReg(CCReg, false);
452 /// Get the operand corresponding to the conditional code result for Thumb1.
453 /// This operand will always refer to CPSR and it will have the Define flag set.
454 /// You can optionally set the Dead flag by means of \p isDead.
455 static inline MachineOperand t1CondCodeOp(bool isDead = false) {
456 return MachineOperand::CreateReg(ARM::CPSR,
457 /*Define*/ true, /*Implicit*/ false,
458 /*Kill*/ false, isDead);
462 bool isUncondBranchOpcode(int Opc) {
463 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B;
467 bool isCondBranchOpcode(int Opc) {
468 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc;
471 static inline bool isJumpTableBranchOpcode(int Opc) {
472 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm_i12 ||
473 Opc == ARM::BR_JTm_rs || Opc == ARM::BR_JTadd || Opc == ARM::tBR_JTr ||
478 bool isIndirectBranchOpcode(int Opc) {
479 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND;
482 static inline bool isPopOpcode(int Opc) {
483 return Opc == ARM::tPOP_RET || Opc == ARM::LDMIA_RET ||
484 Opc == ARM::t2LDMIA_RET || Opc == ARM::tPOP || Opc == ARM::LDMIA_UPD ||
485 Opc == ARM::t2LDMIA_UPD || Opc == ARM::VLDMDIA_UPD;
488 static inline bool isPushOpcode(int Opc) {
489 return Opc == ARM::tPUSH || Opc == ARM::t2STMDB_UPD ||
490 Opc == ARM::STMDB_UPD || Opc == ARM::VSTMDDB_UPD;
493 /// getInstrPredicate - If instruction is predicated, returns its predicate
494 /// condition, otherwise returns AL. It also returns the condition code
495 /// register by reference.
496 ARMCC::CondCodes getInstrPredicate(const MachineInstr &MI, unsigned &PredReg);
498 unsigned getMatchingCondBranchOpcode(unsigned Opc);
500 /// Determine if MI can be folded into an ARM MOVCC instruction, and return the
501 /// opcode of the SSA instruction representing the conditional MI.
502 unsigned canFoldARMInstrIntoMOVCC(unsigned Reg,
504 const MachineRegisterInfo &MRI);
506 /// Map pseudo instructions that imply an 'S' bit onto real opcodes. Whether
507 /// the instruction is encoded with an 'S' bit is determined by the optional
508 /// CPSR def operand.
509 unsigned convertAddSubFlagsOpcode(unsigned OldOpc);
511 /// emitARMRegPlusImmediate / emitT2RegPlusImmediate - Emits a series of
512 /// instructions to materializea destreg = basereg + immediate in ARM / Thumb2
514 void emitARMRegPlusImmediate(MachineBasicBlock &MBB,
515 MachineBasicBlock::iterator &MBBI,
516 const DebugLoc &dl, unsigned DestReg,
517 unsigned BaseReg, int NumBytes,
518 ARMCC::CondCodes Pred, unsigned PredReg,
519 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
521 void emitT2RegPlusImmediate(MachineBasicBlock &MBB,
522 MachineBasicBlock::iterator &MBBI,
523 const DebugLoc &dl, unsigned DestReg,
524 unsigned BaseReg, int NumBytes,
525 ARMCC::CondCodes Pred, unsigned PredReg,
526 const ARMBaseInstrInfo &TII, unsigned MIFlags = 0);
527 void emitThumbRegPlusImmediate(MachineBasicBlock &MBB,
528 MachineBasicBlock::iterator &MBBI,
529 const DebugLoc &dl, unsigned DestReg,
530 unsigned BaseReg, int NumBytes,
531 const TargetInstrInfo &TII,
532 const ARMBaseRegisterInfo &MRI,
533 unsigned MIFlags = 0);
535 /// Tries to add registers to the reglist of a given base-updating
536 /// push/pop instruction to adjust the stack by an additional
537 /// NumBytes. This can save a few bytes per function in code-size, but
538 /// obviously generates more memory traffic. As such, it only takes
539 /// effect in functions being optimised for size.
540 bool tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
541 MachineFunction &MF, MachineInstr *MI,
544 /// rewriteARMFrameIndex / rewriteT2FrameIndex -
545 /// Rewrite MI to access 'Offset' bytes from the FP. Return false if the
546 /// offset could not be handled directly in MI, and return the left-over
547 /// portion by reference.
548 bool rewriteARMFrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
549 unsigned FrameReg, int &Offset,
550 const ARMBaseInstrInfo &TII);
552 bool rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx,
553 unsigned FrameReg, int &Offset,
554 const ARMBaseInstrInfo &TII);
556 } // end namespace llvm
558 #endif // LLVM_LIB_TARGET_ARM_ARMBASEINSTRINFO_H