1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "ARMBaseInstrInfo.h"
16 #include "ARMBaseRegisterInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "MCTargetDesc/ARMBaseInfo.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/SmallVector.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/CodeGen/MachineBasicBlock.h"
26 #include "llvm/CodeGen/MachineConstantPool.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstr.h"
30 #include "llvm/CodeGen/MachineInstrBuilder.h"
31 #include "llvm/CodeGen/MachineOperand.h"
32 #include "llvm/CodeGen/MachineRegisterInfo.h"
33 #include "llvm/CodeGen/RegisterScavenging.h"
34 #include "llvm/CodeGen/VirtRegMap.h"
35 #include "llvm/IR/Attributes.h"
36 #include "llvm/IR/Constants.h"
37 #include "llvm/IR/DebugLoc.h"
38 #include "llvm/IR/Function.h"
39 #include "llvm/IR/Type.h"
40 #include "llvm/MC/MCInstrDesc.h"
41 #include "llvm/Support/Debug.h"
42 #include "llvm/Support/ErrorHandling.h"
43 #include "llvm/Support/raw_ostream.h"
44 #include "llvm/Target/TargetInstrInfo.h"
45 #include "llvm/Target/TargetMachine.h"
46 #include "llvm/Target/TargetOptions.h"
47 #include "llvm/Target/TargetRegisterInfo.h"
51 #define DEBUG_TYPE "arm-register-info"
53 #define GET_REGINFO_TARGET_DESC
54 #include "ARMGenRegisterInfo.inc"
58 ARMBaseRegisterInfo::ARMBaseRegisterInfo()
59 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC) {}
61 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
62 return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
66 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
67 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
68 bool UseSplitPush = STI.splitFramePushPop(*MF);
69 const MCPhysReg *RegList =
72 : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
74 const Function *F = MF->getFunction();
75 if (F->getCallingConv() == CallingConv::GHC) {
76 // GHC set of callee saved regs is empty as all those regs are
77 // used for passing STG regs around
78 return CSR_NoRegs_SaveList;
79 } else if (F->hasFnAttribute("interrupt")) {
81 // M-class CPUs have hardware which saves the registers needed to allow a
82 // function conforming to the AAPCS to function as a handler.
83 return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
84 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
85 // Fast interrupt mode gives the handler a private copy of R8-R14, so less
86 // need to be saved to restore user-mode state.
87 return CSR_FIQ_SaveList;
89 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
90 // exception handling.
91 return CSR_GenericInt_SaveList;
95 if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
96 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
97 return CSR_iOS_SwiftError_SaveList;
99 if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS)
100 return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
101 ? CSR_iOS_CXX_TLS_PE_SaveList
102 : CSR_iOS_CXX_TLS_SaveList;
106 const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
107 const MachineFunction *MF) const {
108 assert(MF && "Invalid MachineFunction pointer.");
109 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
110 MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
111 return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
116 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
117 CallingConv::ID CC) const {
118 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
119 if (CC == CallingConv::GHC)
120 // This is academic becase all GHC calls are (supposed to be) tail calls
121 return CSR_NoRegs_RegMask;
123 if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
124 MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
125 return CSR_iOS_SwiftError_RegMask;
127 if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
128 return CSR_iOS_CXX_TLS_RegMask;
129 return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
133 ARMBaseRegisterInfo::getNoPreservedMask() const {
134 return CSR_NoRegs_RegMask;
138 ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {
139 assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
140 "only know about special TLS call on Darwin");
141 return CSR_iOS_TLSCall_RegMask;
145 ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {
146 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
147 if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
148 return CSR_NoRegs_RegMask;
150 return CSR_FPRegs_RegMask;
154 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
155 CallingConv::ID CC) const {
156 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
157 // This should return a register mask that is the same as that returned by
158 // getCallPreservedMask but that additionally preserves the register used for
159 // the first i32 argument (which must also be the register used to return a
160 // single i32 return value)
162 // In case that the calling convention does not use the same register for
163 // both or otherwise does not want to enable this optimization, the function
164 // should return NULL
165 if (CC == CallingConv::GHC)
166 // This is academic becase all GHC calls are (supposed to be) tail calls
168 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
169 : CSR_AAPCS_ThisReturn_RegMask;
172 BitVector ARMBaseRegisterInfo::
173 getReservedRegs(const MachineFunction &MF) const {
174 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
175 const ARMFrameLowering *TFI = getFrameLowering(MF);
177 // FIXME: avoid re-calculating this every time.
178 BitVector Reserved(getNumRegs());
179 markSuperRegs(Reserved, ARM::SP);
180 markSuperRegs(Reserved, ARM::PC);
181 markSuperRegs(Reserved, ARM::FPSCR);
182 markSuperRegs(Reserved, ARM::APSR_NZCV);
184 markSuperRegs(Reserved, getFramePointerReg(STI));
185 if (hasBasePointer(MF))
186 markSuperRegs(Reserved, BasePtr);
187 // Some targets reserve R9.
188 if (STI.isR9Reserved())
189 markSuperRegs(Reserved, ARM::R9);
190 // Reserve D16-D31 if the subtarget doesn't support them.
191 if (!STI.hasVFP3() || STI.hasD16()) {
192 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
193 for (unsigned R = 0; R < 16; ++R)
194 markSuperRegs(Reserved, ARM::D16 + R);
196 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
197 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
198 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
199 if (Reserved.test(*SI)) markSuperRegs(Reserved, *I);
201 assert(checkAllSuperRegsMarked(Reserved));
205 const TargetRegisterClass *
206 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
207 const MachineFunction &) const {
208 const TargetRegisterClass *Super = RC;
209 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
211 switch (Super->getID()) {
212 case ARM::GPRRegClassID:
213 case ARM::SPRRegClassID:
214 case ARM::DPRRegClassID:
215 case ARM::QPRRegClassID:
216 case ARM::QQPRRegClassID:
217 case ARM::QQQQPRRegClassID:
218 case ARM::GPRPairRegClassID:
226 const TargetRegisterClass *
227 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
229 return &ARM::GPRRegClass;
232 const TargetRegisterClass *
233 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
234 if (RC == &ARM::CCRRegClass)
235 return &ARM::rGPRRegClass; // Can't copy CCR registers.
240 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
241 MachineFunction &MF) const {
242 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
243 const ARMFrameLowering *TFI = getFrameLowering(MF);
245 switch (RC->getID()) {
248 case ARM::tGPRRegClassID: {
249 // hasFP ends up calling getMaxCallFrameComputed() which may not be
250 // available when getPressureLimit() is called as part of
251 // ScheduleDAGRRList.
252 bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
253 ? TFI->hasFP(MF) : true;
256 case ARM::GPRRegClassID: {
257 bool HasFP = MF.getFrameInfo().isMaxCallFrameSizeComputed()
258 ? TFI->hasFP(MF) : true;
259 return 10 - HasFP - (STI.isR9Reserved() ? 1 : 0);
261 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
262 case ARM::DPRRegClassID:
267 // Get the other register in a GPRPair.
268 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
269 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
270 if (ARM::GPRPairRegClass.contains(*Supers))
271 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
275 // Resolve the RegPairEven / RegPairOdd register allocator hints.
277 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
278 ArrayRef<MCPhysReg> Order,
279 SmallVectorImpl<MCPhysReg> &Hints,
280 const MachineFunction &MF,
281 const VirtRegMap *VRM,
282 const LiveRegMatrix *Matrix) const {
283 const MachineRegisterInfo &MRI = MF.getRegInfo();
284 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
287 switch (Hint.first) {
288 case ARMRI::RegPairEven:
291 case ARMRI::RegPairOdd:
295 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
299 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
300 // Check if the other part of the pair has already been assigned, and provide
301 // the paired register as the first hint.
302 unsigned Paired = Hint.second;
306 unsigned PairedPhys = 0;
307 if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
309 } else if (VRM && VRM->hasPhys(Paired)) {
310 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
313 // First prefer the paired physreg.
314 if (PairedPhys && is_contained(Order, PairedPhys))
315 Hints.push_back(PairedPhys);
317 // Then prefer even or odd registers.
318 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
319 unsigned Reg = Order[I];
320 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
322 // Don't provide hints that are paired to a reserved register.
323 unsigned Paired = getPairedGPR(Reg, !Odd, this);
324 if (!Paired || MRI.isReserved(Paired))
326 Hints.push_back(Reg);
331 ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
332 MachineFunction &MF) const {
333 MachineRegisterInfo *MRI = &MF.getRegInfo();
334 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
335 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
336 Hint.first == (unsigned)ARMRI::RegPairEven) &&
337 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
338 // If 'Reg' is one of the even / odd register pair and it's now changed
339 // (e.g. coalesced) into a different register. The other register of the
340 // pair allocation hint must be updated to reflect the relationship
342 unsigned OtherReg = Hint.second;
343 Hint = MRI->getRegAllocationHint(OtherReg);
344 // Make sure the pair has not already divorced.
345 if (Hint.second == Reg) {
346 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
347 if (TargetRegisterInfo::isVirtualRegister(NewReg))
348 MRI->setRegAllocationHint(NewReg,
349 Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
350 : ARMRI::RegPairOdd, OtherReg);
355 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
356 const MachineFrameInfo &MFI = MF.getFrameInfo();
357 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
358 const ARMFrameLowering *TFI = getFrameLowering(MF);
360 // When outgoing call frames are so large that we adjust the stack pointer
361 // around the call, we can no longer use the stack pointer to reach the
362 // emergency spill slot.
363 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
366 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
367 // negative range for ldr/str (255), and thumb1 is positive offsets only.
368 // It's going to be better to use the SP or Base Pointer instead. When there
369 // are variable sized objects, we can't reference off of the SP, so we
370 // reserve a Base Pointer.
371 if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
372 // Conservatively estimate whether the negative offset from the frame
373 // pointer will be sufficient to reach. If a function has a smallish
374 // frame, it's less likely to have lots of spills and callee saved
375 // space, so it's all more likely to be within range of the frame pointer.
376 // If it's wrong, the scavenger will still enable access to work, it just
378 if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
386 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
387 const MachineRegisterInfo *MRI = &MF.getRegInfo();
388 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
389 const ARMFrameLowering *TFI = getFrameLowering(MF);
390 // We can't realign the stack if:
391 // 1. Dynamic stack realignment is explicitly disabled,
392 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
393 // 3. There are VLAs in the function and the base pointer is disabled.
394 if (!TargetRegisterInfo::canRealignStack(MF))
396 if (AFI->isThumb1OnlyFunction())
398 // Stack realignment requires a frame pointer. If we already started
399 // register allocation with frame pointer elimination, it is too late now.
400 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
402 // We may also need a base pointer if there are dynamic allocas or stack
403 // pointer adjustments around calls.
404 if (TFI->hasReservedCallFrame(MF))
406 // A base pointer is required and allowed. Check that it isn't too late to
408 return MRI->canReserveReg(BasePtr);
411 bool ARMBaseRegisterInfo::
412 cannotEliminateFrame(const MachineFunction &MF) const {
413 const MachineFrameInfo &MFI = MF.getFrameInfo();
414 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
416 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
417 || needsStackRealignment(MF);
421 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
422 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
423 const ARMFrameLowering *TFI = getFrameLowering(MF);
426 return getFramePointerReg(STI);
430 /// emitLoadConstPool - Emits a load from constpool to materialize the
431 /// specified immediate.
432 void ARMBaseRegisterInfo::emitLoadConstPool(
433 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
434 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
435 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
436 MachineFunction &MF = *MBB.getParent();
437 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
438 MachineConstantPool *ConstantPool = MF.getConstantPool();
440 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
441 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
443 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
444 .addReg(DestReg, getDefRegState(true), SubIdx)
445 .addConstantPoolIndex(Idx)
447 .add(predOps(Pred, PredReg))
448 .setMIFlags(MIFlags);
451 bool ARMBaseRegisterInfo::
452 requiresRegisterScavenging(const MachineFunction &MF) const {
456 bool ARMBaseRegisterInfo::
457 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
461 bool ARMBaseRegisterInfo::
462 requiresFrameIndexScavenging(const MachineFunction &MF) const {
466 bool ARMBaseRegisterInfo::
467 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
471 int64_t ARMBaseRegisterInfo::
472 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
473 const MCInstrDesc &Desc = MI->getDesc();
474 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
475 int64_t InstrOffs = 0;
479 case ARMII::AddrModeT2_i8:
480 case ARMII::AddrModeT2_i12:
481 case ARMII::AddrMode_i12:
482 InstrOffs = MI->getOperand(Idx+1).getImm();
485 case ARMII::AddrMode5: {
487 const MachineOperand &OffOp = MI->getOperand(Idx+1);
488 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
489 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
490 InstrOffs = -InstrOffs;
494 case ARMII::AddrMode2:
496 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
497 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
498 InstrOffs = -InstrOffs;
500 case ARMII::AddrMode3:
502 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
503 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
504 InstrOffs = -InstrOffs;
506 case ARMII::AddrModeT1_s:
508 InstrOffs = MI->getOperand(ImmIdx).getImm();
512 llvm_unreachable("Unsupported addressing mode!");
515 return InstrOffs * Scale;
518 /// needsFrameBaseReg - Returns true if the instruction's frame index
519 /// reference would be better served by a base register other than FP
520 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
521 /// references it should create new base registers for.
522 bool ARMBaseRegisterInfo::
523 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
524 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
525 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
528 // It's the load/store FI references that cause issues, as it can be difficult
529 // to materialize the offset if it won't fit in the literal field. Estimate
530 // based on the size of the local frame and some conservative assumptions
531 // about the rest of the stack frame (note, this is pre-regalloc, so
532 // we don't know everything for certain yet) whether this offset is likely
533 // to be out of range of the immediate. Return true if so.
535 // We only generate virtual base registers for loads and stores, so
536 // return false for everything else.
537 unsigned Opc = MI->getOpcode();
539 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
540 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
541 case ARM::t2LDRi12: case ARM::t2LDRi8:
542 case ARM::t2STRi12: case ARM::t2STRi8:
543 case ARM::VLDRS: case ARM::VLDRD:
544 case ARM::VSTRS: case ARM::VSTRD:
545 case ARM::tSTRspi: case ARM::tLDRspi:
551 // Without a virtual base register, if the function has variable sized
552 // objects, all fixed-size local references will be via the frame pointer,
553 // Approximate the offset and see if it's legal for the instruction.
554 // Note that the incoming offset is based on the SP value at function entry,
555 // so it'll be negative.
556 MachineFunction &MF = *MI->getParent()->getParent();
557 const ARMFrameLowering *TFI = getFrameLowering(MF);
558 MachineFrameInfo &MFI = MF.getFrameInfo();
559 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
561 // Estimate an offset from the frame pointer.
562 // Conservatively assume all callee-saved registers get pushed. R4-R6
563 // will be earlier than the FP, so we ignore those.
565 int64_t FPOffset = Offset - 8;
566 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
567 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
569 // Estimate an offset from the stack pointer.
570 // The incoming offset is relating to the SP at the start of the function,
571 // but when we access the local it'll be relative to the SP after local
572 // allocation, so adjust our SP-relative offset by that allocation size.
573 Offset += MFI.getLocalFrameSize();
574 // Assume that we'll have at least some spill slots allocated.
575 // FIXME: This is a total SWAG number. We should run some statistics
576 // and pick a real one.
577 Offset += 128; // 128 bytes of spill slots
579 // If there's a frame pointer and the addressing mode allows it, try using it.
580 // The FP is only available if there is no dynamic realignment. We
581 // don't know for sure yet whether we'll need that, so we guess based
582 // on whether there are any local variables that would trigger it.
583 unsigned StackAlign = TFI->getStackAlignment();
584 if (TFI->hasFP(MF) &&
585 !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
586 if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
589 // If we can reference via the stack pointer, try that.
590 // FIXME: This (and the code that resolves the references) can be improved
591 // to only disallow SP relative references in the live range of
592 // the VLA(s). In practice, it's unclear how much difference that
593 // would make, but it may be worth doing.
594 if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
597 // The offset likely isn't legal, we want to allocate a virtual base register.
601 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
602 /// be a pointer to FrameIdx at the beginning of the basic block.
603 void ARMBaseRegisterInfo::
604 materializeFrameBaseRegister(MachineBasicBlock *MBB,
605 unsigned BaseReg, int FrameIdx,
606 int64_t Offset) const {
607 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
608 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
609 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
611 MachineBasicBlock::iterator Ins = MBB->begin();
612 DebugLoc DL; // Defaults to "unknown"
613 if (Ins != MBB->end())
614 DL = Ins->getDebugLoc();
616 const MachineFunction &MF = *MBB->getParent();
617 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
618 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
619 const MCInstrDesc &MCID = TII.get(ADDriOpc);
620 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
622 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
623 .addFrameIndex(FrameIdx).addImm(Offset);
625 if (!AFI->isThumb1OnlyFunction())
626 MIB.add(predOps(ARMCC::AL)).add(condCodeOp());
629 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
630 int64_t Offset) const {
631 MachineBasicBlock &MBB = *MI.getParent();
632 MachineFunction &MF = *MBB.getParent();
633 const ARMBaseInstrInfo &TII =
634 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
635 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
636 int Off = Offset; // ARM doesn't need the general 64-bit offsets
639 assert(!AFI->isThumb1OnlyFunction() &&
640 "This resolveFrameIndex does not support Thumb1!");
642 while (!MI.getOperand(i).isFI()) {
644 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
647 if (!AFI->isThumbFunction())
648 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
650 assert(AFI->isThumb2Function());
651 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
653 assert(Done && "Unable to resolve frame index!");
657 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
658 int64_t Offset) const {
659 const MCInstrDesc &Desc = MI->getDesc();
660 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
663 while (!MI->getOperand(i).isFI()) {
665 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
668 // AddrMode4 and AddrMode6 cannot handle any offset.
669 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
672 unsigned NumBits = 0;
674 bool isSigned = true;
676 case ARMII::AddrModeT2_i8:
677 case ARMII::AddrModeT2_i12:
678 // i8 supports only negative, and i12 supports only positive, so
679 // based on Offset sign, consider the appropriate instruction
688 case ARMII::AddrMode5:
693 case ARMII::AddrMode_i12:
694 case ARMII::AddrMode2:
697 case ARMII::AddrMode3:
700 case ARMII::AddrModeT1_s:
701 NumBits = (BaseReg == ARM::SP ? 8 : 5);
706 llvm_unreachable("Unsupported addressing mode!");
709 Offset += getFrameIndexInstrOffset(MI, i);
710 // Make sure the offset is encodable for instructions that scale the
712 if ((Offset & (Scale-1)) != 0)
715 if (isSigned && Offset < 0)
718 unsigned Mask = (1 << NumBits) - 1;
719 if ((unsigned)Offset <= Mask * Scale)
726 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
727 int SPAdj, unsigned FIOperandNum,
728 RegScavenger *RS) const {
729 MachineInstr &MI = *II;
730 MachineBasicBlock &MBB = *MI.getParent();
731 MachineFunction &MF = *MBB.getParent();
732 const ARMBaseInstrInfo &TII =
733 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
734 const ARMFrameLowering *TFI = getFrameLowering(MF);
735 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
736 assert(!AFI->isThumb1OnlyFunction() &&
737 "This eliminateFrameIndex does not support Thumb1!");
738 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
741 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
743 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
744 // call frame setup/destroy instructions have already been eliminated. That
745 // means the stack pointer cannot be used to access the emergency spill slot
746 // when !hasReservedCallFrame().
748 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
749 assert(TFI->hasReservedCallFrame(MF) &&
750 "Cannot use SP to access the emergency spill slot in "
751 "functions without a reserved call frame");
752 assert(!MF.getFrameInfo().hasVarSizedObjects() &&
753 "Cannot use SP to access the emergency spill slot in "
754 "functions with variable sized frame objects");
758 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
760 // Modify MI as necessary to handle as much of 'Offset' as possible
762 if (!AFI->isThumbFunction())
763 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
765 assert(AFI->isThumb2Function());
766 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
771 // If we get here, the immediate doesn't fit into the instruction. We folded
772 // as much as possible above, handle the rest, providing a register that is
775 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
776 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
777 "This code isn't needed if offset already handled!");
779 unsigned ScratchReg = 0;
780 int PIdx = MI.findFirstPredOperandIdx();
781 ARMCC::CondCodes Pred = (PIdx == -1)
782 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
783 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
785 // Must be addrmode4/6.
786 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
788 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
789 if (!AFI->isThumbFunction())
790 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
791 Offset, Pred, PredReg, TII);
793 assert(AFI->isThumb2Function());
794 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
795 Offset, Pred, PredReg, TII);
797 // Update the original instruction to use the scratch register.
798 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
802 bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
803 const TargetRegisterClass *SrcRC,
805 const TargetRegisterClass *DstRC,
807 const TargetRegisterClass *NewRC) const {
808 auto MBB = MI->getParent();
809 auto MF = MBB->getParent();
810 const MachineRegisterInfo &MRI = MF->getRegInfo();
811 // If not copying into a sub-register this should be ok because we shouldn't
812 // need to split the reg.
815 // Small registers don't frequently cause a problem, so we can coalesce them.
816 if (getRegSizeInBits(*NewRC) < 256 && getRegSizeInBits(*DstRC) < 256 &&
817 getRegSizeInBits(*SrcRC) < 256)
821 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
823 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
825 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
826 // If the source register class is more expensive than the destination, the
827 // coalescing is probably profitable.
828 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
830 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
833 // If the register allocator isn't constrained, we can always allow coalescing
834 // unfortunately we don't know yet if we will be constrained.
835 // The goal of this heuristic is to restrict how many expensive registers
836 // we allow to coalesce in a given basic block.
837 auto AFI = MF->getInfo<ARMFunctionInfo>();
838 auto It = AFI->getCoalescedWeight(MBB);
840 DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
841 << It->second << "\n");
842 DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
843 << NewRCWeight.RegWeight << "\n");
845 // This number is the largest round number that which meets the criteria:
846 // (1) addresses PR18825
847 // (2) generates better code in some test cases (like vldm-shed-a9.ll)
848 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
849 // In practice the SizeMultiplier will only factor in for straight line code
850 // that uses a lot of NEON vectors, which isn't terribly common.
851 unsigned SizeMultiplier = MBB->size()/100;
852 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
853 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
854 It->second += NewRCWeight.RegWeight;