1 //===-- ARMBaseRegisterInfo.cpp - ARM Register Information ----------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "ARMBaseRegisterInfo.h"
16 #include "ARMBaseInstrInfo.h"
17 #include "ARMFrameLowering.h"
18 #include "ARMMachineFunctionInfo.h"
19 #include "ARMSubtarget.h"
20 #include "MCTargetDesc/ARMAddressingModes.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/CodeGen/RegisterScavenging.h"
29 #include "llvm/CodeGen/VirtRegMap.h"
30 #include "llvm/IR/Constants.h"
31 #include "llvm/IR/DerivedTypes.h"
32 #include "llvm/IR/Function.h"
33 #include "llvm/IR/LLVMContext.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/raw_ostream.h"
37 #include "llvm/Target/TargetFrameLowering.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
41 #define DEBUG_TYPE "arm-register-info"
43 #define GET_REGINFO_TARGET_DESC
44 #include "ARMGenRegisterInfo.inc"
48 ARMBaseRegisterInfo::ARMBaseRegisterInfo()
49 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), BasePtr(ARM::R6) {}
51 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
52 return STI.useR7AsFramePointer() ? ARM::R7 : ARM::R11;
56 ARMBaseRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
57 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
58 bool UseSplitPush = STI.splitFramePushPop(*MF);
59 const MCPhysReg *RegList =
62 : (UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList);
64 const Function *F = MF->getFunction();
65 if (F->getCallingConv() == CallingConv::GHC) {
66 // GHC set of callee saved regs is empty as all those regs are
67 // used for passing STG regs around
68 return CSR_NoRegs_SaveList;
69 } else if (F->hasFnAttribute("interrupt")) {
71 // M-class CPUs have hardware which saves the registers needed to allow a
72 // function conforming to the AAPCS to function as a handler.
73 return UseSplitPush ? CSR_AAPCS_SplitPush_SaveList : CSR_AAPCS_SaveList;
74 } else if (F->getFnAttribute("interrupt").getValueAsString() == "FIQ") {
75 // Fast interrupt mode gives the handler a private copy of R8-R14, so less
76 // need to be saved to restore user-mode state.
77 return CSR_FIQ_SaveList;
79 // Generally only R13-R14 (i.e. SP, LR) are automatically preserved by
80 // exception handling.
81 return CSR_GenericInt_SaveList;
85 if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
86 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
87 return CSR_iOS_SwiftError_SaveList;
89 if (STI.isTargetDarwin() && F->getCallingConv() == CallingConv::CXX_FAST_TLS)
90 return MF->getInfo<ARMFunctionInfo>()->isSplitCSR()
91 ? CSR_iOS_CXX_TLS_PE_SaveList
92 : CSR_iOS_CXX_TLS_SaveList;
96 const MCPhysReg *ARMBaseRegisterInfo::getCalleeSavedRegsViaCopy(
97 const MachineFunction *MF) const {
98 assert(MF && "Invalid MachineFunction pointer.");
99 if (MF->getFunction()->getCallingConv() == CallingConv::CXX_FAST_TLS &&
100 MF->getInfo<ARMFunctionInfo>()->isSplitCSR())
101 return CSR_iOS_CXX_TLS_ViaCopy_SaveList;
106 ARMBaseRegisterInfo::getCallPreservedMask(const MachineFunction &MF,
107 CallingConv::ID CC) const {
108 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
109 if (CC == CallingConv::GHC)
110 // This is academic becase all GHC calls are (supposed to be) tail calls
111 return CSR_NoRegs_RegMask;
113 if (STI.isTargetDarwin() && STI.getTargetLowering()->supportSwiftError() &&
114 MF.getFunction()->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
115 return CSR_iOS_SwiftError_RegMask;
117 if (STI.isTargetDarwin() && CC == CallingConv::CXX_FAST_TLS)
118 return CSR_iOS_CXX_TLS_RegMask;
119 return STI.isTargetDarwin() ? CSR_iOS_RegMask : CSR_AAPCS_RegMask;
123 ARMBaseRegisterInfo::getNoPreservedMask() const {
124 return CSR_NoRegs_RegMask;
128 ARMBaseRegisterInfo::getTLSCallPreservedMask(const MachineFunction &MF) const {
129 assert(MF.getSubtarget<ARMSubtarget>().isTargetDarwin() &&
130 "only know about special TLS call on Darwin");
131 return CSR_iOS_TLSCall_RegMask;
135 ARMBaseRegisterInfo::getSjLjDispatchPreservedMask(const MachineFunction &MF) const {
136 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
137 if (!STI.useSoftFloat() && STI.hasVFP2() && !STI.isThumb1Only())
138 return CSR_NoRegs_RegMask;
140 return CSR_FPRegs_RegMask;
145 ARMBaseRegisterInfo::getThisReturnPreservedMask(const MachineFunction &MF,
146 CallingConv::ID CC) const {
147 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
148 // This should return a register mask that is the same as that returned by
149 // getCallPreservedMask but that additionally preserves the register used for
150 // the first i32 argument (which must also be the register used to return a
151 // single i32 return value)
153 // In case that the calling convention does not use the same register for
154 // both or otherwise does not want to enable this optimization, the function
155 // should return NULL
156 if (CC == CallingConv::GHC)
157 // This is academic becase all GHC calls are (supposed to be) tail calls
159 return STI.isTargetDarwin() ? CSR_iOS_ThisReturn_RegMask
160 : CSR_AAPCS_ThisReturn_RegMask;
163 BitVector ARMBaseRegisterInfo::
164 getReservedRegs(const MachineFunction &MF) const {
165 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
166 const ARMFrameLowering *TFI = getFrameLowering(MF);
168 // FIXME: avoid re-calculating this every time.
169 BitVector Reserved(getNumRegs());
170 markSuperRegs(Reserved, ARM::SP);
171 markSuperRegs(Reserved, ARM::PC);
172 markSuperRegs(Reserved, ARM::FPSCR);
173 markSuperRegs(Reserved, ARM::APSR_NZCV);
175 markSuperRegs(Reserved, getFramePointerReg(STI));
176 if (hasBasePointer(MF))
177 markSuperRegs(Reserved, BasePtr);
178 // Some targets reserve R9.
179 if (STI.isR9Reserved())
180 markSuperRegs(Reserved, ARM::R9);
181 // Reserve D16-D31 if the subtarget doesn't support them.
182 if (!STI.hasVFP3() || STI.hasD16()) {
183 static_assert(ARM::D31 == ARM::D16 + 15, "Register list not consecutive!");
184 for (unsigned R = 0; R < 16; ++R)
185 markSuperRegs(Reserved, ARM::D16 + R);
187 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
188 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
189 for (MCSubRegIterator SI(*I, this); SI.isValid(); ++SI)
190 if (Reserved.test(*SI)) markSuperRegs(Reserved, *I);
192 assert(checkAllSuperRegsMarked(Reserved));
196 const TargetRegisterClass *
197 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
198 const MachineFunction &) const {
199 const TargetRegisterClass *Super = RC;
200 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
202 switch (Super->getID()) {
203 case ARM::GPRRegClassID:
204 case ARM::SPRRegClassID:
205 case ARM::DPRRegClassID:
206 case ARM::QPRRegClassID:
207 case ARM::QQPRRegClassID:
208 case ARM::QQQQPRRegClassID:
209 case ARM::GPRPairRegClassID:
217 const TargetRegisterClass *
218 ARMBaseRegisterInfo::getPointerRegClass(const MachineFunction &MF, unsigned Kind)
220 return &ARM::GPRRegClass;
223 const TargetRegisterClass *
224 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
225 if (RC == &ARM::CCRRegClass)
226 return &ARM::rGPRRegClass; // Can't copy CCR registers.
231 ARMBaseRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
232 MachineFunction &MF) const {
233 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
234 const ARMFrameLowering *TFI = getFrameLowering(MF);
236 switch (RC->getID()) {
239 case ARM::tGPRRegClassID:
240 return TFI->hasFP(MF) ? 4 : 5;
241 case ARM::GPRRegClassID: {
242 unsigned FP = TFI->hasFP(MF) ? 1 : 0;
243 return 10 - FP - (STI.isR9Reserved() ? 1 : 0);
245 case ARM::SPRRegClassID: // Currently not used as 'rep' register class.
246 case ARM::DPRRegClassID:
251 // Get the other register in a GPRPair.
252 static unsigned getPairedGPR(unsigned Reg, bool Odd, const MCRegisterInfo *RI) {
253 for (MCSuperRegIterator Supers(Reg, RI); Supers.isValid(); ++Supers)
254 if (ARM::GPRPairRegClass.contains(*Supers))
255 return RI->getSubReg(*Supers, Odd ? ARM::gsub_1 : ARM::gsub_0);
259 // Resolve the RegPairEven / RegPairOdd register allocator hints.
261 ARMBaseRegisterInfo::getRegAllocationHints(unsigned VirtReg,
262 ArrayRef<MCPhysReg> Order,
263 SmallVectorImpl<MCPhysReg> &Hints,
264 const MachineFunction &MF,
265 const VirtRegMap *VRM,
266 const LiveRegMatrix *Matrix) const {
267 const MachineRegisterInfo &MRI = MF.getRegInfo();
268 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg);
271 switch (Hint.first) {
272 case ARMRI::RegPairEven:
275 case ARMRI::RegPairOdd:
279 TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF, VRM);
283 // This register should preferably be even (Odd == 0) or odd (Odd == 1).
284 // Check if the other part of the pair has already been assigned, and provide
285 // the paired register as the first hint.
286 unsigned Paired = Hint.second;
290 unsigned PairedPhys = 0;
291 if (TargetRegisterInfo::isPhysicalRegister(Paired)) {
293 } else if (VRM && VRM->hasPhys(Paired)) {
294 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this);
297 // First prefer the paired physreg.
298 if (PairedPhys && is_contained(Order, PairedPhys))
299 Hints.push_back(PairedPhys);
301 // Then prefer even or odd registers.
302 for (unsigned I = 0, E = Order.size(); I != E; ++I) {
303 unsigned Reg = Order[I];
304 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd)
306 // Don't provide hints that are paired to a reserved register.
307 unsigned Paired = getPairedGPR(Reg, !Odd, this);
308 if (!Paired || MRI.isReserved(Paired))
310 Hints.push_back(Reg);
315 ARMBaseRegisterInfo::updateRegAllocHint(unsigned Reg, unsigned NewReg,
316 MachineFunction &MF) const {
317 MachineRegisterInfo *MRI = &MF.getRegInfo();
318 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg);
319 if ((Hint.first == (unsigned)ARMRI::RegPairOdd ||
320 Hint.first == (unsigned)ARMRI::RegPairEven) &&
321 TargetRegisterInfo::isVirtualRegister(Hint.second)) {
322 // If 'Reg' is one of the even / odd register pair and it's now changed
323 // (e.g. coalesced) into a different register. The other register of the
324 // pair allocation hint must be updated to reflect the relationship
326 unsigned OtherReg = Hint.second;
327 Hint = MRI->getRegAllocationHint(OtherReg);
328 // Make sure the pair has not already divorced.
329 if (Hint.second == Reg) {
330 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg);
331 if (TargetRegisterInfo::isVirtualRegister(NewReg))
332 MRI->setRegAllocationHint(NewReg,
333 Hint.first == (unsigned)ARMRI::RegPairOdd ? ARMRI::RegPairEven
334 : ARMRI::RegPairOdd, OtherReg);
339 bool ARMBaseRegisterInfo::hasBasePointer(const MachineFunction &MF) const {
340 const MachineFrameInfo &MFI = MF.getFrameInfo();
341 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
342 const ARMFrameLowering *TFI = getFrameLowering(MF);
344 // When outgoing call frames are so large that we adjust the stack pointer
345 // around the call, we can no longer use the stack pointer to reach the
346 // emergency spill slot.
347 if (needsStackRealignment(MF) && !TFI->hasReservedCallFrame(MF))
350 // Thumb has trouble with negative offsets from the FP. Thumb2 has a limited
351 // negative range for ldr/str (255), and thumb1 is positive offsets only.
352 // It's going to be better to use the SP or Base Pointer instead. When there
353 // are variable sized objects, we can't reference off of the SP, so we
354 // reserve a Base Pointer.
355 if (AFI->isThumbFunction() && MFI.hasVarSizedObjects()) {
356 // Conservatively estimate whether the negative offset from the frame
357 // pointer will be sufficient to reach. If a function has a smallish
358 // frame, it's less likely to have lots of spills and callee saved
359 // space, so it's all more likely to be within range of the frame pointer.
360 // If it's wrong, the scavenger will still enable access to work, it just
362 if (AFI->isThumb2Function() && MFI.getLocalFrameSize() < 128)
370 bool ARMBaseRegisterInfo::canRealignStack(const MachineFunction &MF) const {
371 const MachineRegisterInfo *MRI = &MF.getRegInfo();
372 const ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
373 const ARMFrameLowering *TFI = getFrameLowering(MF);
374 // We can't realign the stack if:
375 // 1. Dynamic stack realignment is explicitly disabled,
376 // 2. This is a Thumb1 function (it's not useful, so we don't bother), or
377 // 3. There are VLAs in the function and the base pointer is disabled.
378 if (!TargetRegisterInfo::canRealignStack(MF))
380 if (AFI->isThumb1OnlyFunction())
382 // Stack realignment requires a frame pointer. If we already started
383 // register allocation with frame pointer elimination, it is too late now.
384 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())))
386 // We may also need a base pointer if there are dynamic allocas or stack
387 // pointer adjustments around calls.
388 if (TFI->hasReservedCallFrame(MF))
390 // A base pointer is required and allowed. Check that it isn't too late to
392 return MRI->canReserveReg(BasePtr);
395 bool ARMBaseRegisterInfo::
396 cannotEliminateFrame(const MachineFunction &MF) const {
397 const MachineFrameInfo &MFI = MF.getFrameInfo();
398 if (MF.getTarget().Options.DisableFramePointerElim(MF) && MFI.adjustsStack())
400 return MFI.hasVarSizedObjects() || MFI.isFrameAddressTaken()
401 || needsStackRealignment(MF);
405 ARMBaseRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
406 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>();
407 const ARMFrameLowering *TFI = getFrameLowering(MF);
410 return getFramePointerReg(STI);
414 /// emitLoadConstPool - Emits a load from constpool to materialize the
415 /// specified immediate.
416 void ARMBaseRegisterInfo::emitLoadConstPool(
417 MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
418 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val,
419 ARMCC::CondCodes Pred, unsigned PredReg, unsigned MIFlags) const {
420 MachineFunction &MF = *MBB.getParent();
421 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
422 MachineConstantPool *ConstantPool = MF.getConstantPool();
424 ConstantInt::get(Type::getInt32Ty(MF.getFunction()->getContext()), Val);
425 unsigned Idx = ConstantPool->getConstantPoolIndex(C, 4);
427 BuildMI(MBB, MBBI, dl, TII.get(ARM::LDRcp))
428 .addReg(DestReg, getDefRegState(true), SubIdx)
429 .addConstantPoolIndex(Idx)
430 .addImm(0).addImm(Pred).addReg(PredReg)
431 .setMIFlags(MIFlags);
434 bool ARMBaseRegisterInfo::
435 requiresRegisterScavenging(const MachineFunction &MF) const {
439 bool ARMBaseRegisterInfo::
440 trackLivenessAfterRegAlloc(const MachineFunction &MF) const {
444 bool ARMBaseRegisterInfo::
445 requiresFrameIndexScavenging(const MachineFunction &MF) const {
449 bool ARMBaseRegisterInfo::
450 requiresVirtualBaseRegisters(const MachineFunction &MF) const {
454 int64_t ARMBaseRegisterInfo::
455 getFrameIndexInstrOffset(const MachineInstr *MI, int Idx) const {
456 const MCInstrDesc &Desc = MI->getDesc();
457 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
458 int64_t InstrOffs = 0;
462 case ARMII::AddrModeT2_i8:
463 case ARMII::AddrModeT2_i12:
464 case ARMII::AddrMode_i12:
465 InstrOffs = MI->getOperand(Idx+1).getImm();
468 case ARMII::AddrMode5: {
470 const MachineOperand &OffOp = MI->getOperand(Idx+1);
471 InstrOffs = ARM_AM::getAM5Offset(OffOp.getImm());
472 if (ARM_AM::getAM5Op(OffOp.getImm()) == ARM_AM::sub)
473 InstrOffs = -InstrOffs;
477 case ARMII::AddrMode2: {
479 InstrOffs = ARM_AM::getAM2Offset(MI->getOperand(ImmIdx).getImm());
480 if (ARM_AM::getAM2Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
481 InstrOffs = -InstrOffs;
484 case ARMII::AddrMode3: {
486 InstrOffs = ARM_AM::getAM3Offset(MI->getOperand(ImmIdx).getImm());
487 if (ARM_AM::getAM3Op(MI->getOperand(ImmIdx).getImm()) == ARM_AM::sub)
488 InstrOffs = -InstrOffs;
491 case ARMII::AddrModeT1_s: {
493 InstrOffs = MI->getOperand(ImmIdx).getImm();
498 llvm_unreachable("Unsupported addressing mode!");
501 return InstrOffs * Scale;
504 /// needsFrameBaseReg - Returns true if the instruction's frame index
505 /// reference would be better served by a base register other than FP
506 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
507 /// references it should create new base registers for.
508 bool ARMBaseRegisterInfo::
509 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
510 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) {
511 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
514 // It's the load/store FI references that cause issues, as it can be difficult
515 // to materialize the offset if it won't fit in the literal field. Estimate
516 // based on the size of the local frame and some conservative assumptions
517 // about the rest of the stack frame (note, this is pre-regalloc, so
518 // we don't know everything for certain yet) whether this offset is likely
519 // to be out of range of the immediate. Return true if so.
521 // We only generate virtual base registers for loads and stores, so
522 // return false for everything else.
523 unsigned Opc = MI->getOpcode();
525 case ARM::LDRi12: case ARM::LDRH: case ARM::LDRBi12:
526 case ARM::STRi12: case ARM::STRH: case ARM::STRBi12:
527 case ARM::t2LDRi12: case ARM::t2LDRi8:
528 case ARM::t2STRi12: case ARM::t2STRi8:
529 case ARM::VLDRS: case ARM::VLDRD:
530 case ARM::VSTRS: case ARM::VSTRD:
531 case ARM::tSTRspi: case ARM::tLDRspi:
537 // Without a virtual base register, if the function has variable sized
538 // objects, all fixed-size local references will be via the frame pointer,
539 // Approximate the offset and see if it's legal for the instruction.
540 // Note that the incoming offset is based on the SP value at function entry,
541 // so it'll be negative.
542 MachineFunction &MF = *MI->getParent()->getParent();
543 const ARMFrameLowering *TFI = getFrameLowering(MF);
544 MachineFrameInfo &MFI = MF.getFrameInfo();
545 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
547 // Estimate an offset from the frame pointer.
548 // Conservatively assume all callee-saved registers get pushed. R4-R6
549 // will be earlier than the FP, so we ignore those.
551 int64_t FPOffset = Offset - 8;
552 // ARM and Thumb2 functions also need to consider R8-R11 and D8-D15
553 if (!AFI->isThumbFunction() || !AFI->isThumb1OnlyFunction())
555 // Estimate an offset from the stack pointer.
556 // The incoming offset is relating to the SP at the start of the function,
557 // but when we access the local it'll be relative to the SP after local
558 // allocation, so adjust our SP-relative offset by that allocation size.
559 Offset += MFI.getLocalFrameSize();
560 // Assume that we'll have at least some spill slots allocated.
561 // FIXME: This is a total SWAG number. We should run some statistics
562 // and pick a real one.
563 Offset += 128; // 128 bytes of spill slots
565 // If there's a frame pointer and the addressing mode allows it, try using it.
566 // The FP is only available if there is no dynamic realignment. We
567 // don't know for sure yet whether we'll need that, so we guess based
568 // on whether there are any local variables that would trigger it.
569 unsigned StackAlign = TFI->getStackAlignment();
570 if (TFI->hasFP(MF) &&
571 !((MFI.getLocalFrameMaxAlign() > StackAlign) && canRealignStack(MF))) {
572 if (isFrameOffsetLegal(MI, getFrameRegister(MF), FPOffset))
575 // If we can reference via the stack pointer, try that.
576 // FIXME: This (and the code that resolves the references) can be improved
577 // to only disallow SP relative references in the live range of
578 // the VLA(s). In practice, it's unclear how much difference that
579 // would make, but it may be worth doing.
580 if (!MFI.hasVarSizedObjects() && isFrameOffsetLegal(MI, ARM::SP, Offset))
583 // The offset likely isn't legal, we want to allocate a virtual base register.
587 /// materializeFrameBaseRegister - Insert defining instruction(s) for BaseReg to
588 /// be a pointer to FrameIdx at the beginning of the basic block.
589 void ARMBaseRegisterInfo::
590 materializeFrameBaseRegister(MachineBasicBlock *MBB,
591 unsigned BaseReg, int FrameIdx,
592 int64_t Offset) const {
593 ARMFunctionInfo *AFI = MBB->getParent()->getInfo<ARMFunctionInfo>();
594 unsigned ADDriOpc = !AFI->isThumbFunction() ? ARM::ADDri :
595 (AFI->isThumb1OnlyFunction() ? ARM::tADDframe : ARM::t2ADDri);
597 MachineBasicBlock::iterator Ins = MBB->begin();
598 DebugLoc DL; // Defaults to "unknown"
599 if (Ins != MBB->end())
600 DL = Ins->getDebugLoc();
602 const MachineFunction &MF = *MBB->getParent();
603 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
604 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
605 const MCInstrDesc &MCID = TII.get(ADDriOpc);
606 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
608 MachineInstrBuilder MIB = BuildMI(*MBB, Ins, DL, MCID, BaseReg)
609 .addFrameIndex(FrameIdx).addImm(Offset);
611 if (!AFI->isThumb1OnlyFunction())
612 AddDefaultCC(AddDefaultPred(MIB));
615 void ARMBaseRegisterInfo::resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
616 int64_t Offset) const {
617 MachineBasicBlock &MBB = *MI.getParent();
618 MachineFunction &MF = *MBB.getParent();
619 const ARMBaseInstrInfo &TII =
620 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
621 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
622 int Off = Offset; // ARM doesn't need the general 64-bit offsets
625 assert(!AFI->isThumb1OnlyFunction() &&
626 "This resolveFrameIndex does not support Thumb1!");
628 while (!MI.getOperand(i).isFI()) {
630 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
633 if (!AFI->isThumbFunction())
634 Done = rewriteARMFrameIndex(MI, i, BaseReg, Off, TII);
636 assert(AFI->isThumb2Function());
637 Done = rewriteT2FrameIndex(MI, i, BaseReg, Off, TII);
639 assert (Done && "Unable to resolve frame index!");
643 bool ARMBaseRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
644 int64_t Offset) const {
645 const MCInstrDesc &Desc = MI->getDesc();
646 unsigned AddrMode = (Desc.TSFlags & ARMII::AddrModeMask);
649 while (!MI->getOperand(i).isFI()) {
651 assert(i < MI->getNumOperands() &&"Instr doesn't have FrameIndex operand!");
654 // AddrMode4 and AddrMode6 cannot handle any offset.
655 if (AddrMode == ARMII::AddrMode4 || AddrMode == ARMII::AddrMode6)
658 unsigned NumBits = 0;
660 bool isSigned = true;
662 case ARMII::AddrModeT2_i8:
663 case ARMII::AddrModeT2_i12:
664 // i8 supports only negative, and i12 supports only positive, so
665 // based on Offset sign, consider the appropriate instruction
674 case ARMII::AddrMode5:
679 case ARMII::AddrMode_i12:
680 case ARMII::AddrMode2:
683 case ARMII::AddrMode3:
686 case ARMII::AddrModeT1_s:
687 NumBits = (BaseReg == ARM::SP ? 8 : 5);
692 llvm_unreachable("Unsupported addressing mode!");
695 Offset += getFrameIndexInstrOffset(MI, i);
696 // Make sure the offset is encodable for instructions that scale the
698 if ((Offset & (Scale-1)) != 0)
701 if (isSigned && Offset < 0)
704 unsigned Mask = (1 << NumBits) - 1;
705 if ((unsigned)Offset <= Mask * Scale)
712 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
713 int SPAdj, unsigned FIOperandNum,
714 RegScavenger *RS) const {
715 MachineInstr &MI = *II;
716 MachineBasicBlock &MBB = *MI.getParent();
717 MachineFunction &MF = *MBB.getParent();
718 const ARMBaseInstrInfo &TII =
719 *static_cast<const ARMBaseInstrInfo *>(MF.getSubtarget().getInstrInfo());
720 const ARMFrameLowering *TFI = getFrameLowering(MF);
721 ARMFunctionInfo *AFI = MF.getInfo<ARMFunctionInfo>();
722 assert(!AFI->isThumb1OnlyFunction() &&
723 "This eliminateFrameIndex does not support Thumb1!");
724 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
727 int Offset = TFI->ResolveFrameIndexReference(MF, FrameIndex, FrameReg, SPAdj);
729 // PEI::scavengeFrameVirtualRegs() cannot accurately track SPAdj because the
730 // call frame setup/destroy instructions have already been eliminated. That
731 // means the stack pointer cannot be used to access the emergency spill slot
732 // when !hasReservedCallFrame().
734 if (RS && FrameReg == ARM::SP && RS->isScavengingFrameIndex(FrameIndex)){
735 assert(TFI->hasReservedCallFrame(MF) &&
736 "Cannot use SP to access the emergency spill slot in "
737 "functions without a reserved call frame");
738 assert(!MF.getFrameInfo().hasVarSizedObjects() &&
739 "Cannot use SP to access the emergency spill slot in "
740 "functions with variable sized frame objects");
744 assert(!MI.isDebugValue() && "DBG_VALUEs should be handled in target-independent code");
746 // Modify MI as necessary to handle as much of 'Offset' as possible
748 if (!AFI->isThumbFunction())
749 Done = rewriteARMFrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
751 assert(AFI->isThumb2Function());
752 Done = rewriteT2FrameIndex(MI, FIOperandNum, FrameReg, Offset, TII);
757 // If we get here, the immediate doesn't fit into the instruction. We folded
758 // as much as possible above, handle the rest, providing a register that is
761 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode4 ||
762 (MI.getDesc().TSFlags & ARMII::AddrModeMask) == ARMII::AddrMode6) &&
763 "This code isn't needed if offset already handled!");
765 unsigned ScratchReg = 0;
766 int PIdx = MI.findFirstPredOperandIdx();
767 ARMCC::CondCodes Pred = (PIdx == -1)
768 ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();
769 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg();
771 // Must be addrmode4/6.
772 MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, false);
774 ScratchReg = MF.getRegInfo().createVirtualRegister(&ARM::GPRRegClass);
775 if (!AFI->isThumbFunction())
776 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
777 Offset, Pred, PredReg, TII);
779 assert(AFI->isThumb2Function());
780 emitT2RegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
781 Offset, Pred, PredReg, TII);
783 // Update the original instruction to use the scratch register.
784 MI.getOperand(FIOperandNum).ChangeToRegister(ScratchReg, false, false,true);
788 bool ARMBaseRegisterInfo::shouldCoalesce(MachineInstr *MI,
789 const TargetRegisterClass *SrcRC,
791 const TargetRegisterClass *DstRC,
793 const TargetRegisterClass *NewRC) const {
794 auto MBB = MI->getParent();
795 auto MF = MBB->getParent();
796 const MachineRegisterInfo &MRI = MF->getRegInfo();
797 // If not copying into a sub-register this should be ok because we shouldn't
798 // need to split the reg.
801 // Small registers don't frequently cause a problem, so we can coalesce them.
802 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32)
806 MRI.getTargetRegisterInfo()->getRegClassWeight(NewRC);
808 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC);
810 MRI.getTargetRegisterInfo()->getRegClassWeight(DstRC);
811 // If the source register class is more expensive than the destination, the
812 // coalescing is probably profitable.
813 if (SrcRCWeight.RegWeight > NewRCWeight.RegWeight)
815 if (DstRCWeight.RegWeight > NewRCWeight.RegWeight)
818 // If the register allocator isn't constrained, we can always allow coalescing
819 // unfortunately we don't know yet if we will be constrained.
820 // The goal of this heuristic is to restrict how many expensive registers
821 // we allow to coalesce in a given basic block.
822 auto AFI = MF->getInfo<ARMFunctionInfo>();
823 auto It = AFI->getCoalescedWeight(MBB);
825 DEBUG(dbgs() << "\tARM::shouldCoalesce - Coalesced Weight: "
826 << It->second << "\n");
827 DEBUG(dbgs() << "\tARM::shouldCoalesce - Reg Weight: "
828 << NewRCWeight.RegWeight << "\n");
830 // This number is the largest round number that which meets the criteria:
831 // (1) addresses PR18825
832 // (2) generates better code in some test cases (like vldm-shed-a9.ll)
833 // (3) Doesn't regress any test cases (in-tree, test-suite, and SPEC)
834 // In practice the SizeMultiplier will only factor in for straight line code
835 // that uses a lot of NEON vectors, which isn't terribly common.
836 unsigned SizeMultiplier = MBB->size()/100;
837 SizeMultiplier = SizeMultiplier ? SizeMultiplier : 1;
838 if (It->second < NewRCWeight.WeightLimit * SizeMultiplier) {
839 It->second += NewRCWeight.RegWeight;