1 //===-- ARMBaseRegisterInfo.h - ARM Register Information Impl ---*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the base ARM implementation of TargetRegisterInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
15 #define LLVM_LIB_TARGET_ARM_ARMBASEREGISTERINFO_H
17 #include "MCTargetDesc/ARMBaseInfo.h"
18 #include "llvm/Target/TargetRegisterInfo.h"
20 #define GET_REGINFO_HEADER
21 #include "ARMGenRegisterInfo.inc"
24 /// Register allocation hints.
32 /// isARMArea1Register - Returns true if the register is a low register (r0-r7)
33 /// or a stack/pc register that we should push/pop.
34 static inline bool isARMArea1Register(unsigned Reg, bool isIOS) {
37 case R0: case R1: case R2: case R3:
38 case R4: case R5: case R6: case R7:
39 case LR: case SP: case PC:
41 case R8: case R9: case R10: case R11: case R12:
42 // For iOS we want r7 and lr to be next to each other.
49 static inline bool isARMArea2Register(unsigned Reg, bool isIOS) {
52 case R8: case R9: case R10: case R11: case R12:
53 // iOS has this second area.
60 static inline bool isARMArea3Register(unsigned Reg, bool isIOS) {
63 case D15: case D14: case D13: case D12:
64 case D11: case D10: case D9: case D8:
65 case D7: case D6: case D5: case D4:
66 case D3: case D2: case D1: case D0:
67 case D31: case D30: case D29: case D28:
68 case D27: case D26: case D25: case D24:
69 case D23: case D22: case D21: case D20:
70 case D19: case D18: case D17: case D16:
77 static inline bool isCalleeSavedRegister(unsigned Reg,
78 const MCPhysReg *CSRegs) {
79 for (unsigned i = 0; CSRegs[i]; ++i)
85 class ARMBaseRegisterInfo : public ARMGenRegisterInfo {
87 /// BasePtr - ARM physical register used as a base ptr in complex stack
88 /// frames. I.e., when we need a 3rd base, not just SP and FP, due to
89 /// variable size stack objects.
92 // Can be only subclassed.
93 explicit ARMBaseRegisterInfo();
95 // Return the opcode that implements 'Op', or 0 if no opcode
96 unsigned getOpcode(int Op) const;
99 /// Code Generation virtual methods...
100 const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
102 getCalleeSavedRegsViaCopy(const MachineFunction *MF) const;
103 const uint32_t *getCallPreservedMask(const MachineFunction &MF,
104 CallingConv::ID) const override;
105 const uint32_t *getNoPreservedMask() const override;
106 const uint32_t *getTLSCallPreservedMask(const MachineFunction &MF) const;
107 const uint32_t *getSjLjDispatchPreservedMask(const MachineFunction &MF) const;
109 /// getThisReturnPreservedMask - Returns a call preserved mask specific to the
110 /// case that 'returned' is on an i32 first argument if the calling convention
111 /// is one that can (partially) model this attribute with a preserved mask
112 /// (i.e. it is a calling convention that uses the same register for the first
113 /// i32 argument and an i32 return value)
115 /// Should return NULL in the case that the calling convention does not have
117 const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
118 CallingConv::ID) const;
120 BitVector getReservedRegs(const MachineFunction &MF) const override;
122 const TargetRegisterClass *
123 getPointerRegClass(const MachineFunction &MF,
124 unsigned Kind = 0) const override;
125 const TargetRegisterClass *
126 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
128 const TargetRegisterClass *
129 getLargestLegalSuperClass(const TargetRegisterClass *RC,
130 const MachineFunction &MF) const override;
132 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
133 MachineFunction &MF) const override;
135 void getRegAllocationHints(unsigned VirtReg,
136 ArrayRef<MCPhysReg> Order,
137 SmallVectorImpl<MCPhysReg> &Hints,
138 const MachineFunction &MF,
139 const VirtRegMap *VRM,
140 const LiveRegMatrix *Matrix) const override;
142 void updateRegAllocHint(unsigned Reg, unsigned NewReg,
143 MachineFunction &MF) const override;
145 bool hasBasePointer(const MachineFunction &MF) const;
147 bool canRealignStack(const MachineFunction &MF) const override;
148 int64_t getFrameIndexInstrOffset(const MachineInstr *MI,
149 int Idx) const override;
150 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const override;
151 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
152 unsigned BaseReg, int FrameIdx,
153 int64_t Offset) const override;
154 void resolveFrameIndex(MachineInstr &MI, unsigned BaseReg,
155 int64_t Offset) const override;
156 bool isFrameOffsetLegal(const MachineInstr *MI, unsigned BaseReg,
157 int64_t Offset) const override;
159 bool cannotEliminateFrame(const MachineFunction &MF) const;
161 // Debug information queries.
162 unsigned getFrameRegister(const MachineFunction &MF) const override;
163 unsigned getBaseRegister() const { return BasePtr; }
165 bool isLowRegister(unsigned Reg) const;
168 /// emitLoadConstPool - Emits a load from constpool to materialize the
169 /// specified immediate.
171 emitLoadConstPool(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI,
172 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx,
173 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
174 unsigned PredReg = 0,
175 unsigned MIFlags = MachineInstr::NoFlags) const;
177 /// Code Generation virtual methods...
178 bool requiresRegisterScavenging(const MachineFunction &MF) const override;
180 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
182 bool requiresFrameIndexScavenging(const MachineFunction &MF) const override;
184 bool requiresVirtualBaseRegisters(const MachineFunction &MF) const override;
186 void eliminateFrameIndex(MachineBasicBlock::iterator II,
187 int SPAdj, unsigned FIOperandNum,
188 RegScavenger *RS = nullptr) const override;
190 /// \brief SrcRC and DstRC will be morphed into NewRC if this returns true
191 bool shouldCoalesce(MachineInstr *MI,
192 const TargetRegisterClass *SrcRC,
194 const TargetRegisterClass *DstRC,
196 const TargetRegisterClass *NewRC) const override;
199 } // end namespace llvm