1 //===-- ARMCallingConv.td - Calling Conventions for ARM ----*- tablegen -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
9 // This describes the calling conventions for ARM architecture.
10 //===----------------------------------------------------------------------===//
12 /// CCIfAlign - Match of the original alignment of the arg
13 class CCIfAlign<string Align, CCAction A>:
14 CCIf<!strconcat("ArgFlags.getOrigAlign() == ", Align), A>;
16 //===----------------------------------------------------------------------===//
17 // ARM APCS Calling Convention
18 //===----------------------------------------------------------------------===//
19 def CC_ARM_APCS : CallingConv<[
21 // Handles byval parameters.
22 CCIfByVal<CCPassByVal<4, 4>>,
24 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
26 // Pass SwiftSelf in a callee saved register.
27 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
29 // A SwiftError is passed in R8.
30 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
32 // Handle all vector types as either f64 or v2f64.
33 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
34 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
36 // f64 and v2f64 are passed in adjacent GPRs, possibly split onto the stack
37 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_APCS_Custom_f64">>,
39 CCIfType<[f32], CCBitConvertToType<i32>>,
40 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
42 CCIfType<[i32], CCAssignToStack<4, 4>>,
43 CCIfType<[f64], CCAssignToStack<8, 4>>,
44 CCIfType<[v2f64], CCAssignToStack<16, 4>>
47 def RetCC_ARM_APCS : CallingConv<[
48 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
49 CCIfType<[f32], CCBitConvertToType<i32>>,
51 // Pass SwiftSelf in a callee saved register.
52 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
54 // A SwiftError is returned in R8.
55 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
57 // Handle all vector types as either f64 or v2f64.
58 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
59 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
61 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_APCS_Custom_f64">>,
63 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
64 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
67 //===----------------------------------------------------------------------===//
68 // ARM APCS Calling Convention for FastCC (when VFP2 or later is available)
69 //===----------------------------------------------------------------------===//
70 def FastCC_ARM_APCS : CallingConv<[
71 // Handle all vector types as either f64 or v2f64.
72 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
73 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
75 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
76 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
77 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
78 S9, S10, S11, S12, S13, S14, S15]>>,
80 // CPRCs may be allocated to co-processor registers or the stack - they
81 // may never be allocated to core registers.
82 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
83 CCIfType<[f64], CCAssignToStackWithShadow<8, 4, [Q0, Q1, Q2, Q3]>>,
84 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 4, [Q0, Q1, Q2, Q3]>>,
86 CCDelegateTo<CC_ARM_APCS>
89 def RetFastCC_ARM_APCS : CallingConv<[
90 // Handle all vector types as either f64 or v2f64.
91 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
92 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
94 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
95 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
96 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
97 S9, S10, S11, S12, S13, S14, S15]>>,
98 CCDelegateTo<RetCC_ARM_APCS>
101 //===----------------------------------------------------------------------===//
102 // ARM APCS Calling Convention for GHC
103 //===----------------------------------------------------------------------===//
105 def CC_ARM_APCS_GHC : CallingConv<[
106 // Handle all vector types as either f64 or v2f64.
107 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
108 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
110 CCIfType<[v2f64], CCAssignToReg<[Q4, Q5]>>,
111 CCIfType<[f64], CCAssignToReg<[D8, D9, D10, D11]>>,
112 CCIfType<[f32], CCAssignToReg<[S16, S17, S18, S19, S20, S21, S22, S23]>>,
114 // Promote i8/i16 arguments to i32.
115 CCIfType<[i8, i16], CCPromoteToType<i32>>,
117 // Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, SpLim
118 CCIfType<[i32], CCAssignToReg<[R4, R5, R6, R7, R8, R9, R10, R11]>>
121 //===----------------------------------------------------------------------===//
122 // ARM AAPCS (EABI) Calling Convention, common parts
123 //===----------------------------------------------------------------------===//
125 def CC_ARM_AAPCS_Common : CallingConv<[
127 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
129 // i64/f64 is passed in even pairs of GPRs
130 // i64 is 8-aligned i32 here, so we may need to eat R1 as a pad register
131 // (and the same is true for f64 if VFP is not enabled)
132 CCIfType<[i32], CCIfAlign<"8", CCAssignToRegWithShadow<[R0, R2], [R0, R1]>>>,
133 CCIfType<[i32], CCIf<"ArgFlags.getOrigAlign() != 8",
134 CCAssignToReg<[R0, R1, R2, R3]>>>,
136 CCIfType<[i32], CCIfAlign<"8", CCAssignToStackWithShadow<4, 8, [R0, R1, R2, R3]>>>,
137 CCIfType<[i32], CCAssignToStackWithShadow<4, 4, [R0, R1, R2, R3]>>,
138 CCIfType<[f32], CCAssignToStackWithShadow<4, 4, [Q0, Q1, Q2, Q3]>>,
139 CCIfType<[f64], CCAssignToStackWithShadow<8, 8, [Q0, Q1, Q2, Q3]>>,
140 CCIfType<[v2f64], CCIfAlign<"16",
141 CCAssignToStackWithShadow<16, 16, [Q0, Q1, Q2, Q3]>>>,
142 CCIfType<[v2f64], CCAssignToStackWithShadow<16, 8, [Q0, Q1, Q2, Q3]>>
145 def RetCC_ARM_AAPCS_Common : CallingConv<[
146 CCIfType<[i1, i8, i16], CCPromoteToType<i32>>,
147 CCIfType<[i32], CCAssignToReg<[R0, R1, R2, R3]>>,
148 CCIfType<[i64], CCAssignToRegWithShadow<[R0, R2], [R1, R3]>>
151 //===----------------------------------------------------------------------===//
152 // ARM AAPCS (EABI) Calling Convention
153 //===----------------------------------------------------------------------===//
155 def CC_ARM_AAPCS : CallingConv<[
156 // Handles byval parameters.
157 CCIfByVal<CCPassByVal<4, 4>>,
159 // The 'nest' parameter, if any, is passed in R12.
160 CCIfNest<CCAssignToReg<[R12]>>,
162 // Handle all vector types as either f64 or v2f64.
163 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
164 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
166 // Pass SwiftSelf in a callee saved register.
167 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
169 // A SwiftError is passed in R8.
170 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
172 CCIfType<[f64, v2f64], CCCustom<"CC_ARM_AAPCS_Custom_f64">>,
173 CCIfType<[f32], CCBitConvertToType<i32>>,
174 CCDelegateTo<CC_ARM_AAPCS_Common>
177 def RetCC_ARM_AAPCS : CallingConv<[
178 // Handle all vector types as either f64 or v2f64.
179 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
180 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
182 // Pass SwiftSelf in a callee saved register.
183 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
185 // A SwiftError is returned in R8.
186 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
188 CCIfType<[f64, v2f64], CCCustom<"RetCC_ARM_AAPCS_Custom_f64">>,
189 CCIfType<[f32], CCBitConvertToType<i32>>,
190 CCDelegateTo<RetCC_ARM_AAPCS_Common>
193 //===----------------------------------------------------------------------===//
194 // ARM AAPCS-VFP (EABI) Calling Convention
195 // Also used for FastCC (when VFP2 or later is available)
196 //===----------------------------------------------------------------------===//
198 def CC_ARM_AAPCS_VFP : CallingConv<[
199 // Handles byval parameters.
200 CCIfByVal<CCPassByVal<4, 4>>,
202 // Handle all vector types as either f64 or v2f64.
203 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
204 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
206 // Pass SwiftSelf in a callee saved register.
207 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
209 // A SwiftError is passed in R8.
210 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
212 // HFAs are passed in a contiguous block of registers, or on the stack
213 CCIfConsecutiveRegs<CCCustom<"CC_ARM_AAPCS_Custom_Aggregate">>,
215 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
216 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
217 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
218 S9, S10, S11, S12, S13, S14, S15]>>,
219 CCDelegateTo<CC_ARM_AAPCS_Common>
222 def RetCC_ARM_AAPCS_VFP : CallingConv<[
223 // Handle all vector types as either f64 or v2f64.
224 CCIfType<[v1i64, v2i32, v4i16, v8i8, v2f32], CCBitConvertToType<f64>>,
225 CCIfType<[v2i64, v4i32, v8i16, v16i8, v4f32], CCBitConvertToType<v2f64>>,
227 // Pass SwiftSelf in a callee saved register.
228 CCIfSwiftSelf<CCIfType<[i32], CCAssignToReg<[R10]>>>,
230 // A SwiftError is returned in R8.
231 CCIfSwiftError<CCIfType<[i32], CCAssignToReg<[R8]>>>,
233 CCIfType<[v2f64], CCAssignToReg<[Q0, Q1, Q2, Q3]>>,
234 CCIfType<[f64], CCAssignToReg<[D0, D1, D2, D3, D4, D5, D6, D7]>>,
235 CCIfType<[f32], CCAssignToReg<[S0, S1, S2, S3, S4, S5, S6, S7, S8,
236 S9, S10, S11, S12, S13, S14, S15]>>,
237 CCDelegateTo<RetCC_ARM_AAPCS_Common>
240 //===----------------------------------------------------------------------===//
241 // Callee-saved register lists.
242 //===----------------------------------------------------------------------===//
244 def CSR_NoRegs : CalleeSavedRegs<(add)>;
245 def CSR_FPRegs : CalleeSavedRegs<(add (sequence "D%u", 0, 31))>;
247 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
248 (sequence "D%u", 15, 8))>;
250 // The order of callee-saved registers needs to match the order we actually push
251 // them in FrameLowering, because this order is what's used by
252 // PrologEpilogInserter to allocate frame index slots. So when R7 is the frame
253 // pointer, we use this AAPCS alternative.
254 def CSR_AAPCS_SplitPush : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
256 (sequence "D%u", 15, 8))>;
258 // Constructors and destructors return 'this' in the ARM C++ ABI; since 'this'
259 // and the pointer return value are both passed in R0 in these cases, this can
260 // be partially modelled by treating R0 as a callee-saved register
261 // Only the resulting RegMask is used; the SaveList is ignored
262 def CSR_AAPCS_ThisReturn : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6,
263 R5, R4, (sequence "D%u", 15, 8),
266 // iOS ABI deviates from ARM standard ABI. R9 is not a callee-saved register.
267 // Also save R7-R4 first to match the stack frame fixed spill areas.
268 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
270 // R8 is used to pass swifterror, remove it from CSR.
271 def CSR_iOS_SwiftError : CalleeSavedRegs<(sub CSR_iOS, R8)>;
273 def CSR_iOS_ThisReturn : CalleeSavedRegs<(add LR, R7, R6, R5, R4,
274 (sub CSR_AAPCS_ThisReturn, R9))>;
276 def CSR_iOS_TLSCall : CalleeSavedRegs<(add LR, SP,
277 (sequence "R%u", 12, 1),
278 (sequence "D%u", 31, 0))>;
280 // C++ TLS access function saves all registers except SP. Try to match
281 // the order of CSRs in CSR_iOS.
282 def CSR_iOS_CXX_TLS : CalleeSavedRegs<(add CSR_iOS, (sequence "R%u", 12, 1),
283 (sequence "D%u", 31, 0))>;
285 // CSRs that are handled by prologue, epilogue.
286 def CSR_iOS_CXX_TLS_PE : CalleeSavedRegs<(add LR, R12, R11, R7, R5, R4)>;
288 // CSRs that are handled explicitly via copies.
289 def CSR_iOS_CXX_TLS_ViaCopy : CalleeSavedRegs<(sub CSR_iOS_CXX_TLS,
290 CSR_iOS_CXX_TLS_PE)>;
292 // The "interrupt" attribute is used to generate code that is acceptable in
293 // exception-handlers of various kinds. It makes us use a different return
294 // instruction (handled elsewhere) and affects which registers we must return to
295 // our "caller" in the same state as we receive them.
297 // For most interrupts, all registers except SP and LR are shared with
298 // user-space. We mark LR to be saved anyway, since this is what the ARM backend
299 // generally does rather than tracking its liveness as a normal register.
300 def CSR_GenericInt : CalleeSavedRegs<(add LR, (sequence "R%u", 12, 0))>;
302 // The fast interrupt handlers have more private state and get their own copies
303 // of R8-R12, in addition to SP and LR. As before, mark LR for saving too.
305 // FIXME: we mark R11 as callee-saved since it's often the frame-pointer, and
306 // current frame lowering expects to encounter it while processing callee-saved
308 def CSR_FIQ : CalleeSavedRegs<(add LR, R11, (sequence "R%u", 7, 0))>;