1 //===-- ARMConstantIslandPass.cpp - ARM constant islands ------------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that splits the constant pool up into 'islands'
11 // which are scattered through-out the function. This is required due to the
12 // limited pc-relative displacements that ARM has.
14 //===----------------------------------------------------------------------===//
17 #include "ARMBaseInstrInfo.h"
18 #include "ARMBasicBlockInfo.h"
19 #include "ARMMachineFunctionInfo.h"
20 #include "ARMSubtarget.h"
21 #include "MCTargetDesc/ARMBaseInfo.h"
22 #include "Thumb2InstrInfo.h"
23 #include "llvm/ADT/DenseMap.h"
24 #include "llvm/ADT/SmallSet.h"
25 #include "llvm/ADT/SmallVector.h"
26 #include "llvm/ADT/Statistic.h"
27 #include "llvm/ADT/STLExtras.h"
28 #include "llvm/ADT/StringRef.h"
29 #include "llvm/CodeGen/MachineBasicBlock.h"
30 #include "llvm/CodeGen/MachineConstantPool.h"
31 #include "llvm/CodeGen/MachineFunction.h"
32 #include "llvm/CodeGen/MachineFunctionPass.h"
33 #include "llvm/CodeGen/MachineInstr.h"
34 #include "llvm/CodeGen/MachineJumpTableInfo.h"
35 #include "llvm/CodeGen/MachineOperand.h"
36 #include "llvm/CodeGen/MachineRegisterInfo.h"
37 #include "llvm/IR/DataLayout.h"
38 #include "llvm/IR/DebugLoc.h"
39 #include "llvm/MC/MCInstrDesc.h"
40 #include "llvm/Support/CommandLine.h"
41 #include "llvm/Support/Compiler.h"
42 #include "llvm/Support/Debug.h"
43 #include "llvm/Support/ErrorHandling.h"
44 #include "llvm/Support/Format.h"
45 #include "llvm/Support/MathExtras.h"
46 #include "llvm/Support/raw_ostream.h"
57 #define DEBUG_TYPE "arm-cp-islands"
59 #define ARM_CP_ISLANDS_OPT_NAME \
60 "ARM constant island placement and branch shortening pass"
61 STATISTIC(NumCPEs, "Number of constpool entries");
62 STATISTIC(NumSplit, "Number of uncond branches inserted");
63 STATISTIC(NumCBrFixed, "Number of cond branches fixed");
64 STATISTIC(NumUBrFixed, "Number of uncond branches fixed");
65 STATISTIC(NumTBs, "Number of table branches generated");
66 STATISTIC(NumT2CPShrunk, "Number of Thumb2 constantpool instructions shrunk");
67 STATISTIC(NumT2BrShrunk, "Number of Thumb2 immediate branches shrunk");
68 STATISTIC(NumCBZ, "Number of CBZ / CBNZ formed");
69 STATISTIC(NumJTMoved, "Number of jump table destination blocks moved");
70 STATISTIC(NumJTInserted, "Number of jump table intermediate blocks inserted");
73 AdjustJumpTableBlocks("arm-adjust-jump-tables", cl::Hidden, cl::init(true),
74 cl::desc("Adjust basic block layout to better use TB[BH]"));
76 static cl::opt<unsigned>
77 CPMaxIteration("arm-constant-island-max-iteration", cl::Hidden, cl::init(30),
78 cl::desc("The max number of iteration for converge"));
80 static cl::opt<bool> SynthesizeThumb1TBB(
81 "arm-synthesize-thumb-1-tbb", cl::Hidden, cl::init(true),
82 cl::desc("Use compressed jump tables in Thumb-1 by synthesizing an "
83 "equivalent to the TBB/TBH instructions"));
87 /// ARMConstantIslands - Due to limited PC-relative displacements, ARM
88 /// requires constant pool entries to be scattered among the instructions
89 /// inside a function. To do this, it completely ignores the normal LLVM
90 /// constant pool; instead, it places constants wherever it feels like with
91 /// special instructions.
93 /// The terminology used in this pass includes:
94 /// Islands - Clumps of constants placed in the function.
95 /// Water - Potential places where an island could be formed.
96 /// CPE - A constant pool entry that has been placed somewhere, which
97 /// tracks a list of users.
98 class ARMConstantIslands : public MachineFunctionPass {
99 std::vector<BasicBlockInfo> BBInfo;
101 /// WaterList - A sorted list of basic blocks where islands could be placed
102 /// (i.e. blocks that don't fall through to the following block, due
103 /// to a return, unreachable, or unconditional branch).
104 std::vector<MachineBasicBlock*> WaterList;
106 /// NewWaterList - The subset of WaterList that was created since the
107 /// previous iteration by inserting unconditional branches.
108 SmallSet<MachineBasicBlock*, 4> NewWaterList;
110 typedef std::vector<MachineBasicBlock*>::iterator water_iterator;
112 /// CPUser - One user of a constant pool, keeping the machine instruction
113 /// pointer, the constant pool being referenced, and the max displacement
114 /// allowed from the instruction to the CP. The HighWaterMark records the
115 /// highest basic block where a new CPEntry can be placed. To ensure this
116 /// pass terminates, the CP entries are initially placed at the end of the
117 /// function and then move monotonically to lower addresses. The
118 /// exception to this rule is when the current CP entry for a particular
119 /// CPUser is out of range, but there is another CP entry for the same
120 /// constant value in range. We want to use the existing in-range CP
121 /// entry, but if it later moves out of range, the search for new water
122 /// should resume where it left off. The HighWaterMark is used to record
127 MachineBasicBlock *HighWaterMark;
133 CPUser(MachineInstr *mi, MachineInstr *cpemi, unsigned maxdisp,
134 bool neg, bool soimm)
135 : MI(mi), CPEMI(cpemi), MaxDisp(maxdisp), NegOk(neg), IsSoImm(soimm),
136 KnownAlignment(false) {
137 HighWaterMark = CPEMI->getParent();
140 /// getMaxDisp - Returns the maximum displacement supported by MI.
141 /// Correct for unknown alignment.
142 /// Conservatively subtract 2 bytes to handle weird alignment effects.
143 unsigned getMaxDisp() const {
144 return (KnownAlignment ? MaxDisp : MaxDisp - 2) - 2;
148 /// CPUsers - Keep track of all of the machine instructions that use various
149 /// constant pools and their max displacement.
150 std::vector<CPUser> CPUsers;
152 /// CPEntry - One per constant pool entry, keeping the machine instruction
153 /// pointer, the constpool index, and the number of CPUser's which
154 /// reference this entry.
160 CPEntry(MachineInstr *cpemi, unsigned cpi, unsigned rc = 0)
161 : CPEMI(cpemi), CPI(cpi), RefCount(rc) {}
164 /// CPEntries - Keep track of all of the constant pool entry machine
165 /// instructions. For each original constpool index (i.e. those that existed
166 /// upon entry to this pass), it keeps a vector of entries. Original
167 /// elements are cloned as we go along; the clones are put in the vector of
168 /// the original element, but have distinct CPIs.
170 /// The first half of CPEntries contains generic constants, the second half
171 /// contains jump tables. Use getCombinedIndex on a generic CPEMI to look up
172 /// which vector it will be in here.
173 std::vector<std::vector<CPEntry>> CPEntries;
175 /// Maps a JT index to the offset in CPEntries containing copies of that
176 /// table. The equivalent map for a CONSTPOOL_ENTRY is the identity.
177 DenseMap<int, int> JumpTableEntryIndices;
179 /// Maps a JT index to the LEA that actually uses the index to calculate its
181 DenseMap<int, int> JumpTableUserIndices;
183 /// ImmBranch - One per immediate branch, keeping the machine instruction
184 /// pointer, conditional or unconditional, the max displacement,
185 /// and (if isCond is true) the corresponding unconditional branch
189 unsigned MaxDisp : 31;
193 ImmBranch(MachineInstr *mi, unsigned maxdisp, bool cond, unsigned ubr)
194 : MI(mi), MaxDisp(maxdisp), isCond(cond), UncondBr(ubr) {}
197 /// ImmBranches - Keep track of all the immediate branch instructions.
199 std::vector<ImmBranch> ImmBranches;
201 /// PushPopMIs - Keep track of all the Thumb push / pop instructions.
203 SmallVector<MachineInstr*, 4> PushPopMIs;
205 /// T2JumpTables - Keep track of all the Thumb2 jumptable instructions.
206 SmallVector<MachineInstr*, 4> T2JumpTables;
208 /// HasFarJump - True if any far jump instruction has been emitted during
209 /// the branch fix up pass.
213 MachineConstantPool *MCP;
214 const ARMBaseInstrInfo *TII;
215 const ARMSubtarget *STI;
216 ARMFunctionInfo *AFI;
220 bool isPositionIndependentOrROPI;
225 ARMConstantIslands() : MachineFunctionPass(ID) {}
227 bool runOnMachineFunction(MachineFunction &MF) override;
229 MachineFunctionProperties getRequiredProperties() const override {
230 return MachineFunctionProperties().set(
231 MachineFunctionProperties::Property::NoVRegs);
234 StringRef getPassName() const override {
235 return ARM_CP_ISLANDS_OPT_NAME;
239 void doInitialConstPlacement(std::vector<MachineInstr *> &CPEMIs);
240 void doInitialJumpTablePlacement(std::vector<MachineInstr *> &CPEMIs);
241 bool BBHasFallthrough(MachineBasicBlock *MBB);
242 CPEntry *findConstPoolEntry(unsigned CPI, const MachineInstr *CPEMI);
243 unsigned getCPELogAlign(const MachineInstr *CPEMI);
244 void scanFunctionJumpTables();
245 void initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs);
246 MachineBasicBlock *splitBlockBeforeInstr(MachineInstr *MI);
247 void updateForInsertedWaterBlock(MachineBasicBlock *NewBB);
248 void adjustBBOffsetsAfter(MachineBasicBlock *BB);
249 bool decrementCPEReferenceCount(unsigned CPI, MachineInstr* CPEMI);
250 unsigned getCombinedIndex(const MachineInstr *CPEMI);
251 int findInRangeCPEntry(CPUser& U, unsigned UserOffset);
252 bool findAvailableWater(CPUser&U, unsigned UserOffset,
253 water_iterator &WaterIter, bool CloserWater);
254 void createNewWater(unsigned CPUserIndex, unsigned UserOffset,
255 MachineBasicBlock *&NewMBB);
256 bool handleConstantPoolUser(unsigned CPUserIndex, bool CloserWater);
257 void removeDeadCPEMI(MachineInstr *CPEMI);
258 bool removeUnusedCPEntries();
259 bool isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
260 MachineInstr *CPEMI, unsigned Disp, bool NegOk,
261 bool DoDump = false);
262 bool isWaterInRange(unsigned UserOffset, MachineBasicBlock *Water,
263 CPUser &U, unsigned &Growth);
264 bool isBBInRange(MachineInstr *MI, MachineBasicBlock *BB, unsigned Disp);
265 bool fixupImmediateBr(ImmBranch &Br);
266 bool fixupConditionalBr(ImmBranch &Br);
267 bool fixupUnconditionalBr(ImmBranch &Br);
268 bool undoLRSpillRestore();
269 bool optimizeThumb2Instructions();
270 bool optimizeThumb2Branches();
271 bool reorderThumb2JumpTables();
272 bool preserveBaseRegister(MachineInstr *JumpMI, MachineInstr *LEAMI,
273 unsigned &DeadSize, bool &CanDeleteLEA,
275 bool optimizeThumb2JumpTables();
276 MachineBasicBlock *adjustJTTargetBlockForward(MachineBasicBlock *BB,
277 MachineBasicBlock *JTBB);
279 unsigned getOffsetOf(MachineInstr *MI) const;
280 unsigned getUserOffset(CPUser&) const;
284 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
285 unsigned Disp, bool NegativeOK, bool IsSoImm = false);
286 bool isOffsetInRange(unsigned UserOffset, unsigned TrialOffset,
288 return isOffsetInRange(UserOffset, TrialOffset,
289 U.getMaxDisp(), U.NegOk, U.IsSoImm);
293 char ARMConstantIslands::ID = 0;
295 } // end anonymous namespace
297 /// verify - check BBOffsets, BBSizes, alignment of islands
298 void ARMConstantIslands::verify() {
300 assert(std::is_sorted(MF->begin(), MF->end(),
301 [this](const MachineBasicBlock &LHS,
302 const MachineBasicBlock &RHS) {
303 return BBInfo[LHS.getNumber()].postOffset() <
304 BBInfo[RHS.getNumber()].postOffset();
306 DEBUG(dbgs() << "Verifying " << CPUsers.size() << " CP users.\n");
307 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
308 CPUser &U = CPUsers[i];
309 unsigned UserOffset = getUserOffset(U);
310 // Verify offset using the real max displacement without the safety
312 if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, U.getMaxDisp()+2, U.NegOk,
313 /* DoDump = */ true)) {
314 DEBUG(dbgs() << "OK\n");
317 DEBUG(dbgs() << "Out of range.\n");
320 llvm_unreachable("Constant pool entry out of range!");
325 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
326 /// print block size and offset information - debugging
327 LLVM_DUMP_METHOD void ARMConstantIslands::dumpBBs() {
329 for (unsigned J = 0, E = BBInfo.size(); J !=E; ++J) {
330 const BasicBlockInfo &BBI = BBInfo[J];
331 dbgs() << format("%08x BB#%u\t", BBI.Offset, J)
332 << " kb=" << unsigned(BBI.KnownBits)
333 << " ua=" << unsigned(BBI.Unalign)
334 << " pa=" << unsigned(BBI.PostAlign)
335 << format(" size=%#x\n", BBInfo[J].Size);
341 bool ARMConstantIslands::runOnMachineFunction(MachineFunction &mf) {
343 MCP = mf.getConstantPool();
345 DEBUG(dbgs() << "***** ARMConstantIslands: "
346 << MCP->getConstants().size() << " CP entries, aligned to "
347 << MCP->getConstantPoolAlignment() << " bytes *****\n");
349 STI = &static_cast<const ARMSubtarget &>(MF->getSubtarget());
350 TII = STI->getInstrInfo();
351 isPositionIndependentOrROPI =
352 STI->getTargetLowering()->isPositionIndependent() || STI->isROPI();
353 AFI = MF->getInfo<ARMFunctionInfo>();
355 isThumb = AFI->isThumbFunction();
356 isThumb1 = AFI->isThumb1OnlyFunction();
357 isThumb2 = AFI->isThumb2Function();
360 bool GenerateTBB = isThumb2 || (isThumb1 && SynthesizeThumb1TBB);
362 // This pass invalidates liveness information when it splits basic blocks.
363 MF->getRegInfo().invalidateLiveness();
365 // Renumber all of the machine basic blocks in the function, guaranteeing that
366 // the numbers agree with the position of the block in the function.
367 MF->RenumberBlocks();
369 // Try to reorder and otherwise adjust the block layout to make good use
370 // of the TB[BH] instructions.
371 bool MadeChange = false;
372 if (GenerateTBB && AdjustJumpTableBlocks) {
373 scanFunctionJumpTables();
374 MadeChange |= reorderThumb2JumpTables();
375 // Data is out of date, so clear it. It'll be re-computed later.
376 T2JumpTables.clear();
377 // Blocks may have shifted around. Keep the numbering up to date.
378 MF->RenumberBlocks();
381 // Perform the initial placement of the constant pool entries. To start with,
382 // we put them all at the end of the function.
383 std::vector<MachineInstr*> CPEMIs;
385 doInitialConstPlacement(CPEMIs);
387 if (MF->getJumpTableInfo())
388 doInitialJumpTablePlacement(CPEMIs);
390 /// The next UID to take is the first unused one.
391 AFI->initPICLabelUId(CPEMIs.size());
393 // Do the initial scan of the function, building up information about the
394 // sizes of each block, the location of all the water, and finding all of the
395 // constant pool users.
396 initializeFunctionInfo(CPEMIs);
400 // Functions with jump tables need an alignment of 4 because they use the ADR
401 // instruction, which aligns the PC to 4 bytes before adding an offset.
402 if (!T2JumpTables.empty())
403 MF->ensureAlignment(2);
405 /// Remove dead constant pool entries.
406 MadeChange |= removeUnusedCPEntries();
408 // Iteratively place constant pool entries and fix up branches until there
410 unsigned NoCPIters = 0, NoBRIters = 0;
412 DEBUG(dbgs() << "Beginning CP iteration #" << NoCPIters << '\n');
413 bool CPChange = false;
414 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i)
415 // For most inputs, it converges in no more than 5 iterations.
416 // If it doesn't end in 10, the input may have huge BB or many CPEs.
417 // In this case, we will try different heuristics.
418 CPChange |= handleConstantPoolUser(i, NoCPIters >= CPMaxIteration / 2);
419 if (CPChange && ++NoCPIters > CPMaxIteration)
420 report_fatal_error("Constant Island pass failed to converge!");
423 // Clear NewWaterList now. If we split a block for branches, it should
424 // appear as "new water" for the next iteration of constant pool placement.
425 NewWaterList.clear();
427 DEBUG(dbgs() << "Beginning BR iteration #" << NoBRIters << '\n');
428 bool BRChange = false;
429 for (unsigned i = 0, e = ImmBranches.size(); i != e; ++i)
430 BRChange |= fixupImmediateBr(ImmBranches[i]);
431 if (BRChange && ++NoBRIters > 30)
432 report_fatal_error("Branch Fix Up pass failed to converge!");
435 if (!CPChange && !BRChange)
440 // Shrink 32-bit Thumb2 load and store instructions.
441 if (isThumb2 && !STI->prefers32BitThumb())
442 MadeChange |= optimizeThumb2Instructions();
444 // Shrink 32-bit branch instructions.
445 if (isThumb && STI->hasV8MBaselineOps())
446 MadeChange |= optimizeThumb2Branches();
448 // Optimize jump tables using TBB / TBH.
449 if (GenerateTBB && !STI->genExecuteOnly())
450 MadeChange |= optimizeThumb2JumpTables();
452 // After a while, this might be made debug-only, but it is not expensive.
455 // If LR has been forced spilled and no far jump (i.e. BL) has been issued,
456 // undo the spill / restore of LR if possible.
457 if (isThumb && !HasFarJump && AFI->isLRSpilledForFarJump())
458 MadeChange |= undoLRSpillRestore();
460 // Save the mapping between original and cloned constpool entries.
461 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
462 for (unsigned j = 0, je = CPEntries[i].size(); j != je; ++j) {
463 const CPEntry & CPE = CPEntries[i][j];
464 if (CPE.CPEMI && CPE.CPEMI->getOperand(1).isCPI())
465 AFI->recordCPEClone(i, CPE.CPI);
469 DEBUG(dbgs() << '\n'; dumpBBs());
475 JumpTableEntryIndices.clear();
476 JumpTableUserIndices.clear();
479 T2JumpTables.clear();
484 /// \brief Perform the initial placement of the regular constant pool entries.
485 /// To start with, we put them all at the end of the function.
487 ARMConstantIslands::doInitialConstPlacement(std::vector<MachineInstr*> &CPEMIs) {
488 // Create the basic block to hold the CPE's.
489 MachineBasicBlock *BB = MF->CreateMachineBasicBlock();
492 // MachineConstantPool measures alignment in bytes. We measure in log2(bytes).
493 unsigned MaxAlign = Log2_32(MCP->getConstantPoolAlignment());
495 // Mark the basic block as required by the const-pool.
496 BB->setAlignment(MaxAlign);
498 // The function needs to be as aligned as the basic blocks. The linker may
499 // move functions around based on their alignment.
500 MF->ensureAlignment(BB->getAlignment());
502 // Order the entries in BB by descending alignment. That ensures correct
503 // alignment of all entries as long as BB is sufficiently aligned. Keep
504 // track of the insertion point for each alignment. We are going to bucket
505 // sort the entries as they are created.
506 SmallVector<MachineBasicBlock::iterator, 8> InsPoint(MaxAlign + 1, BB->end());
508 // Add all of the constants from the constant pool to the end block, use an
509 // identity mapping of CPI's to CPE's.
510 const std::vector<MachineConstantPoolEntry> &CPs = MCP->getConstants();
512 const DataLayout &TD = MF->getDataLayout();
513 for (unsigned i = 0, e = CPs.size(); i != e; ++i) {
514 unsigned Size = TD.getTypeAllocSize(CPs[i].getType());
515 assert(Size >= 4 && "Too small constant pool entry");
516 unsigned Align = CPs[i].getAlignment();
517 assert(isPowerOf2_32(Align) && "Invalid alignment");
518 // Verify that all constant pool entries are a multiple of their alignment.
519 // If not, we would have to pad them out so that instructions stay aligned.
520 assert((Size % Align) == 0 && "CP Entry not multiple of 4 bytes!");
522 // Insert CONSTPOOL_ENTRY before entries with a smaller alignment.
523 unsigned LogAlign = Log2_32(Align);
524 MachineBasicBlock::iterator InsAt = InsPoint[LogAlign];
525 MachineInstr *CPEMI =
526 BuildMI(*BB, InsAt, DebugLoc(), TII->get(ARM::CONSTPOOL_ENTRY))
527 .addImm(i).addConstantPoolIndex(i).addImm(Size);
528 CPEMIs.push_back(CPEMI);
530 // Ensure that future entries with higher alignment get inserted before
531 // CPEMI. This is bucket sort with iterators.
532 for (unsigned a = LogAlign + 1; a <= MaxAlign; ++a)
533 if (InsPoint[a] == InsAt)
536 // Add a new CPEntry, but no corresponding CPUser yet.
537 CPEntries.emplace_back(1, CPEntry(CPEMI, i));
539 DEBUG(dbgs() << "Moved CPI#" << i << " to end of function, size = "
540 << Size << ", align = " << Align <<'\n');
545 /// \brief Do initial placement of the jump tables. Because Thumb2's TBB and TBH
546 /// instructions can be made more efficient if the jump table immediately
547 /// follows the instruction, it's best to place them immediately next to their
548 /// jumps to begin with. In almost all cases they'll never be moved from that
550 void ARMConstantIslands::doInitialJumpTablePlacement(
551 std::vector<MachineInstr *> &CPEMIs) {
552 unsigned i = CPEntries.size();
553 auto MJTI = MF->getJumpTableInfo();
554 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
556 MachineBasicBlock *LastCorrectlyNumberedBB = nullptr;
557 for (MachineBasicBlock &MBB : *MF) {
558 auto MI = MBB.getLastNonDebugInstr();
563 switch (MI->getOpcode()) {
570 JTOpcode = ARM::JUMPTABLE_ADDRS;
573 JTOpcode = ARM::JUMPTABLE_INSTS;
577 JTOpcode = ARM::JUMPTABLE_TBB;
581 JTOpcode = ARM::JUMPTABLE_TBH;
585 unsigned NumOps = MI->getDesc().getNumOperands();
586 MachineOperand JTOp =
587 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1));
588 unsigned JTI = JTOp.getIndex();
589 unsigned Size = JT[JTI].MBBs.size() * sizeof(uint32_t);
590 MachineBasicBlock *JumpTableBB = MF->CreateMachineBasicBlock();
591 MF->insert(std::next(MachineFunction::iterator(MBB)), JumpTableBB);
592 MachineInstr *CPEMI = BuildMI(*JumpTableBB, JumpTableBB->begin(),
593 DebugLoc(), TII->get(JTOpcode))
595 .addJumpTableIndex(JTI)
597 CPEMIs.push_back(CPEMI);
598 CPEntries.emplace_back(1, CPEntry(CPEMI, JTI));
599 JumpTableEntryIndices.insert(std::make_pair(JTI, CPEntries.size() - 1));
600 if (!LastCorrectlyNumberedBB)
601 LastCorrectlyNumberedBB = &MBB;
604 // If we did anything then we need to renumber the subsequent blocks.
605 if (LastCorrectlyNumberedBB)
606 MF->RenumberBlocks(LastCorrectlyNumberedBB);
609 /// BBHasFallthrough - Return true if the specified basic block can fallthrough
610 /// into the block immediately after it.
611 bool ARMConstantIslands::BBHasFallthrough(MachineBasicBlock *MBB) {
612 // Get the next machine basic block in the function.
613 MachineFunction::iterator MBBI = MBB->getIterator();
614 // Can't fall off end of function.
615 if (std::next(MBBI) == MBB->getParent()->end())
618 MachineBasicBlock *NextBB = &*std::next(MBBI);
619 if (!MBB->isSuccessor(NextBB))
622 // Try to analyze the end of the block. A potential fallthrough may already
623 // have an unconditional branch for whatever reason.
624 MachineBasicBlock *TBB, *FBB;
625 SmallVector<MachineOperand, 4> Cond;
626 bool TooDifficult = TII->analyzeBranch(*MBB, TBB, FBB, Cond);
627 return TooDifficult || FBB == nullptr;
630 /// findConstPoolEntry - Given the constpool index and CONSTPOOL_ENTRY MI,
631 /// look up the corresponding CPEntry.
632 ARMConstantIslands::CPEntry
633 *ARMConstantIslands::findConstPoolEntry(unsigned CPI,
634 const MachineInstr *CPEMI) {
635 std::vector<CPEntry> &CPEs = CPEntries[CPI];
636 // Number of entries per constpool index should be small, just do a
638 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
639 if (CPEs[i].CPEMI == CPEMI)
645 /// getCPELogAlign - Returns the required alignment of the constant pool entry
646 /// represented by CPEMI. Alignment is measured in log2(bytes) units.
647 unsigned ARMConstantIslands::getCPELogAlign(const MachineInstr *CPEMI) {
648 switch (CPEMI->getOpcode()) {
649 case ARM::CONSTPOOL_ENTRY:
651 case ARM::JUMPTABLE_TBB:
652 return isThumb1 ? 2 : 0;
653 case ARM::JUMPTABLE_TBH:
654 return isThumb1 ? 2 : 1;
655 case ARM::JUMPTABLE_INSTS:
657 case ARM::JUMPTABLE_ADDRS:
660 llvm_unreachable("unknown constpool entry kind");
663 unsigned CPI = getCombinedIndex(CPEMI);
664 assert(CPI < MCP->getConstants().size() && "Invalid constant pool index.");
665 unsigned Align = MCP->getConstants()[CPI].getAlignment();
666 assert(isPowerOf2_32(Align) && "Invalid CPE alignment");
667 return Log2_32(Align);
670 /// scanFunctionJumpTables - Do a scan of the function, building up
671 /// information about the sizes of each block and the locations of all
673 void ARMConstantIslands::scanFunctionJumpTables() {
674 for (MachineBasicBlock &MBB : *MF) {
675 for (MachineInstr &I : MBB)
677 (I.getOpcode() == ARM::t2BR_JT || I.getOpcode() == ARM::tBR_JTr))
678 T2JumpTables.push_back(&I);
682 /// initializeFunctionInfo - Do the initial scan of the function, building up
683 /// information about the sizes of each block, the location of all the water,
684 /// and finding all of the constant pool users.
685 void ARMConstantIslands::
686 initializeFunctionInfo(const std::vector<MachineInstr*> &CPEMIs) {
688 BBInfo = computeAllBlockSizes(MF);
690 // The known bits of the entry block offset are determined by the function
692 BBInfo.front().KnownBits = MF->getAlignment();
694 // Compute block offsets and known bits.
695 adjustBBOffsetsAfter(&MF->front());
697 // Now go back through the instructions and build up our data structures.
698 for (MachineBasicBlock &MBB : *MF) {
699 // If this block doesn't fall through into the next MBB, then this is
700 // 'water' that a constant pool island could be placed.
701 if (!BBHasFallthrough(&MBB))
702 WaterList.push_back(&MBB);
704 for (MachineInstr &I : MBB) {
705 if (I.isDebugValue())
708 unsigned Opc = I.getOpcode();
716 continue; // Ignore other JT branches
719 T2JumpTables.push_back(&I);
720 continue; // Does not get an entry in ImmBranches
751 // Record this immediate branch.
752 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
753 ImmBranches.push_back(ImmBranch(&I, MaxOffs, isCond, UOpc));
756 if (Opc == ARM::tPUSH || Opc == ARM::tPOP_RET)
757 PushPopMIs.push_back(&I);
759 if (Opc == ARM::CONSTPOOL_ENTRY || Opc == ARM::JUMPTABLE_ADDRS ||
760 Opc == ARM::JUMPTABLE_INSTS || Opc == ARM::JUMPTABLE_TBB ||
761 Opc == ARM::JUMPTABLE_TBH)
764 // Scan the instructions for constant pool operands.
765 for (unsigned op = 0, e = I.getNumOperands(); op != e; ++op)
766 if (I.getOperand(op).isCPI() || I.getOperand(op).isJTI()) {
767 // We found one. The addressing mode tells us the max displacement
768 // from the PC that this instruction permits.
770 // Basic size info comes from the TSFlags field.
774 bool IsSoImm = false;
778 llvm_unreachable("Unknown addressing mode for CP reference!");
780 // Taking the address of a CP entry.
782 case ARM::LEApcrelJT:
783 // This takes a SoImm, which is 8 bit immediate rotated. We'll
784 // pretend the maximum offset is 255 * 4. Since each instruction
785 // 4 byte wide, this is always correct. We'll check for other
786 // displacements that fits in a SoImm as well.
792 case ARM::t2LEApcrel:
793 case ARM::t2LEApcrelJT:
798 case ARM::tLEApcrelJT:
809 Bits = 12; // +-offset_12
815 Scale = 4; // +(offset_8*4)
821 Scale = 4; // +-(offset_8*4)
827 Scale = 2; // +(offset_5*2)
831 // Remember that this is a user of a CP entry.
832 unsigned CPI = I.getOperand(op).getIndex();
833 if (I.getOperand(op).isJTI()) {
834 JumpTableUserIndices.insert(std::make_pair(CPI, CPUsers.size()));
835 CPI = JumpTableEntryIndices[CPI];
838 MachineInstr *CPEMI = CPEMIs[CPI];
839 unsigned MaxOffs = ((1 << Bits)-1) * Scale;
840 CPUsers.push_back(CPUser(&I, CPEMI, MaxOffs, NegOk, IsSoImm));
842 // Increment corresponding CPEntry reference count.
843 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
844 assert(CPE && "Cannot find a corresponding CPEntry!");
847 // Instructions can only use one CP entry, don't bother scanning the
848 // rest of the operands.
855 /// getOffsetOf - Return the current offset of the specified machine instruction
856 /// from the start of the function. This offset changes as stuff is moved
857 /// around inside the function.
858 unsigned ARMConstantIslands::getOffsetOf(MachineInstr *MI) const {
859 MachineBasicBlock *MBB = MI->getParent();
861 // The offset is composed of two things: the sum of the sizes of all MBB's
862 // before this instruction's block, and the offset from the start of the block
864 unsigned Offset = BBInfo[MBB->getNumber()].Offset;
866 // Sum instructions before MI in MBB.
867 for (MachineBasicBlock::iterator I = MBB->begin(); &*I != MI; ++I) {
868 assert(I != MBB->end() && "Didn't find MI in its own basic block?");
869 Offset += TII->getInstSizeInBytes(*I);
874 /// CompareMBBNumbers - Little predicate function to sort the WaterList by MBB
876 static bool CompareMBBNumbers(const MachineBasicBlock *LHS,
877 const MachineBasicBlock *RHS) {
878 return LHS->getNumber() < RHS->getNumber();
881 /// updateForInsertedWaterBlock - When a block is newly inserted into the
882 /// machine function, it upsets all of the block numbers. Renumber the blocks
883 /// and update the arrays that parallel this numbering.
884 void ARMConstantIslands::updateForInsertedWaterBlock(MachineBasicBlock *NewBB) {
885 // Renumber the MBB's to keep them consecutive.
886 NewBB->getParent()->RenumberBlocks(NewBB);
888 // Insert an entry into BBInfo to align it properly with the (newly
889 // renumbered) block numbers.
890 BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
892 // Next, update WaterList. Specifically, we need to add NewMBB as having
893 // available water after it.
895 std::lower_bound(WaterList.begin(), WaterList.end(), NewBB,
897 WaterList.insert(IP, NewBB);
900 /// Split the basic block containing MI into two blocks, which are joined by
901 /// an unconditional branch. Update data structures and renumber blocks to
902 /// account for this change and returns the newly created block.
903 MachineBasicBlock *ARMConstantIslands::splitBlockBeforeInstr(MachineInstr *MI) {
904 MachineBasicBlock *OrigBB = MI->getParent();
906 // Create a new MBB for the code after the OrigBB.
907 MachineBasicBlock *NewBB =
908 MF->CreateMachineBasicBlock(OrigBB->getBasicBlock());
909 MachineFunction::iterator MBBI = ++OrigBB->getIterator();
910 MF->insert(MBBI, NewBB);
912 // Splice the instructions starting with MI over to NewBB.
913 NewBB->splice(NewBB->end(), OrigBB, MI, OrigBB->end());
915 // Add an unconditional branch from OrigBB to NewBB.
916 // Note the new unconditional branch is not being recorded.
917 // There doesn't seem to be meaningful DebugInfo available; this doesn't
918 // correspond to anything in the source.
919 unsigned Opc = isThumb ? (isThumb2 ? ARM::t2B : ARM::tB) : ARM::B;
921 BuildMI(OrigBB, DebugLoc(), TII->get(Opc)).addMBB(NewBB);
923 BuildMI(OrigBB, DebugLoc(), TII->get(Opc))
925 .add(predOps(ARMCC::AL));
928 // Update the CFG. All succs of OrigBB are now succs of NewBB.
929 NewBB->transferSuccessors(OrigBB);
931 // OrigBB branches to NewBB.
932 OrigBB->addSuccessor(NewBB);
934 // Update internal data structures to account for the newly inserted MBB.
935 // This is almost the same as updateForInsertedWaterBlock, except that
936 // the Water goes after OrigBB, not NewBB.
937 MF->RenumberBlocks(NewBB);
939 // Insert an entry into BBInfo to align it properly with the (newly
940 // renumbered) block numbers.
941 BBInfo.insert(BBInfo.begin() + NewBB->getNumber(), BasicBlockInfo());
943 // Next, update WaterList. Specifically, we need to add OrigMBB as having
944 // available water after it (but not if it's already there, which happens
945 // when splitting before a conditional branch that is followed by an
946 // unconditional branch - in that case we want to insert NewBB).
948 std::lower_bound(WaterList.begin(), WaterList.end(), OrigBB,
950 MachineBasicBlock* WaterBB = *IP;
951 if (WaterBB == OrigBB)
952 WaterList.insert(std::next(IP), NewBB);
954 WaterList.insert(IP, OrigBB);
955 NewWaterList.insert(OrigBB);
957 // Figure out how large the OrigBB is. As the first half of the original
958 // block, it cannot contain a tablejump. The size includes
959 // the new jump we added. (It should be possible to do this without
960 // recounting everything, but it's very confusing, and this is rarely
962 computeBlockSize(MF, OrigBB, BBInfo[OrigBB->getNumber()]);
964 // Figure out how large the NewMBB is. As the second half of the original
965 // block, it may contain a tablejump.
966 computeBlockSize(MF, NewBB, BBInfo[NewBB->getNumber()]);
968 // All BBOffsets following these blocks must be modified.
969 adjustBBOffsetsAfter(OrigBB);
974 /// getUserOffset - Compute the offset of U.MI as seen by the hardware
975 /// displacement computation. Update U.KnownAlignment to match its current
976 /// basic block location.
977 unsigned ARMConstantIslands::getUserOffset(CPUser &U) const {
978 unsigned UserOffset = getOffsetOf(U.MI);
979 const BasicBlockInfo &BBI = BBInfo[U.MI->getParent()->getNumber()];
980 unsigned KnownBits = BBI.internalKnownBits();
982 // The value read from PC is offset from the actual instruction address.
983 UserOffset += (isThumb ? 4 : 8);
985 // Because of inline assembly, we may not know the alignment (mod 4) of U.MI.
986 // Make sure U.getMaxDisp() returns a constrained range.
987 U.KnownAlignment = (KnownBits >= 2);
989 // On Thumb, offsets==2 mod 4 are rounded down by the hardware for
990 // purposes of the displacement computation; compensate for that here.
991 // For unknown alignments, getMaxDisp() constrains the range instead.
992 if (isThumb && U.KnownAlignment)
998 /// isOffsetInRange - Checks whether UserOffset (the location of a constant pool
999 /// reference) is within MaxDisp of TrialOffset (a proposed location of a
1000 /// constant pool entry).
1001 /// UserOffset is computed by getUserOffset above to include PC adjustments. If
1002 /// the mod 4 alignment of UserOffset is not known, the uncertainty must be
1003 /// subtracted from MaxDisp instead. CPUser::getMaxDisp() does that.
1004 bool ARMConstantIslands::isOffsetInRange(unsigned UserOffset,
1005 unsigned TrialOffset, unsigned MaxDisp,
1006 bool NegativeOK, bool IsSoImm) {
1007 if (UserOffset <= TrialOffset) {
1008 // User before the Trial.
1009 if (TrialOffset - UserOffset <= MaxDisp)
1011 // FIXME: Make use full range of soimm values.
1012 } else if (NegativeOK) {
1013 if (UserOffset - TrialOffset <= MaxDisp)
1015 // FIXME: Make use full range of soimm values.
1020 /// isWaterInRange - Returns true if a CPE placed after the specified
1021 /// Water (a basic block) will be in range for the specific MI.
1023 /// Compute how much the function will grow by inserting a CPE after Water.
1024 bool ARMConstantIslands::isWaterInRange(unsigned UserOffset,
1025 MachineBasicBlock* Water, CPUser &U,
1027 unsigned CPELogAlign = getCPELogAlign(U.CPEMI);
1028 unsigned CPEOffset = BBInfo[Water->getNumber()].postOffset(CPELogAlign);
1029 unsigned NextBlockOffset, NextBlockAlignment;
1030 MachineFunction::const_iterator NextBlock = Water->getIterator();
1031 if (++NextBlock == MF->end()) {
1032 NextBlockOffset = BBInfo[Water->getNumber()].postOffset();
1033 NextBlockAlignment = 0;
1035 NextBlockOffset = BBInfo[NextBlock->getNumber()].Offset;
1036 NextBlockAlignment = NextBlock->getAlignment();
1038 unsigned Size = U.CPEMI->getOperand(2).getImm();
1039 unsigned CPEEnd = CPEOffset + Size;
1041 // The CPE may be able to hide in the alignment padding before the next
1042 // block. It may also cause more padding to be required if it is more aligned
1043 // that the next block.
1044 if (CPEEnd > NextBlockOffset) {
1045 Growth = CPEEnd - NextBlockOffset;
1046 // Compute the padding that would go at the end of the CPE to align the next
1048 Growth += OffsetToAlignment(CPEEnd, 1ULL << NextBlockAlignment);
1050 // If the CPE is to be inserted before the instruction, that will raise
1051 // the offset of the instruction. Also account for unknown alignment padding
1052 // in blocks between CPE and the user.
1053 if (CPEOffset < UserOffset)
1054 UserOffset += Growth + UnknownPadding(MF->getAlignment(), CPELogAlign);
1056 // CPE fits in existing padding.
1059 return isOffsetInRange(UserOffset, CPEOffset, U);
1062 /// isCPEntryInRange - Returns true if the distance between specific MI and
1063 /// specific ConstPool entry instruction can fit in MI's displacement field.
1064 bool ARMConstantIslands::isCPEntryInRange(MachineInstr *MI, unsigned UserOffset,
1065 MachineInstr *CPEMI, unsigned MaxDisp,
1066 bool NegOk, bool DoDump) {
1067 unsigned CPEOffset = getOffsetOf(CPEMI);
1071 unsigned Block = MI->getParent()->getNumber();
1072 const BasicBlockInfo &BBI = BBInfo[Block];
1073 dbgs() << "User of CPE#" << CPEMI->getOperand(0).getImm()
1074 << " max delta=" << MaxDisp
1075 << format(" insn address=%#x", UserOffset)
1076 << " in BB#" << Block << ": "
1077 << format("%#x-%x\t", BBI.Offset, BBI.postOffset()) << *MI
1078 << format("CPE address=%#x offset=%+d: ", CPEOffset,
1079 int(CPEOffset-UserOffset));
1083 return isOffsetInRange(UserOffset, CPEOffset, MaxDisp, NegOk);
1087 /// BBIsJumpedOver - Return true of the specified basic block's only predecessor
1088 /// unconditionally branches to its only successor.
1089 static bool BBIsJumpedOver(MachineBasicBlock *MBB) {
1090 if (MBB->pred_size() != 1 || MBB->succ_size() != 1)
1093 MachineBasicBlock *Succ = *MBB->succ_begin();
1094 MachineBasicBlock *Pred = *MBB->pred_begin();
1095 MachineInstr *PredMI = &Pred->back();
1096 if (PredMI->getOpcode() == ARM::B || PredMI->getOpcode() == ARM::tB
1097 || PredMI->getOpcode() == ARM::t2B)
1098 return PredMI->getOperand(0).getMBB() == Succ;
1103 void ARMConstantIslands::adjustBBOffsetsAfter(MachineBasicBlock *BB) {
1104 unsigned BBNum = BB->getNumber();
1105 for(unsigned i = BBNum + 1, e = MF->getNumBlockIDs(); i < e; ++i) {
1106 // Get the offset and known bits at the end of the layout predecessor.
1107 // Include the alignment of the current block.
1108 unsigned LogAlign = MF->getBlockNumbered(i)->getAlignment();
1109 unsigned Offset = BBInfo[i - 1].postOffset(LogAlign);
1110 unsigned KnownBits = BBInfo[i - 1].postKnownBits(LogAlign);
1112 // This is where block i begins. Stop if the offset is already correct,
1113 // and we have updated 2 blocks. This is the maximum number of blocks
1114 // changed before calling this function.
1115 if (i > BBNum + 2 &&
1116 BBInfo[i].Offset == Offset &&
1117 BBInfo[i].KnownBits == KnownBits)
1120 BBInfo[i].Offset = Offset;
1121 BBInfo[i].KnownBits = KnownBits;
1125 /// decrementCPEReferenceCount - find the constant pool entry with index CPI
1126 /// and instruction CPEMI, and decrement its refcount. If the refcount
1127 /// becomes 0 remove the entry and instruction. Returns true if we removed
1128 /// the entry, false if we didn't.
1130 bool ARMConstantIslands::decrementCPEReferenceCount(unsigned CPI,
1131 MachineInstr *CPEMI) {
1132 // Find the old entry. Eliminate it if it is no longer used.
1133 CPEntry *CPE = findConstPoolEntry(CPI, CPEMI);
1134 assert(CPE && "Unexpected!");
1135 if (--CPE->RefCount == 0) {
1136 removeDeadCPEMI(CPEMI);
1137 CPE->CPEMI = nullptr;
1144 unsigned ARMConstantIslands::getCombinedIndex(const MachineInstr *CPEMI) {
1145 if (CPEMI->getOperand(1).isCPI())
1146 return CPEMI->getOperand(1).getIndex();
1148 return JumpTableEntryIndices[CPEMI->getOperand(1).getIndex()];
1151 /// LookForCPEntryInRange - see if the currently referenced CPE is in range;
1152 /// if not, see if an in-range clone of the CPE is in range, and if so,
1153 /// change the data structures so the user references the clone. Returns:
1154 /// 0 = no existing entry found
1155 /// 1 = entry found, and there were no code insertions or deletions
1156 /// 2 = entry found, and there were code insertions or deletions
1157 int ARMConstantIslands::findInRangeCPEntry(CPUser& U, unsigned UserOffset)
1159 MachineInstr *UserMI = U.MI;
1160 MachineInstr *CPEMI = U.CPEMI;
1162 // Check to see if the CPE is already in-range.
1163 if (isCPEntryInRange(UserMI, UserOffset, CPEMI, U.getMaxDisp(), U.NegOk,
1165 DEBUG(dbgs() << "In range\n");
1169 // No. Look for previously created clones of the CPE that are in range.
1170 unsigned CPI = getCombinedIndex(CPEMI);
1171 std::vector<CPEntry> &CPEs = CPEntries[CPI];
1172 for (unsigned i = 0, e = CPEs.size(); i != e; ++i) {
1173 // We already tried this one
1174 if (CPEs[i].CPEMI == CPEMI)
1176 // Removing CPEs can leave empty entries, skip
1177 if (CPEs[i].CPEMI == nullptr)
1179 if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getMaxDisp(),
1181 DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
1182 << CPEs[i].CPI << "\n");
1183 // Point the CPUser node to the replacement
1184 U.CPEMI = CPEs[i].CPEMI;
1185 // Change the CPI in the instruction operand to refer to the clone.
1186 for (unsigned j = 0, e = UserMI->getNumOperands(); j != e; ++j)
1187 if (UserMI->getOperand(j).isCPI()) {
1188 UserMI->getOperand(j).setIndex(CPEs[i].CPI);
1191 // Adjust the refcount of the clone...
1193 // ...and the original. If we didn't remove the old entry, none of the
1194 // addresses changed, so we don't need another pass.
1195 return decrementCPEReferenceCount(CPI, CPEMI) ? 2 : 1;
1201 /// getUnconditionalBrDisp - Returns the maximum displacement that can fit in
1202 /// the specific unconditional branch instruction.
1203 static inline unsigned getUnconditionalBrDisp(int Opc) {
1206 return ((1<<10)-1)*2;
1208 return ((1<<23)-1)*2;
1213 return ((1<<23)-1)*4;
1216 /// findAvailableWater - Look for an existing entry in the WaterList in which
1217 /// we can place the CPE referenced from U so it's within range of U's MI.
1218 /// Returns true if found, false if not. If it returns true, WaterIter
1219 /// is set to the WaterList entry. For Thumb, prefer water that will not
1220 /// introduce padding to water that will. To ensure that this pass
1221 /// terminates, the CPE location for a particular CPUser is only allowed to
1222 /// move to a lower address, so search backward from the end of the list and
1223 /// prefer the first water that is in range.
1224 bool ARMConstantIslands::findAvailableWater(CPUser &U, unsigned UserOffset,
1225 water_iterator &WaterIter,
1227 if (WaterList.empty())
1230 unsigned BestGrowth = ~0u;
1231 // The nearest water without splitting the UserBB is right after it.
1232 // If the distance is still large (we have a big BB), then we need to split it
1233 // if we don't converge after certain iterations. This helps the following
1234 // situation to converge:
1239 // When a CP access is out of range, BB0 may be used as water. However,
1240 // inserting islands between BB0 and BB1 makes other accesses out of range.
1241 MachineBasicBlock *UserBB = U.MI->getParent();
1242 unsigned MinNoSplitDisp =
1243 BBInfo[UserBB->getNumber()].postOffset(getCPELogAlign(U.CPEMI));
1244 if (CloserWater && MinNoSplitDisp > U.getMaxDisp() / 2)
1246 for (water_iterator IP = std::prev(WaterList.end()), B = WaterList.begin();;
1248 MachineBasicBlock* WaterBB = *IP;
1249 // Check if water is in range and is either at a lower address than the
1250 // current "high water mark" or a new water block that was created since
1251 // the previous iteration by inserting an unconditional branch. In the
1252 // latter case, we want to allow resetting the high water mark back to
1253 // this new water since we haven't seen it before. Inserting branches
1254 // should be relatively uncommon and when it does happen, we want to be
1255 // sure to take advantage of it for all the CPEs near that block, so that
1256 // we don't insert more branches than necessary.
1257 // When CloserWater is true, we try to find the lowest address after (or
1258 // equal to) user MI's BB no matter of padding growth.
1260 if (isWaterInRange(UserOffset, WaterBB, U, Growth) &&
1261 (WaterBB->getNumber() < U.HighWaterMark->getNumber() ||
1262 NewWaterList.count(WaterBB) || WaterBB == U.MI->getParent()) &&
1263 Growth < BestGrowth) {
1264 // This is the least amount of required padding seen so far.
1265 BestGrowth = Growth;
1267 DEBUG(dbgs() << "Found water after BB#" << WaterBB->getNumber()
1268 << " Growth=" << Growth << '\n');
1270 if (CloserWater && WaterBB == U.MI->getParent())
1272 // Keep looking unless it is perfect and we're not looking for the lowest
1273 // possible address.
1274 if (!CloserWater && BestGrowth == 0)
1280 return BestGrowth != ~0u;
1283 /// createNewWater - No existing WaterList entry will work for
1284 /// CPUsers[CPUserIndex], so create a place to put the CPE. The end of the
1285 /// block is used if in range, and the conditional branch munged so control
1286 /// flow is correct. Otherwise the block is split to create a hole with an
1287 /// unconditional branch around it. In either case NewMBB is set to a
1288 /// block following which the new island can be inserted (the WaterList
1289 /// is not adjusted).
1290 void ARMConstantIslands::createNewWater(unsigned CPUserIndex,
1291 unsigned UserOffset,
1292 MachineBasicBlock *&NewMBB) {
1293 CPUser &U = CPUsers[CPUserIndex];
1294 MachineInstr *UserMI = U.MI;
1295 MachineInstr *CPEMI = U.CPEMI;
1296 unsigned CPELogAlign = getCPELogAlign(CPEMI);
1297 MachineBasicBlock *UserMBB = UserMI->getParent();
1298 const BasicBlockInfo &UserBBI = BBInfo[UserMBB->getNumber()];
1300 // If the block does not end in an unconditional branch already, and if the
1301 // end of the block is within range, make new water there. (The addition
1302 // below is for the unconditional branch we will be adding: 4 bytes on ARM +
1303 // Thumb2, 2 on Thumb1.
1304 if (BBHasFallthrough(UserMBB)) {
1305 // Size of branch to insert.
1306 unsigned Delta = isThumb1 ? 2 : 4;
1307 // Compute the offset where the CPE will begin.
1308 unsigned CPEOffset = UserBBI.postOffset(CPELogAlign) + Delta;
1310 if (isOffsetInRange(UserOffset, CPEOffset, U)) {
1311 DEBUG(dbgs() << "Split at end of BB#" << UserMBB->getNumber()
1312 << format(", expected CPE offset %#x\n", CPEOffset));
1313 NewMBB = &*++UserMBB->getIterator();
1314 // Add an unconditional branch from UserMBB to fallthrough block. Record
1315 // it for branch lengthening; this new branch will not get out of range,
1316 // but if the preceding conditional branch is out of range, the targets
1317 // will be exchanged, and the altered branch may be out of range, so the
1318 // machinery has to know about it.
1319 int UncondBr = isThumb ? ((isThumb2) ? ARM::t2B : ARM::tB) : ARM::B;
1321 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr)).addMBB(NewMBB);
1323 BuildMI(UserMBB, DebugLoc(), TII->get(UncondBr))
1325 .add(predOps(ARMCC::AL));
1326 unsigned MaxDisp = getUnconditionalBrDisp(UncondBr);
1327 ImmBranches.push_back(ImmBranch(&UserMBB->back(),
1328 MaxDisp, false, UncondBr));
1329 computeBlockSize(MF, UserMBB, BBInfo[UserMBB->getNumber()]);
1330 adjustBBOffsetsAfter(UserMBB);
1335 // What a big block. Find a place within the block to split it. This is a
1336 // little tricky on Thumb1 since instructions are 2 bytes and constant pool
1337 // entries are 4 bytes: if instruction I references island CPE, and
1338 // instruction I+1 references CPE', it will not work well to put CPE as far
1339 // forward as possible, since then CPE' cannot immediately follow it (that
1340 // location is 2 bytes farther away from I+1 than CPE was from I) and we'd
1341 // need to create a new island. So, we make a first guess, then walk through
1342 // the instructions between the one currently being looked at and the
1343 // possible insertion point, and make sure any other instructions that
1344 // reference CPEs will be able to use the same island area; if not, we back
1345 // up the insertion point.
1347 // Try to split the block so it's fully aligned. Compute the latest split
1348 // point where we can add a 4-byte branch instruction, and then align to
1349 // LogAlign which is the largest possible alignment in the function.
1350 unsigned LogAlign = MF->getAlignment();
1351 assert(LogAlign >= CPELogAlign && "Over-aligned constant pool entry");
1352 unsigned KnownBits = UserBBI.internalKnownBits();
1353 unsigned UPad = UnknownPadding(LogAlign, KnownBits);
1354 unsigned BaseInsertOffset = UserOffset + U.getMaxDisp() - UPad;
1355 DEBUG(dbgs() << format("Split in middle of big block before %#x",
1358 // The 4 in the following is for the unconditional branch we'll be inserting
1359 // (allows for long branch on Thumb1). Alignment of the island is handled
1360 // inside isOffsetInRange.
1361 BaseInsertOffset -= 4;
1363 DEBUG(dbgs() << format(", adjusted to %#x", BaseInsertOffset)
1364 << " la=" << LogAlign
1365 << " kb=" << KnownBits
1366 << " up=" << UPad << '\n');
1368 // This could point off the end of the block if we've already got constant
1369 // pool entries following this block; only the last one is in the water list.
1370 // Back past any possible branches (allow for a conditional and a maximally
1371 // long unconditional).
1372 if (BaseInsertOffset + 8 >= UserBBI.postOffset()) {
1373 // Ensure BaseInsertOffset is larger than the offset of the instruction
1374 // following UserMI so that the loop which searches for the split point
1375 // iterates at least once.
1377 std::max(UserBBI.postOffset() - UPad - 8,
1378 UserOffset + TII->getInstSizeInBytes(*UserMI) + 1);
1379 DEBUG(dbgs() << format("Move inside block: %#x\n", BaseInsertOffset));
1381 unsigned EndInsertOffset = BaseInsertOffset + 4 + UPad +
1382 CPEMI->getOperand(2).getImm();
1383 MachineBasicBlock::iterator MI = UserMI;
1385 unsigned CPUIndex = CPUserIndex+1;
1386 unsigned NumCPUsers = CPUsers.size();
1387 MachineInstr *LastIT = nullptr;
1388 for (unsigned Offset = UserOffset + TII->getInstSizeInBytes(*UserMI);
1389 Offset < BaseInsertOffset;
1390 Offset += TII->getInstSizeInBytes(*MI), MI = std::next(MI)) {
1391 assert(MI != UserMBB->end() && "Fell off end of block");
1392 if (CPUIndex < NumCPUsers && CPUsers[CPUIndex].MI == &*MI) {
1393 CPUser &U = CPUsers[CPUIndex];
1394 if (!isOffsetInRange(Offset, EndInsertOffset, U)) {
1395 // Shift intertion point by one unit of alignment so it is within reach.
1396 BaseInsertOffset -= 1u << LogAlign;
1397 EndInsertOffset -= 1u << LogAlign;
1399 // This is overly conservative, as we don't account for CPEMIs being
1400 // reused within the block, but it doesn't matter much. Also assume CPEs
1401 // are added in order with alignment padding. We may eventually be able
1402 // to pack the aligned CPEs better.
1403 EndInsertOffset += U.CPEMI->getOperand(2).getImm();
1407 // Remember the last IT instruction.
1408 if (MI->getOpcode() == ARM::t2IT)
1414 // Avoid splitting an IT block.
1416 unsigned PredReg = 0;
1417 ARMCC::CondCodes CC = getITInstrPredicate(*MI, PredReg);
1418 if (CC != ARMCC::AL)
1422 // We really must not split an IT block.
1423 DEBUG(unsigned PredReg;
1424 assert(!isThumb || getITInstrPredicate(*MI, PredReg) == ARMCC::AL));
1426 NewMBB = splitBlockBeforeInstr(&*MI);
1429 /// handleConstantPoolUser - Analyze the specified user, checking to see if it
1430 /// is out-of-range. If so, pick up the constant pool value and move it some
1431 /// place in-range. Return true if we changed any addresses (thus must run
1432 /// another pass of branch lengthening), false otherwise.
1433 bool ARMConstantIslands::handleConstantPoolUser(unsigned CPUserIndex,
1435 CPUser &U = CPUsers[CPUserIndex];
1436 MachineInstr *UserMI = U.MI;
1437 MachineInstr *CPEMI = U.CPEMI;
1438 unsigned CPI = getCombinedIndex(CPEMI);
1439 unsigned Size = CPEMI->getOperand(2).getImm();
1440 // Compute this only once, it's expensive.
1441 unsigned UserOffset = getUserOffset(U);
1443 // See if the current entry is within range, or there is a clone of it
1445 int result = findInRangeCPEntry(U, UserOffset);
1446 if (result==1) return false;
1447 else if (result==2) return true;
1449 // No existing clone of this CPE is within range.
1450 // We will be generating a new clone. Get a UID for it.
1451 unsigned ID = AFI->createPICLabelUId();
1453 // Look for water where we can place this CPE.
1454 MachineBasicBlock *NewIsland = MF->CreateMachineBasicBlock();
1455 MachineBasicBlock *NewMBB;
1457 if (findAvailableWater(U, UserOffset, IP, CloserWater)) {
1458 DEBUG(dbgs() << "Found water in range\n");
1459 MachineBasicBlock *WaterBB = *IP;
1461 // If the original WaterList entry was "new water" on this iteration,
1462 // propagate that to the new island. This is just keeping NewWaterList
1463 // updated to match the WaterList, which will be updated below.
1464 if (NewWaterList.erase(WaterBB))
1465 NewWaterList.insert(NewIsland);
1467 // The new CPE goes before the following block (NewMBB).
1468 NewMBB = &*++WaterBB->getIterator();
1471 DEBUG(dbgs() << "No water found\n");
1472 createNewWater(CPUserIndex, UserOffset, NewMBB);
1474 // splitBlockBeforeInstr adds to WaterList, which is important when it is
1475 // called while handling branches so that the water will be seen on the
1476 // next iteration for constant pools, but in this context, we don't want
1477 // it. Check for this so it will be removed from the WaterList.
1478 // Also remove any entry from NewWaterList.
1479 MachineBasicBlock *WaterBB = &*--NewMBB->getIterator();
1480 IP = find(WaterList, WaterBB);
1481 if (IP != WaterList.end())
1482 NewWaterList.erase(WaterBB);
1484 // We are adding new water. Update NewWaterList.
1485 NewWaterList.insert(NewIsland);
1488 // Remove the original WaterList entry; we want subsequent insertions in
1489 // this vicinity to go after the one we're about to insert. This
1490 // considerably reduces the number of times we have to move the same CPE
1491 // more than once and is also important to ensure the algorithm terminates.
1492 if (IP != WaterList.end())
1493 WaterList.erase(IP);
1495 // Okay, we know we can put an island before NewMBB now, do it!
1496 MF->insert(NewMBB->getIterator(), NewIsland);
1498 // Update internal data structures to account for the newly inserted MBB.
1499 updateForInsertedWaterBlock(NewIsland);
1501 // Now that we have an island to add the CPE to, clone the original CPE and
1502 // add it to the island.
1503 U.HighWaterMark = NewIsland;
1504 U.CPEMI = BuildMI(NewIsland, DebugLoc(), CPEMI->getDesc())
1506 .add(CPEMI->getOperand(1))
1508 CPEntries[CPI].push_back(CPEntry(U.CPEMI, ID, 1));
1511 // Decrement the old entry, and remove it if refcount becomes 0.
1512 decrementCPEReferenceCount(CPI, CPEMI);
1514 // Mark the basic block as aligned as required by the const-pool entry.
1515 NewIsland->setAlignment(getCPELogAlign(U.CPEMI));
1517 // Increase the size of the island block to account for the new entry.
1518 BBInfo[NewIsland->getNumber()].Size += Size;
1519 adjustBBOffsetsAfter(&*--NewIsland->getIterator());
1521 // Finally, change the CPI in the instruction operand to be ID.
1522 for (unsigned i = 0, e = UserMI->getNumOperands(); i != e; ++i)
1523 if (UserMI->getOperand(i).isCPI()) {
1524 UserMI->getOperand(i).setIndex(ID);
1528 DEBUG(dbgs() << " Moved CPE to #" << ID << " CPI=" << CPI
1529 << format(" offset=%#x\n", BBInfo[NewIsland->getNumber()].Offset));
1534 /// removeDeadCPEMI - Remove a dead constant pool entry instruction. Update
1535 /// sizes and offsets of impacted basic blocks.
1536 void ARMConstantIslands::removeDeadCPEMI(MachineInstr *CPEMI) {
1537 MachineBasicBlock *CPEBB = CPEMI->getParent();
1538 unsigned Size = CPEMI->getOperand(2).getImm();
1539 CPEMI->eraseFromParent();
1540 BBInfo[CPEBB->getNumber()].Size -= Size;
1541 // All succeeding offsets have the current size value added in, fix this.
1542 if (CPEBB->empty()) {
1543 BBInfo[CPEBB->getNumber()].Size = 0;
1545 // This block no longer needs to be aligned.
1546 CPEBB->setAlignment(0);
1548 // Entries are sorted by descending alignment, so realign from the front.
1549 CPEBB->setAlignment(getCPELogAlign(&*CPEBB->begin()));
1551 adjustBBOffsetsAfter(CPEBB);
1552 // An island has only one predecessor BB and one successor BB. Check if
1553 // this BB's predecessor jumps directly to this BB's successor. This
1554 // shouldn't happen currently.
1555 assert(!BBIsJumpedOver(CPEBB) && "How did this happen?");
1556 // FIXME: remove the empty blocks after all the work is done?
1559 /// removeUnusedCPEntries - Remove constant pool entries whose refcounts
1561 bool ARMConstantIslands::removeUnusedCPEntries() {
1562 unsigned MadeChange = false;
1563 for (unsigned i = 0, e = CPEntries.size(); i != e; ++i) {
1564 std::vector<CPEntry> &CPEs = CPEntries[i];
1565 for (unsigned j = 0, ee = CPEs.size(); j != ee; ++j) {
1566 if (CPEs[j].RefCount == 0 && CPEs[j].CPEMI) {
1567 removeDeadCPEMI(CPEs[j].CPEMI);
1568 CPEs[j].CPEMI = nullptr;
1576 /// isBBInRange - Returns true if the distance between specific MI and
1577 /// specific BB can fit in MI's displacement field.
1578 bool ARMConstantIslands::isBBInRange(MachineInstr *MI,MachineBasicBlock *DestBB,
1580 unsigned PCAdj = isThumb ? 4 : 8;
1581 unsigned BrOffset = getOffsetOf(MI) + PCAdj;
1582 unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1584 DEBUG(dbgs() << "Branch of destination BB#" << DestBB->getNumber()
1585 << " from BB#" << MI->getParent()->getNumber()
1586 << " max delta=" << MaxDisp
1587 << " from " << getOffsetOf(MI) << " to " << DestOffset
1588 << " offset " << int(DestOffset-BrOffset) << "\t" << *MI);
1590 if (BrOffset <= DestOffset) {
1591 // Branch before the Dest.
1592 if (DestOffset-BrOffset <= MaxDisp)
1595 if (BrOffset-DestOffset <= MaxDisp)
1601 /// fixupImmediateBr - Fix up an immediate branch whose destination is too far
1602 /// away to fit in its displacement field.
1603 bool ARMConstantIslands::fixupImmediateBr(ImmBranch &Br) {
1604 MachineInstr *MI = Br.MI;
1605 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1607 // Check to see if the DestBB is already in-range.
1608 if (isBBInRange(MI, DestBB, Br.MaxDisp))
1612 return fixupUnconditionalBr(Br);
1613 return fixupConditionalBr(Br);
1616 /// fixupUnconditionalBr - Fix up an unconditional branch whose destination is
1617 /// too far away to fit in its displacement field. If the LR register has been
1618 /// spilled in the epilogue, then we can use BL to implement a far jump.
1619 /// Otherwise, add an intermediate branch instruction to a branch.
1621 ARMConstantIslands::fixupUnconditionalBr(ImmBranch &Br) {
1622 MachineInstr *MI = Br.MI;
1623 MachineBasicBlock *MBB = MI->getParent();
1625 llvm_unreachable("fixupUnconditionalBr is Thumb1 only!");
1627 // Use BL to implement far jump.
1628 Br.MaxDisp = (1 << 21) * 2;
1629 MI->setDesc(TII->get(ARM::tBfar));
1630 BBInfo[MBB->getNumber()].Size += 2;
1631 adjustBBOffsetsAfter(MBB);
1635 DEBUG(dbgs() << " Changed B to long jump " << *MI);
1640 /// fixupConditionalBr - Fix up a conditional branch whose destination is too
1641 /// far away to fit in its displacement field. It is converted to an inverse
1642 /// conditional branch + an unconditional branch to the destination.
1644 ARMConstantIslands::fixupConditionalBr(ImmBranch &Br) {
1645 MachineInstr *MI = Br.MI;
1646 MachineBasicBlock *DestBB = MI->getOperand(0).getMBB();
1648 // Add an unconditional branch to the destination and invert the branch
1649 // condition to jump over it:
1655 ARMCC::CondCodes CC = (ARMCC::CondCodes)MI->getOperand(1).getImm();
1656 CC = ARMCC::getOppositeCondition(CC);
1657 unsigned CCReg = MI->getOperand(2).getReg();
1659 // If the branch is at the end of its MBB and that has a fall-through block,
1660 // direct the updated conditional branch to the fall-through block. Otherwise,
1661 // split the MBB before the next instruction.
1662 MachineBasicBlock *MBB = MI->getParent();
1663 MachineInstr *BMI = &MBB->back();
1664 bool NeedSplit = (BMI != MI) || !BBHasFallthrough(MBB);
1668 if (std::next(MachineBasicBlock::iterator(MI)) == std::prev(MBB->end()) &&
1669 BMI->getOpcode() == Br.UncondBr) {
1670 // Last MI in the BB is an unconditional branch. Can we simply invert the
1671 // condition and swap destinations:
1677 MachineBasicBlock *NewDest = BMI->getOperand(0).getMBB();
1678 if (isBBInRange(MI, NewDest, Br.MaxDisp)) {
1679 DEBUG(dbgs() << " Invert Bcc condition and swap its destination with "
1681 BMI->getOperand(0).setMBB(DestBB);
1682 MI->getOperand(0).setMBB(NewDest);
1683 MI->getOperand(1).setImm(CC);
1690 splitBlockBeforeInstr(MI);
1691 // No need for the branch to the next block. We're adding an unconditional
1692 // branch to the destination.
1693 int delta = TII->getInstSizeInBytes(MBB->back());
1694 BBInfo[MBB->getNumber()].Size -= delta;
1695 MBB->back().eraseFromParent();
1696 // BBInfo[SplitBB].Offset is wrong temporarily, fixed below
1698 MachineBasicBlock *NextBB = &*++MBB->getIterator();
1700 DEBUG(dbgs() << " Insert B to BB#" << DestBB->getNumber()
1701 << " also invert condition and change dest. to BB#"
1702 << NextBB->getNumber() << "\n");
1704 // Insert a new conditional branch and a new unconditional branch.
1705 // Also update the ImmBranch as well as adding a new entry for the new branch.
1706 BuildMI(MBB, DebugLoc(), TII->get(MI->getOpcode()))
1707 .addMBB(NextBB).addImm(CC).addReg(CCReg);
1708 Br.MI = &MBB->back();
1709 BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
1711 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr))
1713 .add(predOps(ARMCC::AL));
1715 BuildMI(MBB, DebugLoc(), TII->get(Br.UncondBr)).addMBB(DestBB);
1716 BBInfo[MBB->getNumber()].Size += TII->getInstSizeInBytes(MBB->back());
1717 unsigned MaxDisp = getUnconditionalBrDisp(Br.UncondBr);
1718 ImmBranches.push_back(ImmBranch(&MBB->back(), MaxDisp, false, Br.UncondBr));
1720 // Remove the old conditional branch. It may or may not still be in MBB.
1721 BBInfo[MI->getParent()->getNumber()].Size -= TII->getInstSizeInBytes(*MI);
1722 MI->eraseFromParent();
1723 adjustBBOffsetsAfter(MBB);
1727 /// undoLRSpillRestore - Remove Thumb push / pop instructions that only spills
1728 /// LR / restores LR to pc. FIXME: This is done here because it's only possible
1729 /// to do this if tBfar is not used.
1730 bool ARMConstantIslands::undoLRSpillRestore() {
1731 bool MadeChange = false;
1732 for (unsigned i = 0, e = PushPopMIs.size(); i != e; ++i) {
1733 MachineInstr *MI = PushPopMIs[i];
1734 // First two operands are predicates.
1735 if (MI->getOpcode() == ARM::tPOP_RET &&
1736 MI->getOperand(2).getReg() == ARM::PC &&
1737 MI->getNumExplicitOperands() == 3) {
1738 // Create the new insn and copy the predicate from the old.
1739 BuildMI(MI->getParent(), MI->getDebugLoc(), TII->get(ARM::tBX_RET))
1740 .add(MI->getOperand(0))
1741 .add(MI->getOperand(1));
1742 MI->eraseFromParent();
1744 } else if (MI->getOpcode() == ARM::tPUSH &&
1745 MI->getOperand(2).getReg() == ARM::LR &&
1746 MI->getNumExplicitOperands() == 3) {
1747 // Just remove the push.
1748 MI->eraseFromParent();
1755 bool ARMConstantIslands::optimizeThumb2Instructions() {
1756 bool MadeChange = false;
1758 // Shrink ADR and LDR from constantpool.
1759 for (unsigned i = 0, e = CPUsers.size(); i != e; ++i) {
1760 CPUser &U = CPUsers[i];
1761 unsigned Opcode = U.MI->getOpcode();
1762 unsigned NewOpc = 0;
1767 case ARM::t2LEApcrel:
1768 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1769 NewOpc = ARM::tLEApcrel;
1775 if (isARMLowRegister(U.MI->getOperand(0).getReg())) {
1776 NewOpc = ARM::tLDRpci;
1786 unsigned UserOffset = getUserOffset(U);
1787 unsigned MaxOffs = ((1 << Bits) - 1) * Scale;
1789 // Be conservative with inline asm.
1790 if (!U.KnownAlignment)
1793 // FIXME: Check if offset is multiple of scale if scale is not 4.
1794 if (isCPEntryInRange(U.MI, UserOffset, U.CPEMI, MaxOffs, false, true)) {
1795 DEBUG(dbgs() << "Shrink: " << *U.MI);
1796 U.MI->setDesc(TII->get(NewOpc));
1797 MachineBasicBlock *MBB = U.MI->getParent();
1798 BBInfo[MBB->getNumber()].Size -= 2;
1799 adjustBBOffsetsAfter(MBB);
1808 bool ARMConstantIslands::optimizeThumb2Branches() {
1809 bool MadeChange = false;
1811 // The order in which branches appear in ImmBranches is approximately their
1812 // order within the function body. By visiting later branches first, we reduce
1813 // the distance between earlier forward branches and their targets, making it
1814 // more likely that the cbn?z optimization, which can only apply to forward
1815 // branches, will succeed.
1816 for (unsigned i = ImmBranches.size(); i != 0; --i) {
1817 ImmBranch &Br = ImmBranches[i-1];
1818 unsigned Opcode = Br.MI->getOpcode();
1819 unsigned NewOpc = 0;
1836 unsigned MaxOffs = ((1 << (Bits-1))-1) * Scale;
1837 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1838 if (isBBInRange(Br.MI, DestBB, MaxOffs)) {
1839 DEBUG(dbgs() << "Shrink branch: " << *Br.MI);
1840 Br.MI->setDesc(TII->get(NewOpc));
1841 MachineBasicBlock *MBB = Br.MI->getParent();
1842 BBInfo[MBB->getNumber()].Size -= 2;
1843 adjustBBOffsetsAfter(MBB);
1849 Opcode = Br.MI->getOpcode();
1850 if (Opcode != ARM::tBcc)
1853 // If the conditional branch doesn't kill CPSR, then CPSR can be liveout
1854 // so this transformation is not safe.
1855 if (!Br.MI->killsRegister(ARM::CPSR))
1859 unsigned PredReg = 0;
1860 ARMCC::CondCodes Pred = getInstrPredicate(*Br.MI, PredReg);
1861 if (Pred == ARMCC::EQ)
1863 else if (Pred == ARMCC::NE)
1864 NewOpc = ARM::tCBNZ;
1867 MachineBasicBlock *DestBB = Br.MI->getOperand(0).getMBB();
1868 // Check if the distance is within 126. Subtract starting offset by 2
1869 // because the cmp will be eliminated.
1870 unsigned BrOffset = getOffsetOf(Br.MI) + 4 - 2;
1871 unsigned DestOffset = BBInfo[DestBB->getNumber()].Offset;
1872 if (BrOffset < DestOffset && (DestOffset - BrOffset) <= 126) {
1873 MachineBasicBlock::iterator CmpMI = Br.MI;
1874 if (CmpMI != Br.MI->getParent()->begin()) {
1876 if (CmpMI->getOpcode() == ARM::tCMPi8) {
1877 unsigned Reg = CmpMI->getOperand(0).getReg();
1878 Pred = getInstrPredicate(*CmpMI, PredReg);
1879 if (Pred == ARMCC::AL &&
1880 CmpMI->getOperand(1).getImm() == 0 &&
1881 isARMLowRegister(Reg)) {
1882 MachineBasicBlock *MBB = Br.MI->getParent();
1883 DEBUG(dbgs() << "Fold: " << *CmpMI << " and: " << *Br.MI);
1884 MachineInstr *NewBR =
1885 BuildMI(*MBB, CmpMI, Br.MI->getDebugLoc(), TII->get(NewOpc))
1886 .addReg(Reg).addMBB(DestBB,Br.MI->getOperand(0).getTargetFlags());
1887 CmpMI->eraseFromParent();
1888 Br.MI->eraseFromParent();
1890 BBInfo[MBB->getNumber()].Size -= 2;
1891 adjustBBOffsetsAfter(MBB);
1903 static bool isSimpleIndexCalc(MachineInstr &I, unsigned EntryReg,
1905 if (I.getOpcode() != ARM::t2ADDrs)
1908 if (I.getOperand(0).getReg() != EntryReg)
1911 if (I.getOperand(1).getReg() != BaseReg)
1914 // FIXME: what about CC and IdxReg?
1918 /// \brief While trying to form a TBB/TBH instruction, we may (if the table
1919 /// doesn't immediately follow the BR_JT) need access to the start of the
1920 /// jump-table. We know one instruction that produces such a register; this
1921 /// function works out whether that definition can be preserved to the BR_JT,
1922 /// possibly by removing an intervening addition (which is usually needed to
1923 /// calculate the actual entry to jump to).
1924 bool ARMConstantIslands::preserveBaseRegister(MachineInstr *JumpMI,
1925 MachineInstr *LEAMI,
1928 bool &BaseRegKill) {
1929 if (JumpMI->getParent() != LEAMI->getParent())
1932 // Now we hope that we have at least these instructions in the basic block:
1933 // BaseReg = t2LEA ...
1935 // EntryReg = t2ADDrs BaseReg, ...
1939 // We have to be very conservative about what we recognise here though. The
1940 // main perturbing factors to watch out for are:
1941 // + Spills at any point in the chain: not direct problems but we would
1942 // expect a blocking Def of the spilled register so in practice what we
1943 // can do is limited.
1944 // + EntryReg == BaseReg: this is the one situation we should allow a Def
1945 // of BaseReg, but only if the t2ADDrs can be removed.
1946 // + Some instruction other than t2ADDrs computing the entry. Not seen in
1947 // the wild, but we should be careful.
1948 unsigned EntryReg = JumpMI->getOperand(0).getReg();
1949 unsigned BaseReg = LEAMI->getOperand(0).getReg();
1951 CanDeleteLEA = true;
1952 BaseRegKill = false;
1953 MachineInstr *RemovableAdd = nullptr;
1954 MachineBasicBlock::iterator I(LEAMI);
1955 for (++I; &*I != JumpMI; ++I) {
1956 if (isSimpleIndexCalc(*I, EntryReg, BaseReg)) {
1961 for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
1962 const MachineOperand &MO = I->getOperand(K);
1963 if (!MO.isReg() || !MO.getReg())
1965 if (MO.isDef() && MO.getReg() == BaseReg)
1967 if (MO.isUse() && MO.getReg() == BaseReg) {
1968 BaseRegKill = BaseRegKill || MO.isKill();
1969 CanDeleteLEA = false;
1977 // Check the add really is removable, and that nothing else in the block
1978 // clobbers BaseReg.
1979 for (++I; &*I != JumpMI; ++I) {
1980 for (unsigned K = 0, E = I->getNumOperands(); K != E; ++K) {
1981 const MachineOperand &MO = I->getOperand(K);
1982 if (!MO.isReg() || !MO.getReg())
1984 if (MO.isDef() && MO.getReg() == BaseReg)
1986 if (MO.isUse() && MO.getReg() == EntryReg)
1987 RemovableAdd = nullptr;
1992 RemovableAdd->eraseFromParent();
1993 DeadSize += isThumb2 ? 4 : 2;
1994 } else if (BaseReg == EntryReg) {
1995 // The add wasn't removable, but clobbered the base for the TBB. So we can't
2000 // We reached the end of the block without seeing another definition of
2001 // BaseReg (except, possibly the t2ADDrs, which was removed). BaseReg can be
2002 // used in the TBB/TBH if necessary.
2006 /// \brief Returns whether CPEMI is the first instruction in the block
2007 /// immediately following JTMI (assumed to be a TBB or TBH terminator). If so,
2008 /// we can switch the first register to PC and usually remove the address
2009 /// calculation that preceded it.
2010 static bool jumpTableFollowsTB(MachineInstr *JTMI, MachineInstr *CPEMI) {
2011 MachineFunction::iterator MBB = JTMI->getParent()->getIterator();
2012 MachineFunction *MF = MBB->getParent();
2015 return MBB != MF->end() && MBB->begin() != MBB->end() &&
2016 &*MBB->begin() == CPEMI;
2019 static void RemoveDeadAddBetweenLEAAndJT(MachineInstr *LEAMI,
2020 MachineInstr *JumpMI,
2021 unsigned &DeadSize) {
2022 // Remove a dead add between the LEA and JT, which used to compute EntryReg,
2023 // but the JT now uses PC. Finds the last ADD (if any) that def's EntryReg
2024 // and is not clobbered / used.
2025 MachineInstr *RemovableAdd = nullptr;
2026 unsigned EntryReg = JumpMI->getOperand(0).getReg();
2028 // Find the last ADD to set EntryReg
2029 MachineBasicBlock::iterator I(LEAMI);
2030 for (++I; &*I != JumpMI; ++I) {
2031 if (I->getOpcode() == ARM::t2ADDrs && I->getOperand(0).getReg() == EntryReg)
2038 // Ensure EntryReg is not clobbered or used.
2039 MachineBasicBlock::iterator J(RemovableAdd);
2040 for (++J; &*J != JumpMI; ++J) {
2041 for (unsigned K = 0, E = J->getNumOperands(); K != E; ++K) {
2042 const MachineOperand &MO = J->getOperand(K);
2043 if (!MO.isReg() || !MO.getReg())
2045 if (MO.isDef() && MO.getReg() == EntryReg)
2047 if (MO.isUse() && MO.getReg() == EntryReg)
2052 DEBUG(dbgs() << "Removing Dead Add: " << *RemovableAdd);
2053 RemovableAdd->eraseFromParent();
2057 static bool registerDefinedBetween(unsigned Reg,
2058 MachineBasicBlock::iterator From,
2059 MachineBasicBlock::iterator To,
2060 const TargetRegisterInfo *TRI) {
2061 for (auto I = From; I != To; ++I)
2062 if (I->modifiesRegister(Reg, TRI))
2067 /// optimizeThumb2JumpTables - Use tbb / tbh instructions to generate smaller
2068 /// jumptables when it's possible.
2069 bool ARMConstantIslands::optimizeThumb2JumpTables() {
2070 bool MadeChange = false;
2072 // FIXME: After the tables are shrunk, can we get rid some of the
2073 // constantpool tables?
2074 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2075 if (!MJTI) return false;
2077 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2078 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
2079 MachineInstr *MI = T2JumpTables[i];
2080 const MCInstrDesc &MCID = MI->getDesc();
2081 unsigned NumOps = MCID.getNumOperands();
2082 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2083 MachineOperand JTOP = MI->getOperand(JTOpIdx);
2084 unsigned JTI = JTOP.getIndex();
2085 assert(JTI < JT.size());
2088 bool HalfWordOk = true;
2089 unsigned JTOffset = getOffsetOf(MI) + 4;
2090 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2091 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
2092 MachineBasicBlock *MBB = JTBBs[j];
2093 unsigned DstOffset = BBInfo[MBB->getNumber()].Offset;
2094 // Negative offset is not ok. FIXME: We should change BB layout to make
2095 // sure all the branches are forward.
2096 if (ByteOk && (DstOffset - JTOffset) > ((1<<8)-1)*2)
2098 unsigned TBHLimit = ((1<<16)-1)*2;
2099 if (HalfWordOk && (DstOffset - JTOffset) > TBHLimit)
2101 if (!ByteOk && !HalfWordOk)
2105 if (!ByteOk && !HalfWordOk)
2108 CPUser &User = CPUsers[JumpTableUserIndices[JTI]];
2109 MachineBasicBlock *MBB = MI->getParent();
2110 if (!MI->getOperand(0).isKill()) // FIXME: needed now?
2113 unsigned DeadSize = 0;
2114 bool CanDeleteLEA = false;
2115 bool BaseRegKill = false;
2117 unsigned IdxReg = ~0U;
2118 bool IdxRegKill = true;
2120 IdxReg = MI->getOperand(1).getReg();
2121 IdxRegKill = MI->getOperand(1).isKill();
2123 bool PreservedBaseReg =
2124 preserveBaseRegister(MI, User.MI, DeadSize, CanDeleteLEA, BaseRegKill);
2125 if (!jumpTableFollowsTB(MI, User.CPEMI) && !PreservedBaseReg)
2128 // We're in thumb-1 mode, so we must have something like:
2129 // %idx = tLSLri %idx, 2
2130 // %base = tLEApcrelJT
2131 // %t = tLDRr %idx, %base
2132 unsigned BaseReg = User.MI->getOperand(0).getReg();
2134 if (User.MI->getIterator() == User.MI->getParent()->begin())
2136 MachineInstr *Shift = User.MI->getPrevNode();
2137 if (Shift->getOpcode() != ARM::tLSLri ||
2138 Shift->getOperand(3).getImm() != 2 ||
2139 !Shift->getOperand(2).isKill())
2141 IdxReg = Shift->getOperand(2).getReg();
2142 unsigned ShiftedIdxReg = Shift->getOperand(0).getReg();
2144 // It's important that IdxReg is live until the actual TBB/TBH. Most of
2145 // the range is checked later, but the LEA might still clobber it and not
2146 // actually get removed.
2147 if (BaseReg == IdxReg && !jumpTableFollowsTB(MI, User.CPEMI))
2150 MachineInstr *Load = User.MI->getNextNode();
2151 if (Load->getOpcode() != ARM::tLDRr)
2153 if (Load->getOperand(1).getReg() != ShiftedIdxReg ||
2154 Load->getOperand(2).getReg() != BaseReg ||
2155 !Load->getOperand(1).isKill())
2158 // If we're in PIC mode, there should be another ADD following.
2159 auto *TRI = STI->getRegisterInfo();
2161 // %base cannot be redefined after the load as it will appear before
2166 if (registerDefinedBetween(BaseReg, Load->getNextNode(), MBB->end(), TRI))
2169 if (isPositionIndependentOrROPI) {
2170 MachineInstr *Add = Load->getNextNode();
2171 if (Add->getOpcode() != ARM::tADDrr ||
2172 Add->getOperand(2).getReg() != Load->getOperand(0).getReg() ||
2173 Add->getOperand(3).getReg() != BaseReg ||
2174 !Add->getOperand(2).isKill())
2176 if (Add->getOperand(0).getReg() != MI->getOperand(0).getReg())
2178 if (registerDefinedBetween(IdxReg, Add->getNextNode(), MI, TRI))
2179 // IdxReg gets redefined in the middle of the sequence.
2181 Add->eraseFromParent();
2184 if (Load->getOperand(0).getReg() != MI->getOperand(0).getReg())
2186 if (registerDefinedBetween(IdxReg, Load->getNextNode(), MI, TRI))
2187 // IdxReg gets redefined in the middle of the sequence.
2191 // Now safe to delete the load and lsl. The LEA will be removed later.
2192 CanDeleteLEA = true;
2193 Shift->eraseFromParent();
2194 Load->eraseFromParent();
2198 DEBUG(dbgs() << "Shrink JT: " << *MI);
2199 MachineInstr *CPEMI = User.CPEMI;
2200 unsigned Opc = ByteOk ? ARM::t2TBB_JT : ARM::t2TBH_JT;
2202 Opc = ByteOk ? ARM::tTBB_JT : ARM::tTBH_JT;
2204 MachineBasicBlock::iterator MI_JT = MI;
2205 MachineInstr *NewJTMI =
2206 BuildMI(*MBB, MI_JT, MI->getDebugLoc(), TII->get(Opc))
2207 .addReg(User.MI->getOperand(0).getReg(),
2208 getKillRegState(BaseRegKill))
2209 .addReg(IdxReg, getKillRegState(IdxRegKill))
2210 .addJumpTableIndex(JTI, JTOP.getTargetFlags())
2211 .addImm(CPEMI->getOperand(0).getImm());
2212 DEBUG(dbgs() << "BB#" << MBB->getNumber() << ": " << *NewJTMI);
2214 unsigned JTOpc = ByteOk ? ARM::JUMPTABLE_TBB : ARM::JUMPTABLE_TBH;
2215 CPEMI->setDesc(TII->get(JTOpc));
2217 if (jumpTableFollowsTB(MI, User.CPEMI)) {
2218 NewJTMI->getOperand(0).setReg(ARM::PC);
2219 NewJTMI->getOperand(0).setIsKill(false);
2223 RemoveDeadAddBetweenLEAAndJT(User.MI, MI, DeadSize);
2225 User.MI->eraseFromParent();
2226 DeadSize += isThumb2 ? 4 : 2;
2228 // The LEA was eliminated, the TBB instruction becomes the only new user
2229 // of the jump table.
2233 User.IsSoImm = false;
2234 User.KnownAlignment = false;
2236 // The LEA couldn't be eliminated, so we must add another CPUser to
2237 // record the TBB or TBH use.
2238 int CPEntryIdx = JumpTableEntryIndices[JTI];
2239 auto &CPEs = CPEntries[CPEntryIdx];
2241 find_if(CPEs, [&](CPEntry &E) { return E.CPEMI == User.CPEMI; });
2243 CPUsers.emplace_back(CPUser(NewJTMI, User.CPEMI, 4, false, false));
2247 unsigned NewSize = TII->getInstSizeInBytes(*NewJTMI);
2248 unsigned OrigSize = TII->getInstSizeInBytes(*MI);
2249 MI->eraseFromParent();
2251 int Delta = OrigSize - NewSize + DeadSize;
2252 BBInfo[MBB->getNumber()].Size -= Delta;
2253 adjustBBOffsetsAfter(MBB);
2262 /// reorderThumb2JumpTables - Adjust the function's block layout to ensure that
2263 /// jump tables always branch forwards, since that's what tbb and tbh need.
2264 bool ARMConstantIslands::reorderThumb2JumpTables() {
2265 bool MadeChange = false;
2267 MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
2268 if (!MJTI) return false;
2270 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
2271 for (unsigned i = 0, e = T2JumpTables.size(); i != e; ++i) {
2272 MachineInstr *MI = T2JumpTables[i];
2273 const MCInstrDesc &MCID = MI->getDesc();
2274 unsigned NumOps = MCID.getNumOperands();
2275 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1);
2276 MachineOperand JTOP = MI->getOperand(JTOpIdx);
2277 unsigned JTI = JTOP.getIndex();
2278 assert(JTI < JT.size());
2280 // We prefer if target blocks for the jump table come after the jump
2281 // instruction so we can use TB[BH]. Loop through the target blocks
2282 // and try to adjust them such that that's true.
2283 int JTNumber = MI->getParent()->getNumber();
2284 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
2285 for (unsigned j = 0, ee = JTBBs.size(); j != ee; ++j) {
2286 MachineBasicBlock *MBB = JTBBs[j];
2287 int DTNumber = MBB->getNumber();
2289 if (DTNumber < JTNumber) {
2290 // The destination precedes the switch. Try to move the block forward
2291 // so we have a positive offset.
2292 MachineBasicBlock *NewBB =
2293 adjustJTTargetBlockForward(MBB, MI->getParent());
2295 MJTI->ReplaceMBBInJumpTable(JTI, JTBBs[j], NewBB);
2304 MachineBasicBlock *ARMConstantIslands::
2305 adjustJTTargetBlockForward(MachineBasicBlock *BB, MachineBasicBlock *JTBB) {
2306 // If the destination block is terminated by an unconditional branch,
2307 // try to move it; otherwise, create a new block following the jump
2308 // table that branches back to the actual target. This is a very simple
2309 // heuristic. FIXME: We can definitely improve it.
2310 MachineBasicBlock *TBB = nullptr, *FBB = nullptr;
2311 SmallVector<MachineOperand, 4> Cond;
2312 SmallVector<MachineOperand, 4> CondPrior;
2313 MachineFunction::iterator BBi = BB->getIterator();
2314 MachineFunction::iterator OldPrior = std::prev(BBi);
2316 // If the block terminator isn't analyzable, don't try to move the block
2317 bool B = TII->analyzeBranch(*BB, TBB, FBB, Cond);
2319 // If the block ends in an unconditional branch, move it. The prior block
2320 // has to have an analyzable terminator for us to move this one. Be paranoid
2321 // and make sure we're not trying to move the entry block of the function.
2322 if (!B && Cond.empty() && BB != &MF->front() &&
2323 !TII->analyzeBranch(*OldPrior, TBB, FBB, CondPrior)) {
2324 BB->moveAfter(JTBB);
2325 OldPrior->updateTerminator();
2326 BB->updateTerminator();
2327 // Update numbering to account for the block being moved.
2328 MF->RenumberBlocks();
2333 // Create a new MBB for the code after the jump BB.
2334 MachineBasicBlock *NewBB =
2335 MF->CreateMachineBasicBlock(JTBB->getBasicBlock());
2336 MachineFunction::iterator MBBI = ++JTBB->getIterator();
2337 MF->insert(MBBI, NewBB);
2339 // Add an unconditional branch from NewBB to BB.
2340 // There doesn't seem to be meaningful DebugInfo available; this doesn't
2341 // correspond directly to anything in the source.
2343 BuildMI(NewBB, DebugLoc(), TII->get(ARM::t2B))
2345 .add(predOps(ARMCC::AL));
2347 BuildMI(NewBB, DebugLoc(), TII->get(ARM::tB))
2349 .add(predOps(ARMCC::AL));
2351 // Update internal data structures to account for the newly inserted MBB.
2352 MF->RenumberBlocks(NewBB);
2355 NewBB->addSuccessor(BB);
2356 JTBB->replaceSuccessor(BB, NewBB);
2362 /// createARMConstantIslandPass - returns an instance of the constpool
2364 FunctionPass *llvm::createARMConstantIslandPass() {
2365 return new ARMConstantIslands();
2368 INITIALIZE_PASS(ARMConstantIslands, "arm-cp-islands", ARM_CP_ISLANDS_OPT_NAME,