1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains a pass that expands pseudo instructions into target
11 // instructions to allow proper scheduling, if-conversion, and other late
12 // optimizations. This pass should be run after register allocation but before
13 // the post-regalloc scheduling pass.
15 //===----------------------------------------------------------------------===//
18 #include "ARMBaseInstrInfo.h"
19 #include "ARMBaseRegisterInfo.h"
20 #include "ARMConstantPoolValue.h"
21 #include "ARMMachineFunctionInfo.h"
22 #include "ARMSubtarget.h"
23 #include "MCTargetDesc/ARMAddressingModes.h"
24 #include "llvm/CodeGen/LivePhysRegs.h"
25 #include "llvm/CodeGen/MachineFrameInfo.h"
26 #include "llvm/CodeGen/MachineFunctionPass.h"
27 #include "llvm/CodeGen/MachineInstrBuilder.h"
28 #include "llvm/CodeGen/MachineInstrBundle.h"
29 #include "llvm/IR/GlobalValue.h"
30 #include "llvm/Support/CommandLine.h"
31 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove!
32 #include "llvm/Target/TargetFrameLowering.h"
33 #include "llvm/Target/TargetRegisterInfo.h"
37 #define DEBUG_TYPE "arm-pseudo"
40 VerifyARMPseudo("verify-arm-pseudo-expand", cl::Hidden,
41 cl::desc("Verify machine code after expanding ARM pseudos"));
44 class ARMExpandPseudo : public MachineFunctionPass {
47 ARMExpandPseudo() : MachineFunctionPass(ID) {}
49 const ARMBaseInstrInfo *TII;
50 const TargetRegisterInfo *TRI;
51 const ARMSubtarget *STI;
54 bool runOnMachineFunction(MachineFunction &Fn) override;
56 MachineFunctionProperties getRequiredProperties() const override {
57 return MachineFunctionProperties().set(
58 MachineFunctionProperties::Property::NoVRegs);
61 StringRef getPassName() const override {
62 return "ARM pseudo instruction expansion pass";
66 void TransferImpOps(MachineInstr &OldMI,
67 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI);
68 bool ExpandMI(MachineBasicBlock &MBB,
69 MachineBasicBlock::iterator MBBI,
70 MachineBasicBlock::iterator &NextMBBI);
71 bool ExpandMBB(MachineBasicBlock &MBB);
72 void ExpandVLD(MachineBasicBlock::iterator &MBBI);
73 void ExpandVST(MachineBasicBlock::iterator &MBBI);
74 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI);
75 void ExpandVTBL(MachineBasicBlock::iterator &MBBI,
76 unsigned Opc, bool IsExt);
77 void ExpandMOV32BitImm(MachineBasicBlock &MBB,
78 MachineBasicBlock::iterator &MBBI);
79 bool ExpandCMP_SWAP(MachineBasicBlock &MBB,
80 MachineBasicBlock::iterator MBBI, unsigned LdrexOp,
81 unsigned StrexOp, unsigned UxtOp,
82 MachineBasicBlock::iterator &NextMBBI);
84 bool ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
85 MachineBasicBlock::iterator MBBI,
86 MachineBasicBlock::iterator &NextMBBI);
88 char ARMExpandPseudo::ID = 0;
91 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to
92 /// the instructions created from the expansion.
93 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI,
94 MachineInstrBuilder &UseMI,
95 MachineInstrBuilder &DefMI) {
96 const MCInstrDesc &Desc = OldMI.getDesc();
97 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands();
99 const MachineOperand &MO = OldMI.getOperand(i);
100 assert(MO.isReg() && MO.getReg());
109 // Constants for register spacing in NEON load/store instructions.
110 // For quad-register load-lane and store-lane pseudo instructors, the
111 // spacing is initially assumed to be EvenDblSpc, and that is changed to
112 // OddDblSpc depending on the lane number operand.
113 enum NEONRegSpacing {
119 // Entries for NEON load/store information table. The table is sorted by
120 // PseudoOpc for fast binary-search lookups.
121 struct NEONLdStTableEntry {
126 bool hasWritebackOperand;
127 uint8_t RegSpacing; // One of type NEONRegSpacing
128 uint8_t NumRegs; // D registers loaded or stored
129 uint8_t RegElts; // elements per D register; used for lane ops
130 // FIXME: Temporary flag to denote whether the real instruction takes
131 // a single register (like the encoding) or all of the registers in
132 // the list (like the asm syntax and the isel DAG). When all definitions
133 // are converted to take only the single encoded register, this will
135 bool copyAllListRegs;
137 // Comparison methods for binary search of the table.
138 bool operator<(const NEONLdStTableEntry &TE) const {
139 return PseudoOpc < TE.PseudoOpc;
141 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) {
142 return TE.PseudoOpc < PseudoOpc;
144 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc,
145 const NEONLdStTableEntry &TE) {
146 return PseudoOpc < TE.PseudoOpc;
151 static const NEONLdStTableEntry NEONLdStTable[] = {
152 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, false, EvenDblSpc, 1, 4 ,true},
153 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, true, EvenDblSpc, 1, 4 ,true},
154 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, false, EvenDblSpc, 1, 2 ,true},
155 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, true, EvenDblSpc, 1, 2 ,true},
156 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, false, EvenDblSpc, 1, 8 ,true},
157 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, true, EvenDblSpc, 1, 8 ,true},
159 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, false, SingleSpc, 4, 1 ,false},
160 { ARM::VLD1d64QPseudoWB_fixed, ARM::VLD1d64Qwb_fixed, true, true, false, SingleSpc, 4, 1 ,false},
161 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, false, SingleSpc, 3, 1 ,false},
162 { ARM::VLD1d64TPseudoWB_fixed, ARM::VLD1d64Twb_fixed, true, true, false, SingleSpc, 3, 1 ,false},
164 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, false, SingleSpc, 2, 4 ,true},
165 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, true, SingleSpc, 2, 4 ,true},
166 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, false, SingleSpc, 2, 2 ,true},
167 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, true, SingleSpc, 2, 2 ,true},
168 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, false, SingleSpc, 2, 8 ,true},
169 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, true, SingleSpc, 2, 8 ,true},
170 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, false, EvenDblSpc, 2, 4 ,true},
171 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, true, EvenDblSpc, 2, 4 ,true},
172 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, false, EvenDblSpc, 2, 2 ,true},
173 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, true, EvenDblSpc, 2, 2 ,true},
175 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, false, SingleSpc, 4, 4 ,false},
176 { ARM::VLD2q16PseudoWB_fixed, ARM::VLD2q16wb_fixed, true, true, false, SingleSpc, 4, 4 ,false},
177 { ARM::VLD2q16PseudoWB_register, ARM::VLD2q16wb_register, true, true, true, SingleSpc, 4, 4 ,false},
178 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, false, SingleSpc, 4, 2 ,false},
179 { ARM::VLD2q32PseudoWB_fixed, ARM::VLD2q32wb_fixed, true, true, false, SingleSpc, 4, 2 ,false},
180 { ARM::VLD2q32PseudoWB_register, ARM::VLD2q32wb_register, true, true, true, SingleSpc, 4, 2 ,false},
181 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, false, SingleSpc, 4, 8 ,false},
182 { ARM::VLD2q8PseudoWB_fixed, ARM::VLD2q8wb_fixed, true, true, false, SingleSpc, 4, 8 ,false},
183 { ARM::VLD2q8PseudoWB_register, ARM::VLD2q8wb_register, true, true, true, SingleSpc, 4, 8 ,false},
185 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, false, SingleSpc, 3, 4,true},
186 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, true, SingleSpc, 3, 4,true},
187 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, false, SingleSpc, 3, 2,true},
188 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, true, SingleSpc, 3, 2,true},
189 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, false, SingleSpc, 3, 8,true},
190 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, true, SingleSpc, 3, 8,true},
192 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, false, SingleSpc, 3, 4 ,true},
193 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
194 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, false, SingleSpc, 3, 2 ,true},
195 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
196 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, false, SingleSpc, 3, 8 ,true},
197 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
198 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, false, EvenDblSpc, 3, 4 ,true},
199 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
200 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, false, EvenDblSpc, 3, 2 ,true},
201 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
203 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, false, SingleSpc, 3, 4 ,true},
204 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, true, SingleSpc, 3, 4 ,true},
205 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, false, SingleSpc, 3, 2 ,true},
206 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, true, SingleSpc, 3, 2 ,true},
207 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, false, SingleSpc, 3, 8 ,true},
208 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, true, SingleSpc, 3, 8 ,true},
210 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, true, EvenDblSpc, 3, 4 ,true},
211 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, false, OddDblSpc, 3, 4 ,true},
212 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, true, OddDblSpc, 3, 4 ,true},
213 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, true, EvenDblSpc, 3, 2 ,true},
214 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, false, OddDblSpc, 3, 2 ,true},
215 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, true, OddDblSpc, 3, 2 ,true},
216 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, true, EvenDblSpc, 3, 8 ,true},
217 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, false, OddDblSpc, 3, 8 ,true},
218 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, true, OddDblSpc, 3, 8 ,true},
220 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, false, SingleSpc, 4, 4,true},
221 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, true, SingleSpc, 4, 4,true},
222 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, false, SingleSpc, 4, 2,true},
223 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, true, SingleSpc, 4, 2,true},
224 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, false, SingleSpc, 4, 8,true},
225 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, true, SingleSpc, 4, 8,true},
227 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, false, SingleSpc, 4, 4 ,true},
228 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
229 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, false, SingleSpc, 4, 2 ,true},
230 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
231 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, false, SingleSpc, 4, 8 ,true},
232 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
233 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, false, EvenDblSpc, 4, 4 ,true},
234 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
235 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, false, EvenDblSpc, 4, 2 ,true},
236 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
238 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, false, SingleSpc, 4, 4 ,true},
239 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, true, SingleSpc, 4, 4 ,true},
240 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, false, SingleSpc, 4, 2 ,true},
241 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, true, SingleSpc, 4, 2 ,true},
242 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, false, SingleSpc, 4, 8 ,true},
243 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, true, SingleSpc, 4, 8 ,true},
245 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, true, EvenDblSpc, 4, 4 ,true},
246 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, false, OddDblSpc, 4, 4 ,true},
247 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, true, OddDblSpc, 4, 4 ,true},
248 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, true, EvenDblSpc, 4, 2 ,true},
249 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, false, OddDblSpc, 4, 2 ,true},
250 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, true, OddDblSpc, 4, 2 ,true},
251 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, true, EvenDblSpc, 4, 8 ,true},
252 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, false, OddDblSpc, 4, 8 ,true},
253 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, true, OddDblSpc, 4, 8 ,true},
255 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, false, EvenDblSpc, 1, 4 ,true},
256 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD, false, true, true, EvenDblSpc, 1, 4 ,true},
257 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, false, EvenDblSpc, 1, 2 ,true},
258 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD, false, true, true, EvenDblSpc, 1, 2 ,true},
259 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, false, EvenDblSpc, 1, 8 ,true},
260 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, true, EvenDblSpc, 1, 8 ,true},
262 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, false, SingleSpc, 4, 1 ,false},
263 { ARM::VST1d64QPseudoWB_fixed, ARM::VST1d64Qwb_fixed, false, true, false, SingleSpc, 4, 1 ,false},
264 { ARM::VST1d64QPseudoWB_register, ARM::VST1d64Qwb_register, false, true, true, SingleSpc, 4, 1 ,false},
265 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, false, SingleSpc, 3, 1 ,false},
266 { ARM::VST1d64TPseudoWB_fixed, ARM::VST1d64Twb_fixed, false, true, false, SingleSpc, 3, 1 ,false},
267 { ARM::VST1d64TPseudoWB_register, ARM::VST1d64Twb_register, false, true, true, SingleSpc, 3, 1 ,false},
269 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, false, SingleSpc, 2, 4 ,true},
270 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, true, SingleSpc, 2, 4 ,true},
271 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, false, SingleSpc, 2, 2 ,true},
272 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, true, SingleSpc, 2, 2 ,true},
273 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, false, SingleSpc, 2, 8 ,true},
274 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, true, SingleSpc, 2, 8 ,true},
275 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, false, EvenDblSpc, 2, 4,true},
276 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, true, EvenDblSpc, 2, 4,true},
277 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, false, EvenDblSpc, 2, 2,true},
278 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, true, EvenDblSpc, 2, 2,true},
280 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, false, SingleSpc, 4, 4 ,false},
281 { ARM::VST2q16PseudoWB_fixed, ARM::VST2q16wb_fixed, false, true, false, SingleSpc, 4, 4 ,false},
282 { ARM::VST2q16PseudoWB_register, ARM::VST2q16wb_register, false, true, true, SingleSpc, 4, 4 ,false},
283 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, false, SingleSpc, 4, 2 ,false},
284 { ARM::VST2q32PseudoWB_fixed, ARM::VST2q32wb_fixed, false, true, false, SingleSpc, 4, 2 ,false},
285 { ARM::VST2q32PseudoWB_register, ARM::VST2q32wb_register, false, true, true, SingleSpc, 4, 2 ,false},
286 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, false, SingleSpc, 4, 8 ,false},
287 { ARM::VST2q8PseudoWB_fixed, ARM::VST2q8wb_fixed, false, true, false, SingleSpc, 4, 8 ,false},
288 { ARM::VST2q8PseudoWB_register, ARM::VST2q8wb_register, false, true, true, SingleSpc, 4, 8 ,false},
290 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, false, SingleSpc, 3, 4 ,true},
291 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
292 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, false, SingleSpc, 3, 2 ,true},
293 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
294 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, false, SingleSpc, 3, 8 ,true},
295 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
296 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, false, EvenDblSpc, 3, 4,true},
297 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, true, EvenDblSpc, 3, 4,true},
298 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, false, EvenDblSpc, 3, 2,true},
299 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, true, EvenDblSpc, 3, 2,true},
301 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, false, SingleSpc, 3, 4 ,true},
302 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, true, SingleSpc, 3, 4 ,true},
303 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, false, SingleSpc, 3, 2 ,true},
304 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, true, SingleSpc, 3, 2 ,true},
305 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, false, SingleSpc, 3, 8 ,true},
306 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, true, SingleSpc, 3, 8 ,true},
308 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, true, EvenDblSpc, 3, 4 ,true},
309 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, false, OddDblSpc, 3, 4 ,true},
310 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, true, OddDblSpc, 3, 4 ,true},
311 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, true, EvenDblSpc, 3, 2 ,true},
312 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, false, OddDblSpc, 3, 2 ,true},
313 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, true, OddDblSpc, 3, 2 ,true},
314 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, true, EvenDblSpc, 3, 8 ,true},
315 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, false, OddDblSpc, 3, 8 ,true},
316 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, true, OddDblSpc, 3, 8 ,true},
318 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, false, SingleSpc, 4, 4 ,true},
319 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
320 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, false, SingleSpc, 4, 2 ,true},
321 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
322 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, false, SingleSpc, 4, 8 ,true},
323 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
324 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, false, EvenDblSpc, 4, 4,true},
325 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, true, EvenDblSpc, 4, 4,true},
326 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, false, EvenDblSpc, 4, 2,true},
327 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, true, EvenDblSpc, 4, 2,true},
329 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, false, SingleSpc, 4, 4 ,true},
330 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, true, SingleSpc, 4, 4 ,true},
331 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, false, SingleSpc, 4, 2 ,true},
332 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, true, SingleSpc, 4, 2 ,true},
333 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, false, SingleSpc, 4, 8 ,true},
334 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, true, SingleSpc, 4, 8 ,true},
336 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, true, EvenDblSpc, 4, 4 ,true},
337 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, false, OddDblSpc, 4, 4 ,true},
338 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, true, OddDblSpc, 4, 4 ,true},
339 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, true, EvenDblSpc, 4, 2 ,true},
340 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, false, OddDblSpc, 4, 2 ,true},
341 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, true, OddDblSpc, 4, 2 ,true},
342 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, true, EvenDblSpc, 4, 8 ,true},
343 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, false, OddDblSpc, 4, 8 ,true},
344 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, true, OddDblSpc, 4, 8 ,true}
347 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON
348 /// load or store pseudo instruction.
349 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) {
351 // Make sure the table is sorted.
352 static bool TableChecked = false;
354 assert(std::is_sorted(std::begin(NEONLdStTable), std::end(NEONLdStTable)) &&
355 "NEONLdStTable is not sorted!");
360 auto I = std::lower_bound(std::begin(NEONLdStTable),
361 std::end(NEONLdStTable), Opcode);
362 if (I != std::end(NEONLdStTable) && I->PseudoOpc == Opcode)
367 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register,
368 /// corresponding to the specified register spacing. Not all of the results
369 /// are necessarily valid, e.g., a Q register only has 2 D subregisters.
370 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc,
371 const TargetRegisterInfo *TRI, unsigned &D0,
372 unsigned &D1, unsigned &D2, unsigned &D3) {
373 if (RegSpc == SingleSpc) {
374 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
375 D1 = TRI->getSubReg(Reg, ARM::dsub_1);
376 D2 = TRI->getSubReg(Reg, ARM::dsub_2);
377 D3 = TRI->getSubReg(Reg, ARM::dsub_3);
378 } else if (RegSpc == EvenDblSpc) {
379 D0 = TRI->getSubReg(Reg, ARM::dsub_0);
380 D1 = TRI->getSubReg(Reg, ARM::dsub_2);
381 D2 = TRI->getSubReg(Reg, ARM::dsub_4);
382 D3 = TRI->getSubReg(Reg, ARM::dsub_6);
384 assert(RegSpc == OddDblSpc && "unknown register spacing");
385 D0 = TRI->getSubReg(Reg, ARM::dsub_1);
386 D1 = TRI->getSubReg(Reg, ARM::dsub_3);
387 D2 = TRI->getSubReg(Reg, ARM::dsub_5);
388 D3 = TRI->getSubReg(Reg, ARM::dsub_7);
392 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register
393 /// operands to real VLD instructions with D register operands.
394 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) {
395 MachineInstr &MI = *MBBI;
396 MachineBasicBlock &MBB = *MI.getParent();
398 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
399 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed");
400 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
401 unsigned NumRegs = TableEntry->NumRegs;
403 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
404 TII->get(TableEntry->RealOpc));
407 bool DstIsDead = MI.getOperand(OpIdx).isDead();
408 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
409 unsigned D0, D1, D2, D3;
410 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
411 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
412 if (NumRegs > 1 && TableEntry->copyAllListRegs)
413 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
414 if (NumRegs > 2 && TableEntry->copyAllListRegs)
415 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
416 if (NumRegs > 3 && TableEntry->copyAllListRegs)
417 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
419 if (TableEntry->isUpdating)
420 MIB.add(MI.getOperand(OpIdx++));
422 // Copy the addrmode6 operands.
423 MIB.add(MI.getOperand(OpIdx++));
424 MIB.add(MI.getOperand(OpIdx++));
425 // Copy the am6offset operand.
426 if (TableEntry->hasWritebackOperand)
427 MIB.add(MI.getOperand(OpIdx++));
429 // For an instruction writing double-spaced subregs, the pseudo instruction
430 // has an extra operand that is a use of the super-register. Record the
431 // operand index and skip over it.
432 unsigned SrcOpIdx = 0;
433 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc)
436 // Copy the predicate operands.
437 MIB.add(MI.getOperand(OpIdx++));
438 MIB.add(MI.getOperand(OpIdx++));
440 // Copy the super-register source operand used for double-spaced subregs over
441 // to the new instruction as an implicit operand.
443 MachineOperand MO = MI.getOperand(SrcOpIdx);
444 MO.setImplicit(true);
447 // Add an implicit def for the super-register.
448 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
449 TransferImpOps(MI, MIB, MIB);
451 // Transfer memoperands.
452 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
454 MI.eraseFromParent();
457 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register
458 /// operands to real VST instructions with D register operands.
459 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) {
460 MachineInstr &MI = *MBBI;
461 MachineBasicBlock &MBB = *MI.getParent();
463 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
464 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed");
465 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
466 unsigned NumRegs = TableEntry->NumRegs;
468 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
469 TII->get(TableEntry->RealOpc));
471 if (TableEntry->isUpdating)
472 MIB.add(MI.getOperand(OpIdx++));
474 // Copy the addrmode6 operands.
475 MIB.add(MI.getOperand(OpIdx++));
476 MIB.add(MI.getOperand(OpIdx++));
477 // Copy the am6offset operand.
478 if (TableEntry->hasWritebackOperand)
479 MIB.add(MI.getOperand(OpIdx++));
481 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
482 bool SrcIsUndef = MI.getOperand(OpIdx).isUndef();
483 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
484 unsigned D0, D1, D2, D3;
485 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3);
486 MIB.addReg(D0, getUndefRegState(SrcIsUndef));
487 if (NumRegs > 1 && TableEntry->copyAllListRegs)
488 MIB.addReg(D1, getUndefRegState(SrcIsUndef));
489 if (NumRegs > 2 && TableEntry->copyAllListRegs)
490 MIB.addReg(D2, getUndefRegState(SrcIsUndef));
491 if (NumRegs > 3 && TableEntry->copyAllListRegs)
492 MIB.addReg(D3, getUndefRegState(SrcIsUndef));
494 // Copy the predicate operands.
495 MIB.add(MI.getOperand(OpIdx++));
496 MIB.add(MI.getOperand(OpIdx++));
498 if (SrcIsKill && !SrcIsUndef) // Add an implicit kill for the super-reg.
499 MIB->addRegisterKilled(SrcReg, TRI, true);
500 else if (!SrcIsUndef)
501 MIB.addReg(SrcReg, RegState::Implicit); // Add implicit uses for src reg.
502 TransferImpOps(MI, MIB, MIB);
504 // Transfer memoperands.
505 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
507 MI.eraseFromParent();
510 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ
511 /// register operands to real instructions with D register operands.
512 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) {
513 MachineInstr &MI = *MBBI;
514 MachineBasicBlock &MBB = *MI.getParent();
516 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode());
517 assert(TableEntry && "NEONLdStTable lookup failed");
518 NEONRegSpacing RegSpc = (NEONRegSpacing)TableEntry->RegSpacing;
519 unsigned NumRegs = TableEntry->NumRegs;
520 unsigned RegElts = TableEntry->RegElts;
522 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
523 TII->get(TableEntry->RealOpc));
525 // The lane operand is always the 3rd from last operand, before the 2
526 // predicate operands.
527 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm();
529 // Adjust the lane and spacing as needed for Q registers.
530 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane");
531 if (RegSpc == EvenDblSpc && Lane >= RegElts) {
535 assert(Lane < RegElts && "out of range lane for VLD/VST-lane");
537 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0;
539 bool DstIsDead = false;
540 if (TableEntry->IsLoad) {
541 DstIsDead = MI.getOperand(OpIdx).isDead();
542 DstReg = MI.getOperand(OpIdx++).getReg();
543 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3);
544 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead));
546 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
548 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
550 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
553 if (TableEntry->isUpdating)
554 MIB.add(MI.getOperand(OpIdx++));
556 // Copy the addrmode6 operands.
557 MIB.add(MI.getOperand(OpIdx++));
558 MIB.add(MI.getOperand(OpIdx++));
559 // Copy the am6offset operand.
560 if (TableEntry->hasWritebackOperand)
561 MIB.add(MI.getOperand(OpIdx++));
563 // Grab the super-register source.
564 MachineOperand MO = MI.getOperand(OpIdx++);
565 if (!TableEntry->IsLoad)
566 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3);
568 // Add the subregs as sources of the new instruction.
569 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) |
570 getKillRegState(MO.isKill()));
571 MIB.addReg(D0, SrcFlags);
573 MIB.addReg(D1, SrcFlags);
575 MIB.addReg(D2, SrcFlags);
577 MIB.addReg(D3, SrcFlags);
579 // Add the lane number operand.
583 // Copy the predicate operands.
584 MIB.add(MI.getOperand(OpIdx++));
585 MIB.add(MI.getOperand(OpIdx++));
587 // Copy the super-register source to be an implicit source.
588 MO.setImplicit(true);
590 if (TableEntry->IsLoad)
591 // Add an implicit def for the super-register.
592 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
593 TransferImpOps(MI, MIB, MIB);
594 // Transfer memoperands.
595 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
596 MI.eraseFromParent();
599 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ
600 /// register operands to real instructions with D register operands.
601 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI,
602 unsigned Opc, bool IsExt) {
603 MachineInstr &MI = *MBBI;
604 MachineBasicBlock &MBB = *MI.getParent();
606 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc));
609 // Transfer the destination register operand.
610 MIB.add(MI.getOperand(OpIdx++));
612 MIB.add(MI.getOperand(OpIdx++));
614 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
615 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
616 unsigned D0, D1, D2, D3;
617 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3);
620 // Copy the other source register operand.
621 MIB.add(MI.getOperand(OpIdx++));
623 // Copy the predicate operands.
624 MIB.add(MI.getOperand(OpIdx++));
625 MIB.add(MI.getOperand(OpIdx++));
627 // Add an implicit kill and use for the super-reg.
628 MIB.addReg(SrcReg, RegState::Implicit | getKillRegState(SrcIsKill));
629 TransferImpOps(MI, MIB, MIB);
630 MI.eraseFromParent();
633 static bool IsAnAddressOperand(const MachineOperand &MO) {
634 // This check is overly conservative. Unless we are certain that the machine
635 // operand is not a symbol reference, we return that it is a symbol reference.
636 // This is important as the load pair may not be split up Windows.
637 switch (MO.getType()) {
638 case MachineOperand::MO_Register:
639 case MachineOperand::MO_Immediate:
640 case MachineOperand::MO_CImmediate:
641 case MachineOperand::MO_FPImmediate:
643 case MachineOperand::MO_MachineBasicBlock:
645 case MachineOperand::MO_FrameIndex:
647 case MachineOperand::MO_ConstantPoolIndex:
648 case MachineOperand::MO_TargetIndex:
649 case MachineOperand::MO_JumpTableIndex:
650 case MachineOperand::MO_ExternalSymbol:
651 case MachineOperand::MO_GlobalAddress:
652 case MachineOperand::MO_BlockAddress:
654 case MachineOperand::MO_RegisterMask:
655 case MachineOperand::MO_RegisterLiveOut:
657 case MachineOperand::MO_Metadata:
658 case MachineOperand::MO_MCSymbol:
660 case MachineOperand::MO_CFIIndex:
662 case MachineOperand::MO_IntrinsicID:
663 case MachineOperand::MO_Predicate:
664 llvm_unreachable("should not exist post-isel");
666 llvm_unreachable("unhandled machine operand type");
669 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
670 MachineBasicBlock::iterator &MBBI) {
671 MachineInstr &MI = *MBBI;
672 unsigned Opcode = MI.getOpcode();
673 unsigned PredReg = 0;
674 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg);
675 unsigned DstReg = MI.getOperand(0).getReg();
676 bool DstIsDead = MI.getOperand(0).isDead();
677 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm;
678 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1);
679 bool RequiresBundling = STI->isTargetWindows() && IsAnAddressOperand(MO);
680 MachineInstrBuilder LO16, HI16;
682 if (!STI->hasV6T2Ops() &&
683 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
684 // FIXME Windows CE supports older ARM CPUs
685 assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
687 // Expand into a movi + orr.
688 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
689 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
690 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
693 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
694 unsigned ImmVal = (unsigned)MO.getImm();
695 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
696 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
697 LO16 = LO16.addImm(SOImmValV1);
698 HI16 = HI16.addImm(SOImmValV2);
699 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
700 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
701 LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());
702 HI16.addImm(Pred).addReg(PredReg).add(condCodeOp());
703 TransferImpOps(MI, LO16, HI16);
704 MI.eraseFromParent();
708 unsigned LO16Opc = 0;
709 unsigned HI16Opc = 0;
710 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) {
711 LO16Opc = ARM::t2MOVi16;
712 HI16Opc = ARM::t2MOVTi16;
714 LO16Opc = ARM::MOVi16;
715 HI16Opc = ARM::MOVTi16;
718 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg);
719 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc))
720 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
723 switch (MO.getType()) {
724 case MachineOperand::MO_Immediate: {
725 unsigned Imm = MO.getImm();
726 unsigned Lo16 = Imm & 0xffff;
727 unsigned Hi16 = (Imm >> 16) & 0xffff;
728 LO16 = LO16.addImm(Lo16);
729 HI16 = HI16.addImm(Hi16);
732 case MachineOperand::MO_ExternalSymbol: {
733 const char *ES = MO.getSymbolName();
734 unsigned TF = MO.getTargetFlags();
735 LO16 = LO16.addExternalSymbol(ES, TF | ARMII::MO_LO16);
736 HI16 = HI16.addExternalSymbol(ES, TF | ARMII::MO_HI16);
740 const GlobalValue *GV = MO.getGlobal();
741 unsigned TF = MO.getTargetFlags();
742 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16);
743 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16);
748 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
749 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
750 LO16.addImm(Pred).addReg(PredReg);
751 HI16.addImm(Pred).addReg(PredReg);
753 if (RequiresBundling)
754 finalizeBundle(MBB, LO16->getIterator(), MBBI->getIterator());
756 TransferImpOps(MI, LO16, HI16);
757 MI.eraseFromParent();
760 static void addPostLoopLiveIns(MachineBasicBlock *MBB, LivePhysRegs &LiveRegs) {
761 for (auto I = LiveRegs.begin(); I != LiveRegs.end(); ++I)
765 /// Expand a CMP_SWAP pseudo-inst to an ldrex/strex loop as simply as
766 /// possible. This only gets used at -O0 so we don't care about efficiency of the
768 bool ARMExpandPseudo::ExpandCMP_SWAP(MachineBasicBlock &MBB,
769 MachineBasicBlock::iterator MBBI,
770 unsigned LdrexOp, unsigned StrexOp,
772 MachineBasicBlock::iterator &NextMBBI) {
773 bool IsThumb = STI->isThumb();
774 MachineInstr &MI = *MBBI;
775 DebugLoc DL = MI.getDebugLoc();
776 MachineOperand &Dest = MI.getOperand(0);
777 unsigned StatusReg = MI.getOperand(1).getReg();
778 MachineOperand &Addr = MI.getOperand(2);
779 MachineOperand &Desired = MI.getOperand(3);
780 MachineOperand &New = MI.getOperand(4);
782 LivePhysRegs LiveRegs(TII->getRegisterInfo());
783 LiveRegs.addLiveOuts(MBB);
784 for (auto I = std::prev(MBB.end()); I != MBBI; --I)
785 LiveRegs.stepBackward(*I);
787 MachineFunction *MF = MBB.getParent();
788 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
789 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
790 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
792 MF->insert(++MBB.getIterator(), LoadCmpBB);
793 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
794 MF->insert(++StoreBB->getIterator(), DoneBB);
797 MachineInstrBuilder MIB =
798 BuildMI(MBB, MBBI, DL, TII->get(UxtOp), Desired.getReg())
799 .addReg(Desired.getReg(), RegState::Kill);
802 MIB.add(predOps(ARMCC::AL));
806 // ldrex rDest, [rAddr]
807 // cmp rDest, rDesired
809 LoadCmpBB->addLiveIn(Addr.getReg());
810 LoadCmpBB->addLiveIn(Dest.getReg());
811 LoadCmpBB->addLiveIn(Desired.getReg());
812 addPostLoopLiveIns(LoadCmpBB, LiveRegs);
814 MachineInstrBuilder MIB;
815 MIB = BuildMI(LoadCmpBB, DL, TII->get(LdrexOp), Dest.getReg());
816 MIB.addReg(Addr.getReg());
817 if (LdrexOp == ARM::t2LDREX)
818 MIB.addImm(0); // a 32-bit Thumb ldrex (only) allows an offset.
819 MIB.add(predOps(ARMCC::AL));
821 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
822 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
823 .addReg(Dest.getReg(), getKillRegState(Dest.isDead()))
825 .add(predOps(ARMCC::AL));
826 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
827 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
830 .addReg(ARM::CPSR, RegState::Kill);
831 LoadCmpBB->addSuccessor(DoneBB);
832 LoadCmpBB->addSuccessor(StoreBB);
835 // strex rStatus, rNew, [rAddr]
838 StoreBB->addLiveIn(Addr.getReg());
839 StoreBB->addLiveIn(New.getReg());
840 addPostLoopLiveIns(StoreBB, LiveRegs);
843 MIB = BuildMI(StoreBB, DL, TII->get(StrexOp), StatusReg);
846 if (StrexOp == ARM::t2STREX)
847 MIB.addImm(0); // a 32-bit Thumb strex (only) allows an offset.
848 MIB.add(predOps(ARMCC::AL));
850 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
851 BuildMI(StoreBB, DL, TII->get(CMPri))
852 .addReg(StatusReg, RegState::Kill)
854 .add(predOps(ARMCC::AL));
855 BuildMI(StoreBB, DL, TII->get(Bcc))
858 .addReg(ARM::CPSR, RegState::Kill);
859 StoreBB->addSuccessor(LoadCmpBB);
860 StoreBB->addSuccessor(DoneBB);
862 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
863 DoneBB->transferSuccessors(&MBB);
864 addPostLoopLiveIns(DoneBB, LiveRegs);
866 MBB.addSuccessor(LoadCmpBB);
868 NextMBBI = MBB.end();
869 MI.eraseFromParent();
873 /// ARM's ldrexd/strexd take a consecutive register pair (represented as a
874 /// single GPRPair register), Thumb's take two separate registers so we need to
875 /// extract the subregs from the pair.
876 static void addExclusiveRegPair(MachineInstrBuilder &MIB, MachineOperand &Reg,
877 unsigned Flags, bool IsThumb,
878 const TargetRegisterInfo *TRI) {
880 unsigned RegLo = TRI->getSubReg(Reg.getReg(), ARM::gsub_0);
881 unsigned RegHi = TRI->getSubReg(Reg.getReg(), ARM::gsub_1);
882 MIB.addReg(RegLo, Flags | getKillRegState(Reg.isDead()));
883 MIB.addReg(RegHi, Flags | getKillRegState(Reg.isDead()));
885 MIB.addReg(Reg.getReg(), Flags | getKillRegState(Reg.isDead()));
888 /// Expand a 64-bit CMP_SWAP to an ldrexd/strexd loop.
889 bool ARMExpandPseudo::ExpandCMP_SWAP_64(MachineBasicBlock &MBB,
890 MachineBasicBlock::iterator MBBI,
891 MachineBasicBlock::iterator &NextMBBI) {
892 bool IsThumb = STI->isThumb();
893 MachineInstr &MI = *MBBI;
894 DebugLoc DL = MI.getDebugLoc();
895 MachineOperand &Dest = MI.getOperand(0);
896 unsigned StatusReg = MI.getOperand(1).getReg();
897 MachineOperand &Addr = MI.getOperand(2);
898 MachineOperand &Desired = MI.getOperand(3);
899 MachineOperand &New = MI.getOperand(4);
901 unsigned DestLo = TRI->getSubReg(Dest.getReg(), ARM::gsub_0);
902 unsigned DestHi = TRI->getSubReg(Dest.getReg(), ARM::gsub_1);
903 unsigned DesiredLo = TRI->getSubReg(Desired.getReg(), ARM::gsub_0);
904 unsigned DesiredHi = TRI->getSubReg(Desired.getReg(), ARM::gsub_1);
906 LivePhysRegs LiveRegs(TII->getRegisterInfo());
907 LiveRegs.addLiveOuts(MBB);
908 for (auto I = std::prev(MBB.end()); I != MBBI; --I)
909 LiveRegs.stepBackward(*I);
911 MachineFunction *MF = MBB.getParent();
912 auto LoadCmpBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
913 auto StoreBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
914 auto DoneBB = MF->CreateMachineBasicBlock(MBB.getBasicBlock());
916 MF->insert(++MBB.getIterator(), LoadCmpBB);
917 MF->insert(++LoadCmpBB->getIterator(), StoreBB);
918 MF->insert(++StoreBB->getIterator(), DoneBB);
921 // ldrexd rDestLo, rDestHi, [rAddr]
922 // cmp rDestLo, rDesiredLo
923 // sbcs rStatus<dead>, rDestHi, rDesiredHi
925 LoadCmpBB->addLiveIn(Addr.getReg());
926 LoadCmpBB->addLiveIn(Dest.getReg());
927 LoadCmpBB->addLiveIn(Desired.getReg());
928 addPostLoopLiveIns(LoadCmpBB, LiveRegs);
930 unsigned LDREXD = IsThumb ? ARM::t2LDREXD : ARM::LDREXD;
931 MachineInstrBuilder MIB;
932 MIB = BuildMI(LoadCmpBB, DL, TII->get(LDREXD));
933 addExclusiveRegPair(MIB, Dest, RegState::Define, IsThumb, TRI);
934 MIB.addReg(Addr.getReg()).add(predOps(ARMCC::AL));
936 unsigned CMPrr = IsThumb ? ARM::tCMPhir : ARM::CMPrr;
937 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
938 .addReg(DestLo, getKillRegState(Dest.isDead()))
939 .addReg(DesiredLo, getKillRegState(Desired.isDead()))
940 .add(predOps(ARMCC::AL));
942 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
943 .addReg(DestHi, getKillRegState(Dest.isDead()))
944 .addReg(DesiredHi, getKillRegState(Desired.isDead()))
945 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
947 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
948 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
951 .addReg(ARM::CPSR, RegState::Kill);
952 LoadCmpBB->addSuccessor(DoneBB);
953 LoadCmpBB->addSuccessor(StoreBB);
956 // strexd rStatus, rNewLo, rNewHi, [rAddr]
959 StoreBB->addLiveIn(Addr.getReg());
960 StoreBB->addLiveIn(New.getReg());
961 addPostLoopLiveIns(StoreBB, LiveRegs);
963 unsigned STREXD = IsThumb ? ARM::t2STREXD : ARM::STREXD;
964 MIB = BuildMI(StoreBB, DL, TII->get(STREXD), StatusReg);
965 addExclusiveRegPair(MIB, New, 0, IsThumb, TRI);
966 MIB.add(Addr).add(predOps(ARMCC::AL));
968 unsigned CMPri = IsThumb ? ARM::t2CMPri : ARM::CMPri;
969 BuildMI(StoreBB, DL, TII->get(CMPri))
970 .addReg(StatusReg, RegState::Kill)
972 .add(predOps(ARMCC::AL));
973 BuildMI(StoreBB, DL, TII->get(Bcc))
976 .addReg(ARM::CPSR, RegState::Kill);
977 StoreBB->addSuccessor(LoadCmpBB);
978 StoreBB->addSuccessor(DoneBB);
980 DoneBB->splice(DoneBB->end(), &MBB, MI, MBB.end());
981 DoneBB->transferSuccessors(&MBB);
982 addPostLoopLiveIns(DoneBB, LiveRegs);
984 MBB.addSuccessor(LoadCmpBB);
986 NextMBBI = MBB.end();
987 MI.eraseFromParent();
992 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
993 MachineBasicBlock::iterator MBBI,
994 MachineBasicBlock::iterator &NextMBBI) {
995 MachineInstr &MI = *MBBI;
996 unsigned Opcode = MI.getOpcode();
1001 case ARM::TCRETURNdi:
1002 case ARM::TCRETURNri: {
1003 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
1004 assert(MBBI->isReturn() &&
1005 "Can only insert epilog into returning blocks");
1006 unsigned RetOpcode = MBBI->getOpcode();
1007 DebugLoc dl = MBBI->getDebugLoc();
1008 const ARMBaseInstrInfo &TII = *static_cast<const ARMBaseInstrInfo *>(
1009 MBB.getParent()->getSubtarget().getInstrInfo());
1011 // Tail call return: adjust the stack pointer and jump to callee.
1012 MBBI = MBB.getLastNonDebugInstr();
1013 MachineOperand &JumpTarget = MBBI->getOperand(0);
1015 // Jump to label or value in register.
1016 if (RetOpcode == ARM::TCRETURNdi) {
1019 ? (STI->isTargetMachO() ? ARM::tTAILJMPd : ARM::tTAILJMPdND)
1021 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(TCOpcode));
1022 if (JumpTarget.isGlobal())
1023 MIB.addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset(),
1024 JumpTarget.getTargetFlags());
1026 assert(JumpTarget.isSymbol());
1027 MIB.addExternalSymbol(JumpTarget.getSymbolName(),
1028 JumpTarget.getTargetFlags());
1031 // Add the default predicate in Thumb mode.
1033 MIB.add(predOps(ARMCC::AL));
1034 } else if (RetOpcode == ARM::TCRETURNri) {
1035 BuildMI(MBB, MBBI, dl,
1036 TII.get(STI->isThumb() ? ARM::tTAILJMPr : ARM::TAILJMPr))
1037 .addReg(JumpTarget.getReg(), RegState::Kill);
1040 auto NewMI = std::prev(MBBI);
1041 for (unsigned i = 1, e = MBBI->getNumOperands(); i != e; ++i)
1042 NewMI->addOperand(MBBI->getOperand(i));
1044 // Delete the pseudo instruction TCRETURN.
1050 case ARM::VMOVDcc: {
1051 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD;
1052 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc),
1053 MI.getOperand(1).getReg())
1054 .add(MI.getOperand(2))
1055 .addImm(MI.getOperand(3).getImm()) // 'pred'
1056 .add(MI.getOperand(4));
1058 MI.eraseFromParent();
1063 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr;
1064 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1065 MI.getOperand(1).getReg())
1066 .add(MI.getOperand(2))
1067 .addImm(MI.getOperand(3).getImm()) // 'pred'
1068 .add(MI.getOperand(4))
1069 .add(condCodeOp()); // 's' bit
1071 MI.eraseFromParent();
1074 case ARM::MOVCCsi: {
1075 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1076 (MI.getOperand(1).getReg()))
1077 .add(MI.getOperand(2))
1078 .addImm(MI.getOperand(3).getImm())
1079 .addImm(MI.getOperand(4).getImm()) // 'pred'
1080 .add(MI.getOperand(5))
1081 .add(condCodeOp()); // 's' bit
1083 MI.eraseFromParent();
1086 case ARM::MOVCCsr: {
1087 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsr),
1088 (MI.getOperand(1).getReg()))
1089 .add(MI.getOperand(2))
1090 .add(MI.getOperand(3))
1091 .addImm(MI.getOperand(4).getImm())
1092 .addImm(MI.getOperand(5).getImm()) // 'pred'
1093 .add(MI.getOperand(6))
1094 .add(condCodeOp()); // 's' bit
1096 MI.eraseFromParent();
1099 case ARM::t2MOVCCi16:
1100 case ARM::MOVCCi16: {
1101 unsigned NewOpc = AFI->isThumbFunction() ? ARM::t2MOVi16 : ARM::MOVi16;
1102 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1103 MI.getOperand(1).getReg())
1104 .addImm(MI.getOperand(2).getImm())
1105 .addImm(MI.getOperand(3).getImm()) // 'pred'
1106 .add(MI.getOperand(4));
1107 MI.eraseFromParent();
1112 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi;
1113 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1114 MI.getOperand(1).getReg())
1115 .addImm(MI.getOperand(2).getImm())
1116 .addImm(MI.getOperand(3).getImm()) // 'pred'
1117 .add(MI.getOperand(4))
1118 .add(condCodeOp()); // 's' bit
1120 MI.eraseFromParent();
1125 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MVNi : ARM::MVNi;
1126 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc),
1127 MI.getOperand(1).getReg())
1128 .addImm(MI.getOperand(2).getImm())
1129 .addImm(MI.getOperand(3).getImm()) // 'pred'
1130 .add(MI.getOperand(4))
1131 .add(condCodeOp()); // 's' bit
1133 MI.eraseFromParent();
1136 case ARM::t2MOVCClsl:
1137 case ARM::t2MOVCClsr:
1138 case ARM::t2MOVCCasr:
1139 case ARM::t2MOVCCror: {
1142 case ARM::t2MOVCClsl: NewOpc = ARM::t2LSLri; break;
1143 case ARM::t2MOVCClsr: NewOpc = ARM::t2LSRri; break;
1144 case ARM::t2MOVCCasr: NewOpc = ARM::t2ASRri; break;
1145 case ARM::t2MOVCCror: NewOpc = ARM::t2RORri; break;
1146 default: llvm_unreachable("unexpeced conditional move");
1148 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc),
1149 MI.getOperand(1).getReg())
1150 .add(MI.getOperand(2))
1151 .addImm(MI.getOperand(3).getImm())
1152 .addImm(MI.getOperand(4).getImm()) // 'pred'
1153 .add(MI.getOperand(5))
1154 .add(condCodeOp()); // 's' bit
1155 MI.eraseFromParent();
1158 case ARM::Int_eh_sjlj_dispatchsetup: {
1159 MachineFunction &MF = *MI.getParent()->getParent();
1160 const ARMBaseInstrInfo *AII =
1161 static_cast<const ARMBaseInstrInfo*>(TII);
1162 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo();
1163 // For functions using a base pointer, we rematerialize it (via the frame
1164 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it
1165 // for us. Otherwise, expand to nothing.
1166 if (RI.hasBasePointer(MF)) {
1167 int32_t NumBytes = AFI->getFramePtrSpillOffset();
1168 unsigned FramePtr = RI.getFrameRegister(MF);
1169 assert(MF.getSubtarget().getFrameLowering()->hasFP(MF) &&
1170 "base pointer without frame pointer?");
1172 if (AFI->isThumb2Function()) {
1173 emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1174 FramePtr, -NumBytes, ARMCC::AL, 0, *TII);
1175 } else if (AFI->isThumbFunction()) {
1176 emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1177 FramePtr, -NumBytes, *TII, RI);
1179 emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6,
1180 FramePtr, -NumBytes, ARMCC::AL, 0,
1183 // If there's dynamic realignment, adjust for it.
1184 if (RI.needsStackRealignment(MF)) {
1185 MachineFrameInfo &MFI = MF.getFrameInfo();
1186 unsigned MaxAlign = MFI.getMaxAlignment();
1187 assert (!AFI->isThumb1OnlyFunction());
1188 // Emit bic r6, r6, MaxAlign
1189 assert(MaxAlign <= 256 && "The BIC instruction cannot encode "
1190 "immediates larger than 256 with all lower "
1192 unsigned bicOpc = AFI->isThumbFunction() ?
1193 ARM::t2BICri : ARM::BICri;
1194 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(bicOpc), ARM::R6)
1195 .addReg(ARM::R6, RegState::Kill)
1196 .addImm(MaxAlign - 1)
1197 .add(predOps(ARMCC::AL))
1202 MI.eraseFromParent();
1206 case ARM::MOVsrl_flag:
1207 case ARM::MOVsra_flag: {
1208 // These are just fancy MOVs instructions.
1209 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1210 MI.getOperand(0).getReg())
1211 .add(MI.getOperand(1))
1212 .addImm(ARM_AM::getSORegOpc(
1213 (Opcode == ARM::MOVsrl_flag ? ARM_AM::lsr : ARM_AM::asr), 1))
1214 .add(predOps(ARMCC::AL))
1215 .addReg(ARM::CPSR, RegState::Define);
1216 MI.eraseFromParent();
1220 // This encodes as "MOVs Rd, Rm, rrx
1221 MachineInstrBuilder MIB =
1222 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVsi),
1223 MI.getOperand(0).getReg())
1224 .add(MI.getOperand(1))
1225 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))
1226 .add(predOps(ARMCC::AL))
1228 TransferImpOps(MI, MIB, MIB);
1229 MI.eraseFromParent();
1234 const bool Thumb = Opcode == ARM::tTPsoft;
1236 MachineInstrBuilder MIB;
1237 if (STI->genLongCalls()) {
1238 MachineFunction *MF = MBB.getParent();
1239 MachineConstantPool *MCP = MF->getConstantPool();
1240 unsigned PCLabelID = AFI->createPICLabelUId();
1241 MachineConstantPoolValue *CPV =
1242 ARMConstantPoolSymbol::Create(MF->getFunction()->getContext(),
1243 "__aeabi_read_tp", PCLabelID, 0);
1244 unsigned Reg = MI.getOperand(0).getReg();
1245 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1246 TII->get(Thumb ? ARM::tLDRpci : ARM::LDRi12), Reg)
1247 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1250 MIB.add(predOps(ARMCC::AL));
1252 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1253 TII->get(Thumb ? ARM::tBLXr : ARM::BLX));
1255 MIB.add(predOps(ARMCC::AL));
1256 MIB.addReg(Reg, RegState::Kill);
1258 MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1259 TII->get(Thumb ? ARM::tBL : ARM::BL));
1261 MIB.add(predOps(ARMCC::AL));
1262 MIB.addExternalSymbol("__aeabi_read_tp", 0);
1265 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1266 TransferImpOps(MI, MIB, MIB);
1267 MI.eraseFromParent();
1270 case ARM::tLDRpci_pic:
1271 case ARM::t2LDRpci_pic: {
1272 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic)
1273 ? ARM::tLDRpci : ARM::t2LDRpci;
1274 unsigned DstReg = MI.getOperand(0).getReg();
1275 bool DstIsDead = MI.getOperand(0).isDead();
1276 MachineInstrBuilder MIB1 =
1277 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg)
1278 .add(MI.getOperand(1))
1279 .add(predOps(ARMCC::AL));
1280 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1281 MachineInstrBuilder MIB2 =
1282 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD))
1283 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1285 .add(MI.getOperand(2));
1286 TransferImpOps(MI, MIB1, MIB2);
1287 MI.eraseFromParent();
1291 case ARM::LDRLIT_ga_abs:
1292 case ARM::LDRLIT_ga_pcrel:
1293 case ARM::LDRLIT_ga_pcrel_ldr:
1294 case ARM::tLDRLIT_ga_abs:
1295 case ARM::tLDRLIT_ga_pcrel: {
1296 unsigned DstReg = MI.getOperand(0).getReg();
1297 bool DstIsDead = MI.getOperand(0).isDead();
1298 const MachineOperand &MO1 = MI.getOperand(1);
1299 const GlobalValue *GV = MO1.getGlobal();
1301 Opcode != ARM::tLDRLIT_ga_pcrel && Opcode != ARM::tLDRLIT_ga_abs;
1303 Opcode != ARM::LDRLIT_ga_abs && Opcode != ARM::tLDRLIT_ga_abs;
1304 unsigned LDRLITOpc = IsARM ? ARM::LDRi12 : ARM::tLDRpci;
1305 unsigned PICAddOpc =
1307 ? (Opcode == ARM::LDRLIT_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1310 // We need a new const-pool entry to load from.
1311 MachineConstantPool *MCP = MBB.getParent()->getConstantPool();
1312 unsigned ARMPCLabelIndex = 0;
1313 MachineConstantPoolValue *CPV;
1316 unsigned PCAdj = IsARM ? 8 : 4;
1317 ARMPCLabelIndex = AFI->createPICLabelUId();
1318 CPV = ARMConstantPoolConstant::Create(GV, ARMPCLabelIndex,
1319 ARMCP::CPValue, PCAdj);
1321 CPV = ARMConstantPoolConstant::Create(GV, ARMCP::no_modifier);
1323 MachineInstrBuilder MIB =
1324 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LDRLITOpc), DstReg)
1325 .addConstantPoolIndex(MCP->getConstantPoolIndex(CPV, 4));
1328 MIB.add(predOps(ARMCC::AL));
1331 MachineInstrBuilder MIB =
1332 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(PICAddOpc))
1333 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1335 .addImm(ARMPCLabelIndex);
1338 MIB.add(predOps(ARMCC::AL));
1341 MI.eraseFromParent();
1344 case ARM::MOV_ga_pcrel:
1345 case ARM::MOV_ga_pcrel_ldr:
1346 case ARM::t2MOV_ga_pcrel: {
1347 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode.
1348 unsigned LabelId = AFI->createPICLabelUId();
1349 unsigned DstReg = MI.getOperand(0).getReg();
1350 bool DstIsDead = MI.getOperand(0).isDead();
1351 const MachineOperand &MO1 = MI.getOperand(1);
1352 const GlobalValue *GV = MO1.getGlobal();
1353 unsigned TF = MO1.getTargetFlags();
1354 bool isARM = Opcode != ARM::t2MOV_ga_pcrel;
1355 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel;
1356 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel;
1357 unsigned LO16TF = TF | ARMII::MO_LO16;
1358 unsigned HI16TF = TF | ARMII::MO_HI16;
1359 unsigned PICAddOpc = isARM
1360 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD)
1362 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1363 TII->get(LO16Opc), DstReg)
1364 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF)
1367 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc), DstReg)
1369 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF)
1372 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(),
1373 TII->get(PICAddOpc))
1374 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
1375 .addReg(DstReg).addImm(LabelId);
1377 MIB3.add(predOps(ARMCC::AL));
1378 if (Opcode == ARM::MOV_ga_pcrel_ldr)
1379 MIB3->setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1381 TransferImpOps(MI, MIB1, MIB3);
1382 MI.eraseFromParent();
1386 case ARM::MOVi32imm:
1387 case ARM::MOVCCi32imm:
1388 case ARM::t2MOVi32imm:
1389 case ARM::t2MOVCCi32imm:
1390 ExpandMOV32BitImm(MBB, MBBI);
1393 case ARM::SUBS_PC_LR: {
1394 MachineInstrBuilder MIB =
1395 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri), ARM::PC)
1397 .add(MI.getOperand(0))
1398 .add(MI.getOperand(1))
1399 .add(MI.getOperand(2))
1400 .addReg(ARM::CPSR, RegState::Undef);
1401 TransferImpOps(MI, MIB, MIB);
1402 MI.eraseFromParent();
1405 case ARM::VLDMQIA: {
1406 unsigned NewOpc = ARM::VLDMDIA;
1407 MachineInstrBuilder MIB =
1408 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1411 // Grab the Q register destination.
1412 bool DstIsDead = MI.getOperand(OpIdx).isDead();
1413 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
1415 // Copy the source register.
1416 MIB.add(MI.getOperand(OpIdx++));
1418 // Copy the predicate operands.
1419 MIB.add(MI.getOperand(OpIdx++));
1420 MIB.add(MI.getOperand(OpIdx++));
1422 // Add the destination operands (D subregs).
1423 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0);
1424 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1);
1425 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
1426 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
1428 // Add an implicit def for the super-register.
1429 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
1430 TransferImpOps(MI, MIB, MIB);
1431 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1432 MI.eraseFromParent();
1436 case ARM::VSTMQIA: {
1437 unsigned NewOpc = ARM::VSTMDIA;
1438 MachineInstrBuilder MIB =
1439 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc));
1442 // Grab the Q register source.
1443 bool SrcIsKill = MI.getOperand(OpIdx).isKill();
1444 unsigned SrcReg = MI.getOperand(OpIdx++).getReg();
1446 // Copy the destination register.
1447 MIB.add(MI.getOperand(OpIdx++));
1449 // Copy the predicate operands.
1450 MIB.add(MI.getOperand(OpIdx++));
1451 MIB.add(MI.getOperand(OpIdx++));
1453 // Add the source operands (D subregs).
1454 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0);
1455 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1);
1456 MIB.addReg(D0, SrcIsKill ? RegState::Kill : 0)
1457 .addReg(D1, SrcIsKill ? RegState::Kill : 0);
1459 if (SrcIsKill) // Add an implicit kill for the Q register.
1460 MIB->addRegisterKilled(SrcReg, TRI, true);
1462 TransferImpOps(MI, MIB, MIB);
1463 MIB.setMemRefs(MI.memoperands_begin(), MI.memoperands_end());
1464 MI.eraseFromParent();
1468 case ARM::VLD2q8Pseudo:
1469 case ARM::VLD2q16Pseudo:
1470 case ARM::VLD2q32Pseudo:
1471 case ARM::VLD2q8PseudoWB_fixed:
1472 case ARM::VLD2q16PseudoWB_fixed:
1473 case ARM::VLD2q32PseudoWB_fixed:
1474 case ARM::VLD2q8PseudoWB_register:
1475 case ARM::VLD2q16PseudoWB_register:
1476 case ARM::VLD2q32PseudoWB_register:
1477 case ARM::VLD3d8Pseudo:
1478 case ARM::VLD3d16Pseudo:
1479 case ARM::VLD3d32Pseudo:
1480 case ARM::VLD1d64TPseudo:
1481 case ARM::VLD1d64TPseudoWB_fixed:
1482 case ARM::VLD3d8Pseudo_UPD:
1483 case ARM::VLD3d16Pseudo_UPD:
1484 case ARM::VLD3d32Pseudo_UPD:
1485 case ARM::VLD3q8Pseudo_UPD:
1486 case ARM::VLD3q16Pseudo_UPD:
1487 case ARM::VLD3q32Pseudo_UPD:
1488 case ARM::VLD3q8oddPseudo:
1489 case ARM::VLD3q16oddPseudo:
1490 case ARM::VLD3q32oddPseudo:
1491 case ARM::VLD3q8oddPseudo_UPD:
1492 case ARM::VLD3q16oddPseudo_UPD:
1493 case ARM::VLD3q32oddPseudo_UPD:
1494 case ARM::VLD4d8Pseudo:
1495 case ARM::VLD4d16Pseudo:
1496 case ARM::VLD4d32Pseudo:
1497 case ARM::VLD1d64QPseudo:
1498 case ARM::VLD1d64QPseudoWB_fixed:
1499 case ARM::VLD4d8Pseudo_UPD:
1500 case ARM::VLD4d16Pseudo_UPD:
1501 case ARM::VLD4d32Pseudo_UPD:
1502 case ARM::VLD4q8Pseudo_UPD:
1503 case ARM::VLD4q16Pseudo_UPD:
1504 case ARM::VLD4q32Pseudo_UPD:
1505 case ARM::VLD4q8oddPseudo:
1506 case ARM::VLD4q16oddPseudo:
1507 case ARM::VLD4q32oddPseudo:
1508 case ARM::VLD4q8oddPseudo_UPD:
1509 case ARM::VLD4q16oddPseudo_UPD:
1510 case ARM::VLD4q32oddPseudo_UPD:
1511 case ARM::VLD3DUPd8Pseudo:
1512 case ARM::VLD3DUPd16Pseudo:
1513 case ARM::VLD3DUPd32Pseudo:
1514 case ARM::VLD3DUPd8Pseudo_UPD:
1515 case ARM::VLD3DUPd16Pseudo_UPD:
1516 case ARM::VLD3DUPd32Pseudo_UPD:
1517 case ARM::VLD4DUPd8Pseudo:
1518 case ARM::VLD4DUPd16Pseudo:
1519 case ARM::VLD4DUPd32Pseudo:
1520 case ARM::VLD4DUPd8Pseudo_UPD:
1521 case ARM::VLD4DUPd16Pseudo_UPD:
1522 case ARM::VLD4DUPd32Pseudo_UPD:
1526 case ARM::VST2q8Pseudo:
1527 case ARM::VST2q16Pseudo:
1528 case ARM::VST2q32Pseudo:
1529 case ARM::VST2q8PseudoWB_fixed:
1530 case ARM::VST2q16PseudoWB_fixed:
1531 case ARM::VST2q32PseudoWB_fixed:
1532 case ARM::VST2q8PseudoWB_register:
1533 case ARM::VST2q16PseudoWB_register:
1534 case ARM::VST2q32PseudoWB_register:
1535 case ARM::VST3d8Pseudo:
1536 case ARM::VST3d16Pseudo:
1537 case ARM::VST3d32Pseudo:
1538 case ARM::VST1d64TPseudo:
1539 case ARM::VST3d8Pseudo_UPD:
1540 case ARM::VST3d16Pseudo_UPD:
1541 case ARM::VST3d32Pseudo_UPD:
1542 case ARM::VST1d64TPseudoWB_fixed:
1543 case ARM::VST1d64TPseudoWB_register:
1544 case ARM::VST3q8Pseudo_UPD:
1545 case ARM::VST3q16Pseudo_UPD:
1546 case ARM::VST3q32Pseudo_UPD:
1547 case ARM::VST3q8oddPseudo:
1548 case ARM::VST3q16oddPseudo:
1549 case ARM::VST3q32oddPseudo:
1550 case ARM::VST3q8oddPseudo_UPD:
1551 case ARM::VST3q16oddPseudo_UPD:
1552 case ARM::VST3q32oddPseudo_UPD:
1553 case ARM::VST4d8Pseudo:
1554 case ARM::VST4d16Pseudo:
1555 case ARM::VST4d32Pseudo:
1556 case ARM::VST1d64QPseudo:
1557 case ARM::VST4d8Pseudo_UPD:
1558 case ARM::VST4d16Pseudo_UPD:
1559 case ARM::VST4d32Pseudo_UPD:
1560 case ARM::VST1d64QPseudoWB_fixed:
1561 case ARM::VST1d64QPseudoWB_register:
1562 case ARM::VST4q8Pseudo_UPD:
1563 case ARM::VST4q16Pseudo_UPD:
1564 case ARM::VST4q32Pseudo_UPD:
1565 case ARM::VST4q8oddPseudo:
1566 case ARM::VST4q16oddPseudo:
1567 case ARM::VST4q32oddPseudo:
1568 case ARM::VST4q8oddPseudo_UPD:
1569 case ARM::VST4q16oddPseudo_UPD:
1570 case ARM::VST4q32oddPseudo_UPD:
1574 case ARM::VLD1LNq8Pseudo:
1575 case ARM::VLD1LNq16Pseudo:
1576 case ARM::VLD1LNq32Pseudo:
1577 case ARM::VLD1LNq8Pseudo_UPD:
1578 case ARM::VLD1LNq16Pseudo_UPD:
1579 case ARM::VLD1LNq32Pseudo_UPD:
1580 case ARM::VLD2LNd8Pseudo:
1581 case ARM::VLD2LNd16Pseudo:
1582 case ARM::VLD2LNd32Pseudo:
1583 case ARM::VLD2LNq16Pseudo:
1584 case ARM::VLD2LNq32Pseudo:
1585 case ARM::VLD2LNd8Pseudo_UPD:
1586 case ARM::VLD2LNd16Pseudo_UPD:
1587 case ARM::VLD2LNd32Pseudo_UPD:
1588 case ARM::VLD2LNq16Pseudo_UPD:
1589 case ARM::VLD2LNq32Pseudo_UPD:
1590 case ARM::VLD3LNd8Pseudo:
1591 case ARM::VLD3LNd16Pseudo:
1592 case ARM::VLD3LNd32Pseudo:
1593 case ARM::VLD3LNq16Pseudo:
1594 case ARM::VLD3LNq32Pseudo:
1595 case ARM::VLD3LNd8Pseudo_UPD:
1596 case ARM::VLD3LNd16Pseudo_UPD:
1597 case ARM::VLD3LNd32Pseudo_UPD:
1598 case ARM::VLD3LNq16Pseudo_UPD:
1599 case ARM::VLD3LNq32Pseudo_UPD:
1600 case ARM::VLD4LNd8Pseudo:
1601 case ARM::VLD4LNd16Pseudo:
1602 case ARM::VLD4LNd32Pseudo:
1603 case ARM::VLD4LNq16Pseudo:
1604 case ARM::VLD4LNq32Pseudo:
1605 case ARM::VLD4LNd8Pseudo_UPD:
1606 case ARM::VLD4LNd16Pseudo_UPD:
1607 case ARM::VLD4LNd32Pseudo_UPD:
1608 case ARM::VLD4LNq16Pseudo_UPD:
1609 case ARM::VLD4LNq32Pseudo_UPD:
1610 case ARM::VST1LNq8Pseudo:
1611 case ARM::VST1LNq16Pseudo:
1612 case ARM::VST1LNq32Pseudo:
1613 case ARM::VST1LNq8Pseudo_UPD:
1614 case ARM::VST1LNq16Pseudo_UPD:
1615 case ARM::VST1LNq32Pseudo_UPD:
1616 case ARM::VST2LNd8Pseudo:
1617 case ARM::VST2LNd16Pseudo:
1618 case ARM::VST2LNd32Pseudo:
1619 case ARM::VST2LNq16Pseudo:
1620 case ARM::VST2LNq32Pseudo:
1621 case ARM::VST2LNd8Pseudo_UPD:
1622 case ARM::VST2LNd16Pseudo_UPD:
1623 case ARM::VST2LNd32Pseudo_UPD:
1624 case ARM::VST2LNq16Pseudo_UPD:
1625 case ARM::VST2LNq32Pseudo_UPD:
1626 case ARM::VST3LNd8Pseudo:
1627 case ARM::VST3LNd16Pseudo:
1628 case ARM::VST3LNd32Pseudo:
1629 case ARM::VST3LNq16Pseudo:
1630 case ARM::VST3LNq32Pseudo:
1631 case ARM::VST3LNd8Pseudo_UPD:
1632 case ARM::VST3LNd16Pseudo_UPD:
1633 case ARM::VST3LNd32Pseudo_UPD:
1634 case ARM::VST3LNq16Pseudo_UPD:
1635 case ARM::VST3LNq32Pseudo_UPD:
1636 case ARM::VST4LNd8Pseudo:
1637 case ARM::VST4LNd16Pseudo:
1638 case ARM::VST4LNd32Pseudo:
1639 case ARM::VST4LNq16Pseudo:
1640 case ARM::VST4LNq32Pseudo:
1641 case ARM::VST4LNd8Pseudo_UPD:
1642 case ARM::VST4LNd16Pseudo_UPD:
1643 case ARM::VST4LNd32Pseudo_UPD:
1644 case ARM::VST4LNq16Pseudo_UPD:
1645 case ARM::VST4LNq32Pseudo_UPD:
1649 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false); return true;
1650 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false); return true;
1651 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true); return true;
1652 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true); return true;
1654 case ARM::CMP_SWAP_8:
1656 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXB, ARM::t2STREXB,
1657 ARM::tUXTB, NextMBBI);
1659 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXB, ARM::STREXB,
1660 ARM::UXTB, NextMBBI);
1661 case ARM::CMP_SWAP_16:
1663 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREXH, ARM::t2STREXH,
1664 ARM::tUXTH, NextMBBI);
1666 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREXH, ARM::STREXH,
1667 ARM::UXTH, NextMBBI);
1668 case ARM::CMP_SWAP_32:
1670 return ExpandCMP_SWAP(MBB, MBBI, ARM::t2LDREX, ARM::t2STREX, 0,
1673 return ExpandCMP_SWAP(MBB, MBBI, ARM::LDREX, ARM::STREX, 0, NextMBBI);
1675 case ARM::CMP_SWAP_64:
1676 return ExpandCMP_SWAP_64(MBB, MBBI, NextMBBI);
1680 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) {
1681 bool Modified = false;
1683 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1685 MachineBasicBlock::iterator NMBBI = std::next(MBBI);
1686 Modified |= ExpandMI(MBB, MBBI, NMBBI);
1693 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
1694 STI = &static_cast<const ARMSubtarget &>(MF.getSubtarget());
1695 TII = STI->getInstrInfo();
1696 TRI = STI->getRegisterInfo();
1697 AFI = MF.getInfo<ARMFunctionInfo>();
1699 bool Modified = false;
1700 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E;
1702 Modified |= ExpandMBB(*MFI);
1703 if (VerifyARMPseudo)
1704 MF.verify(this, "After expanding ARM pseudo instructions.");
1708 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction
1710 FunctionPass *llvm::createARMExpandPseudoPass() {
1711 return new ARMExpandPseudo();